FORM 2
THE PATENTS ACT, 1970
(39 of 1970) & THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
[See section 10, Rule 13] DIGITAL TO ANALOG CONVERTING APPARATUS, CONTROL APPARATUS, AND CONTROL SYSTEM; MITSUBISHI ELECTRIC CORPORATION, A CORPORATION ORGANISED AND EXISTING UNDER THE LAWS OF JAPAN, WHOSE ADDRESS IS 7-3, MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO 100-8310, JAPAN
THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.2
DESCRIPTION Field [0001] The present invention relates to a digital to analog converting apparatus, a control apparatus, and a 5 control system that output a waveform pattern produced based on a plurality of digital values.
Background [0002] A facility in a factory automation (FA) field is 10 generally implemented by combining two or more types of devices. Two or more devices constituting a facility in the FA field are connected to a programmable controller that is a control apparatus in which control processing and information processing are integrated. The programmable 15 controller may sometimes output a waveform pattern produced based on a plurality of digital values to a device. [0003] The programmable controller illustrated in Patent Document 1 prepares a plurality of waveform patterns each produced based on N digital values (N is a natural number), 20 converts the digital value of the designated waveform pattern into an analog value, and outputs the analog value to the device. The programmable controller can easily implement outputting a desired waveform pattern without the need of a complicated program. 25 Citation List Patent Literature [0004] Patent Literature 1: Japanese Patent Application Laid-open No. 3-136178 30 Summary 3
Technical Problem [0005] There is a problem in that the programmable controller outputting the waveform pattern to the device is unable to change the waveform pattern in the process of outputting one waveform pattern, that is, while the device 5 is operating. The programmable controller is desired to change the waveform pattern to be outputted, in the process of outputting the waveform pattern, that is, while the device is operating. [0006] In view of the foregoing circumstances, the 10 present invention has been made, and an object of the present invention is to provide a digital analog converting apparatus (hereinafter referred to as a D/A converting apparatus) capable of changing the waveform pattern while a waveform pattern is being outputted. 15 Solution to Problem
[0007] In order to solve the above-mentioned problems and achieve the object, the present invention provides a D/A converting apparatus connected to one or more devices. 20 The D/A converting apparatus has a waveform data registration area in which a waveform pattern produced based on a plurality of digital values is stored, an execution pattern table in which information on the waveform pattern in the waveform data registration area is 25 set, an execution table in which information about the waveform pattern to be outputted to the devices is set, and an output unit. The waveform pattern is produced based on a plurality of digital values. The output unit reads the waveform pattern set in the execution table from the 30 waveform data registration area with reference to the execution pattern table and sequentially outputs the read waveform pattern to the devices. 4
Advantageous Effects of Invention [0008] The D/A converting apparatus according to the present invention has an advantageous effect that the apparatus is capable of changing the waveform pattern while 5 the waveform pattern is being outputted. Brief Description of Drawings [0009] FIG. 1 is a diagram illustrating a configuration of a 10 control system including a control apparatus according to the first embodiment. FIG. 2 is a diagram illustrating a hardware configuration of a computer of the control system illustrated in FIG. 1. 15 FIG. 3 is a diagram illustrating a waveform pattern generated by a waveform data string support tool of the computer illustrated in FIG. 2. FIG. 4 is a diagram illustrating a waveform data registration area of a shared memory of a D/A converting 20 apparatus of a PLC according to the first embodiment. FIG. 5 is a diagram illustrating an execution pattern table of the shared memory of the D/A converting apparatus of the PLC according to the first embodiment. FIG. 6 is a diagram illustrating an execution table of 25 the shared memory of the D/A converting apparatus of the PLC according to the first embodiment. FIG. 7 is a diagram illustrating a value b in FIG. 6. FIG. 8 is a diagram illustrating a change table of the shared memory of the D/A converting apparatus of the PLC 30 according to the first embodiment. FIG. 9 is a diagram illustrating a value c in FIG. 8.
FIG. 10 is a diagram illustrating a change request 5
table of the shared memory of the D/A converting apparatus of the PLC according to the first embodiment. FIG. 11 is a diagram illustrating a value d in FIG. 10. FIG. 12 is a diagram illustrating a hardware configuration of a CPU apparatus and the D/A converting 5 apparatus of the PLC according to the first embodiment. FIG. 13 is a diagram illustrating an example of an execution table in which a first waveform pattern of the D/A converting apparatus of the PLC according to the first embodiment is set. 10 FIG. 14 is a diagram illustrating an example of a change table in which a waveform pattern after the execution table illustrated in FIG. 13 is changed is set. FIG. 15 is a diagram illustrating an example of a change request table for executing the change table 15 illustrated in FIG. 14. FIG. 16 is a diagram illustrating an example of a waveform pattern to be outputted to a device when the change request table illustrated in FIG. 15 is executed. FIG. 17 is a diagram illustrating an example of an 20 execution table in which a second waveform pattern of the D/A converting apparatus of the PLC according to the first embodiment is set. FIG. 18 is a diagram illustrating an example of a change table in which a waveform pattern and the number of 25 repetitive outputs after the execution table illustrated in FIG. 17 is changed are set. FIG. 19 is a diagram illustrating an example of a change request table for executing the change table illustrated in FIG. 18. 30
FIG. 20 is a diagram illustrating an example of a waveform pattern to be outputted to a device when the change request table illustrated in FIG. 19 is executed. 6
FIG. 21 is a diagram illustrating an example of an execution table in which a third waveform pattern of the D/A converting apparatus of the PLC according to the first embodiment is set. FIG. 22 is a diagram illustrating an example of a 5 change table in which a waveform pattern and an offset address after the execution table illustrated in FIG. 21 is changed are set. FIG. 23 is a diagram illustrating an example of a change request table for executing the change table 10 illustrated in FIG. 22. FIG. 24 is a diagram illustrating an example of a waveform pattern to be outputted to a device when the change request table illustrated in FIG. 23 is executed. FIG. 25 is a diagram illustrating an example of an 15 execution table in which a second waveform pattern of the D/A converting apparatus of the PLC according to the first embodiment is set. FIG. 26 is a diagram illustrating an example of a change table in which the offset address after the 20 execution table illustrated in FIG. 25 is changed is set. FIG. 27 is a diagram illustrating an example of a change request table for executing the change table illustrated in FIG. 26. FIG. 28 is a diagram illustrating a relative address 25 of the second waveform pattern specified in FIG. 26. FIG. 29 is a diagram illustrating an example of a waveform pattern to be outputted to a device when the change request table illustrated in FIG. 27 is executed. FIG. 30 is a diagram illustrating an example of a 30 change table in which a waveform pattern after the execution table illustrated in FIG. 13 is changed is set.
FIG. 31 is a diagram illustrating an example of a 7
waveform pattern to be outputted to a device when the change request table illustrated in FIG. 15 is executed. FIG. 32 is a flowchart illustrating an operation of a calculating unit of the D/A converting apparatus of the PLC according to the first embodiment. 5 Description of Embodiments [0010] Hereinafter, a D/A converting apparatus, a control apparatus, and a control system according to an embodiment of the present invention will be described in 10 detail with reference to the drawings. The invention is not necessarily limited by the embodiment. [0011] First Embodiment. FIG. 1 is a diagram illustrating a configuration of a control system including a control apparatus according to a 15 first embodiment. A control system 1 constitutes a facility in the FA field, and as illustrated in FIG. 1, the control system 1 includes a plurality of devices 2a, 2b, 2c, and 2d installed in the facility, a control apparatus 3 connected to the devices 2a, 2b, 2c, and 2d, and a computer 20 4 that is a transmitting apparatus connected to the control apparatus 3. In the first embodiment, the control system 1 has four devices that are the devices 2a, 2b, 2c, and 2d, but the number of devices is not limited to four. In the first embodiment, the devices 2a, 2b, 2c, and 2d are each a 25 driving device that carries out an operation thereof, such as a switch, regulating valve, solenoid valve, motor, or pump installed in the facility.
[0012] The computer 4 generates a control program to be executed by the control apparatus 3 and transmits the 30 control program to the control apparatus 3. The control apparatus 3 executes the control program to control the devices 2a, 2b, 2c, and 2d. In the first embodiment, the 8
control apparatus 3 is a programmable logic controller (PLC) and is hereinafter referred to as a PLC 3. The programmable logic controller is defined by a Japan Industrial Standard (JIS) B 3502:2011. [0013] FIG. 2 is a diagram illustrating a hardware 5 configuration of a computer of the control system illustrated in FIG. 1. The computer 4 according to the first embodiment is a computer that executes a computer program and includes a central processing unit (CPU) 41, a random access memory (RAM) 42, a read only memory (ROM) 43, 10 a storage apparatus 44, an input apparatus 45, a display apparatus 46, and a communication interface 47, as illustrated in FIG. 2. The CPU 41, the RAM 42, the ROM 43, the storage apparatus 44, the input apparatus 45, the display apparatus 46, and the communication interface 47 15 are connected to one another via a bus B. [0014] The CPU 41 executes the computer programs stored in the ROM 43 and the storage apparatus 44 while using the RAM 42 as a work area. In the first embodiment, the computer program stored in the ROM 43 is a basic 20 input/output system (BIOS) or a unified extensible firmware interface (UEFI), but the computer program to be stored in the ROM 43 is not limited to the BIOS or the UEFI. In the first embodiment, the computer programs stored in the storage apparatus 44 are an operating system program and an 25 engineering tool program, but the computer programs to be stored in the storage apparatus 44 are not limited to the operating system program and the engineering tool program. In the first embodiment, the storage apparatus 44 is a solid state drive (SSD) or a hard disk drive (HDD), but the 30 storage apparatus 44 is not limited to the SSD or the HDD.
[0015] The input apparatus 45 receives a manipulation input from the user. In the first embodiment, the input 9
apparatus 45 is a keyboard or a mouse but not limited to the keyboard or the mouse. The display apparatus 46 displays characters and images. In the first embodiment, the display apparatus 46 is a liquid crystal display apparatus but not limited to the liquid crystal display 5 apparatus. The communication interface 47 communicates with the PLC 3. [0016] As illustrated in FIG. 1, the computer 4 includes an engineering tool 48 having a function of operating the PLC 3 and editing a program and a waveform data string 10 support tool 49. FIG. 3 is a diagram illustrating waveform patterns generated by a waveform data string support tool of the computer illustrated in FIG. 2. The waveform data string support tool 49 is implemented by the CPU 41 executing the computer program stored in the storage 15 apparatus 44 using the RAM 42 as a work area. [0017] The waveform data string support tool 49 generates waveform patterns WP illustrated in FIG. 3 which is outputted to the devices 2a, 2b, 2c, and 2d by the PLC 3. The waveform pattern WP generated by the waveform data 20 string support tool 49 is stored in the storage apparatus 44. The waveform data string support tool 49 is executed by the CPU 41 using the RAM 42 as a work area and thereby transmits the generated waveform pattern WP to the PLC 3. The waveform pattern WP is generated in accordance with an 25 operation based on at least one of the engineering tool 48 and the waveform data string support tool 49 which are stored in the storage apparatus 44 in the CPU 41. The waveform patterns WP represent the operations of the devices 2a, 2b, 2c, and 2d with the lapse of time. 30
[0018] The waveform pattern WP is produced based on a plurality of digital values. In the digital values constituting the waveform pattern WP, an address indicating 10
an elapsed time from the start of the waveform pattern WP is determined, and a value indicating a magnitude of the operation is determined. In the digital value, the magnitude of the operation is defined by a predetermined number of gradations. In the first embodiment, the 5 computer 4 is adapted, for the waveform patterns WP, to produce a first waveform pattern WP1, a second waveform pattern WP2, a third waveform pattern WP3, a fourth waveform pattern WP4, a fifth waveform pattern WP5, and a P-th waveform pattern WPP (P is a natural number larger 10 than 5), as illustrated in FIG. 3 and stores the waveform patterns. The first waveform pattern WP1 has 13000 digital values, the second waveform pattern WP2 has 7000 digital values, the third waveform pattern WP3 has 13000 digital values, the fourth waveform pattern WP4 has 8000 digital 15 values, the fifth waveform pattern WP5 has 5000 digital values, and the P-th waveform pattern WPP has NP digital values. Hereinafter, the waveform patterns which can be specified are referred to as the first waveform pattern WP1, the second waveform pattern WP2, the third waveform pattern 20 WP3, the fourth waveform pattern WP4, the fifth waveform pattern WP5, and the P-th waveform pattern WPP, and a waveform pattern which is unable to be specified is referred to simply as a waveform pattern WP.
[0019] As illustrated in FIG. 1, the PLC 3 includes a 25 digital/analog (D/A) converting apparatus 5 connected to one or more devices 2a, 2b, 2c, and 2d, and a CPU apparatus 12. The D/A converting apparatus 5 and the CPU apparatus 12 are communicably connected to each other by a communication bus B3. The D/A converting apparatus 5 and 30 the CPU apparatus 12 include bus interfaces 51 and 121 to which the communication bus B3 is connected, respectively. The CPU apparatus 12 includes a peripheral apparatus 11
interface 125 communicably connected to the computer 4. [0020] In the first embodiment, the D/A converting apparatus 5 includes a calculating unit 6 that executes an internally stored program, a shared memory 7 serving as a storage unit that stores the waveform patterns WP therein, 5 an internal memory 61 used as a temporary storage area, a D/A (digital to analog) converting unit 8 serving as a converting unit that converts a digital value transmitted from the calculating unit 6 into an analog value, a counter 9, an analog output interface 52, and a trigger signal 10 input interface 53, as illustrated in FIG. 1. [0021] The D/A converting apparatus 5 has the analog output interface 52 for establishing a connection with the four devices 2a, 2b, 2c, and 2d, the interface 52 covering a first analog output channel CH1, a second analog output 15 channel CH2, a third analog output channel CH3, and a fourth analog output channel CH4 retained therein, but the present embodiment is not limited to the four analog output channels CH1, CH2, CH3, and CH4. In this specification, when it is necessary to distinguish the first analog output 20 channel CH1, the second analog output channel CH2, the third analog output channel CH3, and the fourth analog output channel CH4 from one another, they are indicated by CH1, CH2, CH3, and CH4, respectively. The calculating unit 6 of the D/A converting apparatus 5 sequentially outputs 25 any one of the waveform patterns WP1, WP2, WP3, WP4, and WP5 to the analog output channels CH1, CH2, CH3, and CH4 to control the devices 2a, 2b, 2c, and 2d.
[0022] The D/A converting apparatus 5 has a trigger signal input interface 53 for receiving trigger signals 30 outputted from the four devices 2a, 2b, 2c, and 2d, the interface 53 covering a first channel trigger CHT1, a second channel trigger CHT2, a third channel trigger CHT3, 12
and a fourth channel trigger CHT4 retained therein, but the present embodiment is not limited to the four channel triggers CHT1, CHT2, CHT3, and CHT4. In this specification, hereinafter, when it is necessary to distinguish the first channel trigger CHT1, the second channel trigger CHT2, the 5 third channel trigger CHT3, and the fourth channel trigger CHT4 from one another, they are indicated by CHT1, CHT2, CHT3, and CHT4, respectively. Upon detecting a rising edge of the trigger signal outputted from each of the devices 2a, 2b, 2c, and 2d, the calculating unit 6 of the D/A 10 converting apparatus 5 starts a waveform outputting operation. Further, upon detecting a falling edge of the trigger signal during execution of the waveform outputting operation, the calculating unit 6 of the D/A converting apparatus 5 stops the waveform outputting operation. The 15 calculating unit 6 of the D/A converting apparatus 5 receives a waveform output start request and a waveform output stop request even in dependence upon an operation performed by the user on the engineering tool 48 on the computer 4 or execution of a ladder program which is 20 produced by the engineering tool 48 and written in the CPU apparatus 12. [0023] The shared memory 7 is a temporary storage area that is freely readable and writable by both the calculating unit 6 of the D/A converting apparatus 5 and 25 the CPU apparatus 12. As illustrated in FIG. 1, the shared memory 7 includes a waveform output parameter area 70 and a waveform data registration area 71, and further includes an execution pattern table 72, an execution table 73, a change table 74, and a change request table 75 which are necessary 30 for changing an output waveform during execution of the waveform outputting operation.
[0024] In the waveform output parameter area 70 in the 13
shared memory 7, a parameter for setting a waveform output period and a parameter for designating an analog value to be outputted during stoppage of the waveform output are written by any one of the engineering tool 48 and the waveform data string support tool 49 via the CPU apparatus 5 12. The waveform output period means a period in which an address of the digital value of the waveform pattern WP is updated and is specified by a multiple of a D/A conversion period. [0025] In the waveform data registration area 71 in the 10 shared memory 7, the waveform patterns WP1, WP2, WP3, WP4, and WP5 are written in the shared memory 7 by any one of the engineering tool 48 and the waveform data string support tool 49 of the computer 4 via the CPU apparatus 12 as illustrated in FIG. 4, but the present embodiment is not 15 limited to the five waveform patterns WP. Referring to FIG. 4, the waveform data registration area 71 stores a maximum of 50000 pieces of information, but the present embodiment is not limited to 50000 pieces of information. In other words, the waveform data registration area 71 is defined as 20 a region in which the digital values constituting each waveform pattern WP is stored in advance in accordance with an output time series in which the digital value is desired to be outputted.
[0026] In the first embodiment, as illustrated in FIG. 4, 25 the waveform data registration area 71 stores therein the first waveform pattern WP1, the second waveform pattern WP2, the third waveform pattern WP3, the fourth waveform pattern WP4, and the fifth waveform pattern WP5. In the first embodiment, the waveform data registration area 71 stores 30 therein the digital value of the first waveform pattern WP1 in order from an address "0" which is a first address, and stores therein the digital value of the second waveform 14
pattern WP2 in order from an address "13000" next to an address "12999" which is the last address in which the digital value of the first waveform pattern WP1 is stored. The waveform data registration area 71 stores therein the digital value of the third waveform pattern WP3 in order 5 from an address "20000" next to an address "19999" which is the last address in which the digital value of the second waveform pattern WP2 is stored, and stores therein the digital value of the fourth waveform pattern WP4 in order from an address "33000" next to an address "32999" which is 10 the last address in which the digital value of the third waveform pattern WP3 is stored. The waveform data registration area 71 stores therein the digital value of the fifth waveform pattern WP5 in order from an address "41000" next to an address "40999" which is the last 15 address in which the digital value of the fourth waveform pattern WP4 is stored, and an area from an address "46000" next to an address "45999" which is the last address in which the digital value of the fifth waveform pattern WP5 is stored to an address "49999" which is the last address 20 is in an empty state in which no information is stored. The address "0", the address "12999", the address "13000", the address "19999", the address "20000", the address "32999", the address "33000", the address "40999", the address "41000", the address "45999", the address "46000", 25 and the address "49999" are absolute addresses of the storage area of the waveform data registration area 71.
[0027] In the first embodiment, the storage area of the waveform data registration area 71 in which the first waveform pattern WP1 is stored is managed on the basis of 30 relative addresses from an address "0" to an address "12999" from the absolute address "0" as a point of origin. The storage area of the waveform data registration area 71 15
in which the second waveform pattern WP2 is stored is managed on the basis of relative addresses from an address "0" to an address "6999" from the absolute address "13000" as a point of origin. The storage area of the waveform data registration area 71 in which the third waveform 5 pattern WP3 is stored is managed on the basis of relative addresses from an address "0" to an address "12999" from the absolute address "20000" as a point of origin. The storage area of the waveform data registration area 71 in which the fourth waveform pattern WP4 is stored is managed 10 on the basis of relative addresses from an address "0" to an address "7999" from the absolute address "33000" as a point of origin. The storage area of the waveform data registration area 71 in which the fifth waveform pattern WP5 is stored is managed on the basis of relative addresses 15 from an address "0" to an address "4999" from the absolute address "41000" as a point of origin. [0028] FIG. 5 is a diagram illustrating an execution pattern table of the shared memory of the D/A converting apparatus of the PLC according to the first embodiment. 20 The execution pattern table 72 is composed of a first absolute address and the number of digital values, which are information for each waveform pattern WP in the waveform data registration area 71. Since there is no waveform pattern WP in which the number of digital values 25 is 0, the calculating unit 6 sequentially searches each waveform pattern WP, and can recognize a terminating end of the execution pattern table 72 at a time point at which the number of digital values is 0. The execution pattern table 72 is written into the shared memory 7 via the CPU 30 apparatus 12 by any one of the engineering tool 48 and the waveform data string support tool 49 on the computer 4.
[0029] In the first embodiment, the execution pattern 16
table 72 specifies the first absolute address "0" of the storage area of the waveform data registration area 71 of the first waveform pattern WP1 and the number "13000" of digital values of the first waveform pattern WP1. The execution pattern table 72 specifies the first absolute 5 address "13000" of the storage area of the waveform data registration area 71 of the second waveform pattern WP2 and the number "7000" of digital values of the second waveform pattern WP2. The execution pattern table 72 specifies the first absolute address "20000" of the storage area of the 10 waveform data registration area 71 of the third waveform pattern WP3 and the number "13000" of digital values of the third waveform pattern WP3. The execution pattern table 72 specifies the first absolute address "33000" of the storage area of the waveform data registration area 71 of the 15 fourth waveform pattern WP4 and the number "8000" of digital values of the fourth waveform pattern WP4. The execution pattern table 72 specifies the first absolute address "41000" of the storage area of the waveform data registration area 71 of the fifth waveform pattern WP5 and 20 the number "5000" of digital values of the fifth waveform pattern WP5.
[0030] In the execution pattern table 72, an address "0" used in the execution pattern table 72 is assigned to the first absolute address "0" of the storage area of the 25 waveform data registration area 71 of the first waveform pattern WP1, and an address "1" used in the execution pattern table 72 is assigned to the number "13000" of digital values of the first waveform pattern WP1. In the execution pattern table 72, an address "2" used in the 30 execution pattern table 72 is assigned to the first absolute address "13000" of the storage area of the waveform data registration area 71 of the second waveform 17
pattern WP2, and an address "3" used in the execution pattern table 72 is assigned to the number "7000" of digital values of the second waveform pattern WP2. In the execution pattern table 72, an address "4" used in the execution pattern table 72 is assigned to the first 5 absolute address "20000" of the storage area of the waveform data registration area 71 of the third waveform pattern WP3, and an address "5" used in the execution pattern table 72 is assigned to the number "13000" of digital values of the third waveform pattern WP3. In the 10 execution pattern table 72, an address "6" used in the execution pattern table 72 is assigned to the first absolute address "33000" of the storage area of the waveform data registration area 71 of the fourth waveform pattern WP4, and an address "7" used in the execution 15 pattern table 72 is assigned to the number "8000" of digital values of the fourth waveform pattern WP4. In the execution pattern table 72, an address "8" used in the execution pattern table 72 is assigned to the first absolute address "41000" of the storage area of the 20 waveform data registration area 71 of the fifth waveform pattern WP5, and an address "9" used in the execution pattern table 72 is assigned to the number "5000" of digital values of the fifth waveform pattern WP5.
[0031] The calculating unit 6 of the D/A converting 25 apparatus 5 is also an output unit that outputs the waveform pattern WP to the devices 2a, 2b, 2c, and 2d through the analog output I/F 52, and stores a value obtained by adding the first absolute address of each waveform pattern WP and the number of digital values set in 30 the execution pattern table 72 and then subtracting one therefrom, in the internal memory 61 as an end absolute address of each waveform pattern WP. The calculating unit 18
6 of the D/A converting apparatus 5 stores a value obtained by subtracting one from the number of digital values of each waveform pattern WP in the internal memory 61 as an end relative address of each waveform pattern WP. The calculating unit 6 refers to the waveform pattern WP stored 5 in the waveform data registration area 71 using both the absolute address and the relative address. As an example, as shown in FIG. 4, the end absolute address "19999" of the second waveform pattern WP2 stored in the waveform data registration area 71 is obtained based on the first 10 absolute address "13000" of the storage area of the waveform data registration area 71 of the second waveform pattern WP2 and the number "7000" of digital values of the second waveform pattern WP2, which are set in the execution pattern table 72 as shown in VII of FIG. 5. Similarly, the 15 end relative address "6999" is obtained.
[0032] FIG. 6 is a diagram illustrating the execution table of the shared memory of the D/A converting apparatus of the PLC according to the first embodiment. FIG. 7 is a diagram illustrating a value b in FIG. 6. The execution 20 table 73 illustrated in FIG. 6 has information for managing the execution state of the waveform pattern WP to be outputted for each of the analog output channels CH1, CH2, CH3, and CH4 set therein. In the execution table 73, a default value is written from the waveform data string 25 support tool 49 on the computer 4 into the shared memory 7 via the CPU apparatus 12. The execution state of the output of the waveform pattern WP can be changed for each of the analog output channels CH1, CH2, CH3, and CH4 by rewriting the values of the execution table 73 based on an 30 operation of the engineering tool 48 on the computer 4 or based on execution of a ladder program in accordance with states or changes of the devices 2a, 2b, 2c, and 2d, the 19
ladder program being created by the engineering tool 48 and written in the CPU apparatus 12.
[0033] In the first embodiment, the execution table 73 specifies numbers for waveform patterns WP to be outputted to the analog output channels CH1, CH2, CH3, and CH4 and 5 the number of repetitive outputs of the waveform pattern WP as information about the waveform patterns WP. In the first embodiment, in the execution table 73, "1" is set as a value “a” when the first waveform pattern WP1 is specified, "2" is set as a value “a” when the second 10 waveform pattern WP2 is specified, "3" is set as a value “a” when the third waveform pattern WP3 is specified, "4" is set as a value “a” when the fourth waveform pattern WP4 is specified, and "5" is set as a value “a” when the fifth waveform pattern WP5 is specified. As shown in FIG. 7, 15 when the number of times of repetitive output is a finite number of times, the execution table 73 specifies, as a value “b” for setting the number of repetitive outputs, a finite number of times itself between 1 and a natural number N each of which is a finite number of times itself. 20 In the execution table 73, as the value “b” for setting the number of repetitive outputs, as illustrated in FIG. 7, when the number of repetitive outputs is infinite, "-1" is set for example, but a value for setting infinite repetition is not necessarily limited to "-1". The 25 calculating unit 6 can determine the waveform pattern WP to be outputted with reference to the content of the execution table 73 set for each of the analog output channels CH1, CH2, CH3, and CH4, read the corresponding waveform pattern WP from the waveform data registration area 71 with 30 reference to the information managed by the execution pattern table 72, and perform output control of the waveform pattern WP by the number of times desired by the 20
user. [0034] FIG. 8 is a diagram illustrating the change table of the shared memory of the D/A converting apparatus of the PLC according to the first embodiment. FIG. 9 is a diagram illustrating a value c in FIG. 8. The change table 74 5 specifies changing information for each of the analog output channels CH1, CH2, CH3, and CH4, the changing information being used to change information managed in the execution table 73 without stopping the output of the waveform pattern WP while the output of the waveform 10 pattern WP is being executed. In the change table 74, when the user desires to change the execution state of the waveform output in accordance with the states or changes of the devices 2a, 2b, 2c, and 2d, a value is set for each of the analog output channels CH1, CH2, CH3, and CH4 based on 15 operation of the engineering tool 48 on the computer 4 or based on execution of a ladder program produced by the engineering tool 48 and written in the CPU apparatus 12. [0035] In the first embodiment, the change table 74 is composed of four items that are a targeted waveform pattern 20 WP, the number of repetitive outputs of the waveform pattern WP, an offset address of the targeted waveform pattern WP, and a change timing at which the three pieces of change information mentioned earlier should be reflected in the execution table 73. 25
[0036] In the first embodiment, the change table 74 specifies similarly to the execution table 73, a number of the waveform pattern WP as the value “a” for determining a newly-targeted waveform pattern WP for each of the analog output channels CH1, CH2, CH3, and CH4. In the change 30 table 74, similarly to the execution table 73, as the value “b” for setting the number of repetitive outputs of the newly-targeted waveform pattern WP, when the number of 21
repetitive outputs is a finite number of times, a finite number itself is set, and when the number of repetitive outputs is an infinite number, "-1" is set. [0037] In the change table 74, the relative address of the digital value which is outputted first after the 5 transition among a plurality of digital values constituting the waveform pattern WP after the transition is set as the value for setting the offset address. By setting the offset address, the D/A converting apparatus 5 can start the output from an arbitrary address of the waveform 10 pattern WP. [0038] In the change table 74, as a change timing at which the information set in the change table 74 is to be reflected in the execution table 73, selection can be made between a timing at which a change request is issued or a 15 timing at which the output of the waveform pattern WP being outputted is completed, and what is selected is determined by a value “c” for setting the change timing. As the value "c" of the change timing, as illustrated in FIG. 9, "0" is set when it is the timing at which the internally stored 20 program receives the change request, and "1" is set when it is the timing at which the output of the waveform pattern WP being outputted is completed, but the value "c" for the change timing is not necessarily limited to "0" and "1".
[0039] In the first embodiment, in the change table 74, 25 an address "0" used in the change table 74 is assigned to the value “a” for setting the changed waveform pattern WP to be outputted to the first analog output channel CH1, an address "1" used in the change table 74 is assigned to the value “b” for setting the number of repetitive outputs of 30 the waveform pattern WP to the first analog output channel CH1, an address "2" used in the change table 74 is assigned to the relative address for setting the offset address of 22
the waveform pattern WP to be outputted to the first analog output channel CH1, and an address "3" used in the change table 74 is assigned to the value “c” for setting the change timing of the first analog output channel CH1. In the change table 74, an address "4" used in the change 5 table 74 is assigned to the value “a” for setting the changed waveform pattern WP to be outputted to the second analog output channel CH2, an address "5" used in the change table 74 is assigned to the value “b” for setting the number of repetitive outputs of the waveform pattern WP 10 to the second analog output channel CH2, an address "6" used in the change table 74 is assigned to the relative address for setting the offset address of the waveform pattern WP to be outputted to the second analog output channel CH2, and an address "7" used in the change table 74 15 is assigned to the value “c” for setting the change timing of the second analog output channel CH2. In the change table 74, an address "8" used in the change table 74 is assigned to the value “a” for setting the changed waveform pattern WP to be outputted to the third analog output 20 channel CH3, an address "9" used in the change table 74 is assigned to the value “b” for setting the number of repetitive outputs of the waveform pattern WP to the third analog output channel CH3, an address "10" used in the change table 74 is assigned to the relative address for 25 setting the offset address of the waveform pattern WP to be outputted to the third analog output channel CH3, and an address "11" used in the change table 74 is assigned to the value c for setting the change timing of the third analog output channel CH3. In the change table 74, an address 30 "12" used in the change table 74 is assigned to the value “a” for setting the changed waveform pattern WP to be outputted to the fourth analog output channel CH4, an 23
address "13" used in the change table 74 is assigned to the value “b” for setting the number of repetitive outputs of the waveform pattern WP to the fourth analog output channel CH4, an address "14" used in the change table 74 is assigned to the relative address for setting the offset 5 address of the waveform pattern WP to be outputted to the fourth analog output channel CH4, and an address "15" used in the change table 74 is assigned to the value c for setting the change timing of the fourth analog output channel CH4. 10
[0040] FIG. 10 is a diagram illustrating the change request table of the shared memory of the D/A converting apparatus of the PLC according to the first embodiment. FIG. 11 is a diagram illustrating a value “d” in FIG. 10. The change request table 75 is used to store change 15 information in the change table 74 and thereafter to notify the D/A converting apparatus 5 of the content of the change request for each of the analog output channels CH1, CH2, CH3, and CH4, when the user desires to change the execution state of the output of the waveform pattern WP managed by 20 the execution table 73. In the change request table 75, when the user wishes to change the execution state of the output of the waveform pattern WP in accordance with the states or the changes of the devices 2a, 2b, 2c, and 2d, the value is set for each of the analog output channels CH1, 25 CH2, CH3, and CH4 based on operation of the engineering tool 48 on the computer 4 or based on the execution of the ladder program which is generated by the engineering tool 48 and written in the CPU apparatus 12. In short, the change request table 75 is used to specify whether or not 30 the information set in the execution table 73 needs to be changed to the change information set in the change table 74. 24
[0041] In the change request table 75, as illustrated in FIG. 10, the value “d” for setting the request content is set for each of the analog output channels CH1, CH2, CH3, and CH4. In the change request table 75, as illustrated in FIG. 11, "0" is set as the value d for setting the request 5 content when there is no request to change. In the change request table 75, "1" is set as the value “d” for setting the request content when the waveform pattern WP set in the execution table 73 is changed to the waveform pattern WP set in the change table 74. In the change request table 75, 10 "2" is set as the value “d” for setting the request content when the number of repetitive outputs set in the execution table 73 is changed to the number of repetitive outputs set in the change table 74. In the change request table 75, "3" is set as the value “d” for setting the request content 15 when the output of the waveform pattern WP is started from the offset address set in the change table 74. In the change request table 75, "4" is set as the value “d” for setting the request content when the waveform pattern WP and the number of repetitive outputs are changed. In the 20 change request table 75, "5" is set as the value “d” for setting the request content when the waveform pattern WP is changed and the output of the waveform pattern WP is started from the relative address set in the offset address. In the change request table 75, "6" is set as the value “d” 25 for setting the request content when the number of repetitive outputs is changed and the output of the waveform pattern WP is started from the relative address specified in the offset address. In the change request table 75, "7" is set as the value “d” for setting the 30 request content when the waveform pattern WP and the number of repetitive outputs are changed and the output of the waveform pattern WP is started from the relative address 25
set in the offset address. Such a subdivision of the value of the request as described above is intended to beforehand branch the internally stored program of the D/A converting apparatus 5 according to the subdivision thereby to increase a processing speed when the change request is 5 received. However, the present invention is not limited to the example having the values of "0", "1", "2", "3", "4", "5", "6", and "7" of the value “d” of the request, their respective request contents allocated thereto, or a requesting manner. 10 [0042] The internally stored program executed by the calculating unit 6 of the D/A converting apparatus 5 constantly monitors the change of the value “d” of the change request table 75 during the execution of the output of the waveform pattern WP. A timing when the value “d” is 15 changed from "0" to "non 0" for each of the analog output channels CH1, CH2, CH3, and CH4 of the change request table 75 means a timing at which the user issues the change request. The calculating unit 6 recognizes the change content with reference to the change table 74 of the analog 20 output channels CH1, CH2, CH3 and CH4 in which the value “d” has been "non 0", and changes the execution state of the output of the waveform pattern WP to an "in operation" by rewriting contents of the analog output channels CH1, CH2, CH3, and CH4 in which the value “d” of the change 25 request table 75 has been "non 0" at a timing designated by the change timing of the change table 74. Note that a timing when the value “d” is changed from "0" to "non 0" for each of the analog output channels CH1, CH2, CH3, and CH4 of the change request table 75 means a timing at which 30 the change request table 75 is updated from "unchanged" to "need to change".
[0043] In the first embodiment, in the change request 26
table 75, an address "0" used in the change request table 75 is assigned to the value “d” for setting the request content of the first analog output channel CH1, and an address "1" used in the change request table 75 is assigned to the value “d” for setting the request content of the 5 second analog output channel CH2. In the change request table 75, an address "2" used in the change request table 75 is assigned to the value “d” for setting the request content of the third analog output channel CH3, and an address "3" used in the change request table 75 is assigned 10 to the value “d” for setting the request content of the fourth analog output channel CH4. [0044] The CPU apparatus 12 is connected to both the D/A converting apparatus 5 and the computer 4. The CPU apparatus 12 includes an internal memory 122 that stores an 15 internally stored program, a calculating unit 123 that executes the internally stored program stored in the internal memory 122, and an external memory interface 124. The external memory interface 124 can be connected to an external storage medium storing apparatus that stores 20 information in an external storage medium (not illustrated) storing information readable by the computer 4. [0045] Next, hardware configurations of the CPU apparatus 12 and the D/A converting apparatus 5 of the PLC 3 will be described. FIG. 12 is a diagram illustrating 25 hardware configurations of the CPU apparatus and the D/A converting apparatus of the PLC according to the first embodiment. In FIG. 12, parts equal to those in FIG. 1 are denoted by the same reference symbols.
[0046] As illustrated in FIG. 12, the CPU apparatus 12 30 includes a micro-processing unit (MPU) 123, a memory 122, a communication circuit 128, a peripheral apparatus interface 125, a bus interface 121, and an external storage apparatus 27
interface 124. The MPU 123, the memory 122, the communication circuit 128, the peripheral apparatus interface 125, the bus interface 121, and the external storage apparatus interface 124 are connected to one another via an internal bus B12. 5 [0047] A function of the calculating unit 123 of the CPU apparatus 12 is implemented by the MPU 123 reading and executing the internally stored program. The internally stored program is implemented by software, firmware, or a combination of software and firmware. A function of the 10 internal memory 122 of the CPU apparatus 12 is implemented by the memory 122. The memory 122 is constituted by a non-volatile semiconductor memory or a volatile semiconductor memory. A RAM, a ROM, a flash memory, an erasable programmable read only memory (EPROM), or an electrically 15 erasable programmable read only memory (EEPROM) can be used as the non-volatile semiconductor memory or the volatile semiconductor memory. Further, the memory 122 may be constituted by at least one of a magnetic disk, an optical disk, and a magneto-optical disk. 20
[0048] The communication circuit 128 is implemented by a single circuit, a composite circuit, a programmed processor, a parallel-programmed processor, an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a combination of two or more thereof. A 25 function of the external memory interface 124 of the CPU apparatus 12 is implemented by the external storage apparatus interface 124. In the first embodiment, the external storage medium in which information is stored by the external storage medium storing apparatus connected to 30 the external storage apparatus interface 124 is constituted by a secure digital (SD) memory card or a static random access memory (SRAM) cassette, but the external storage 28
medium is not limited to the SD memory card or the SRAM cassette and may be constituted by a magnetic disk, an optical disk, or a magneto-optical disk. [0049] As illustrated in FIG. 12, the D/A converting apparatus 5 includes an MPU 6 having the internal memory 61 5 and the counter 9 built-in, a memory 7, a communication circuit 56, a bus interface 51, an analog output interface 52, a trigger signal input interface 53, a D/A converter 8. The MPU 6, the memory 7, the communication circuit 56, the bus interface 51, the analog output interface 52, the 10 trigger signal input interface 53 and the D/A converter 8 are connected to one another via an internal bus B5. [0050] A function of the calculating unit 6 of the D/A converting apparatus 5 is implemented by the MPU 6 reading and executing an internally stored program. The internally 15 stored program is implemented by software, firmware, or a combination of software and firmware. Functions of the waveform output parameter area 70, the waveform data registration area 71, the execution pattern table 72, the execution table 73, the change table 74, and the change 20 request table 75 of the shared memory 7 of the D/A converting apparatus 5 are implemented by the memory 7. The memory 7 is constituted by a non-volatile semiconductor memory or a volatile semiconductor memory. A RAM, a ROM, a flash memory, an EPROM, or an EEPROM can be used as the 25 non-volatile semiconductor memory or the volatile semiconductor memory. Further, the memory 7 may be constituted by at least one of a magnetic disk, an optical disk, and a magneto-optical disk.
[0051] A function of the communication circuit 56 is 30 implemented by a single circuit, a composite circuit, a programmed processor, a parallel-programmed processor, an ASIC, an FPGA, or a combination of two or more of them. A 29
function of the D/A converting unit 8 of the D/A converting apparatus 5 is implemented by the D/A converter 8. [0052] The counter 9 of the D/A converting apparatus 5 counts an internal control clock of the calculating unit 6, and when a value set as a D/A conversion period is reached, 5 the counter 9 issues an interrupt signal to the calculating unit 6. By allocating an internally stored program for waveform output to the interrupt signal in advance, the calculating unit 6 can execute the output of the waveform pattern WP on the basis of the D/A conversion period. 10 Further, when the trigger signal is inputted from the external devices 2a, 2b, 2c, and 2d via the trigger signal input interface 53, the D/A converting apparatus 5 can start the output of the waveform pattern WP for each of the analog output channels CH1, CH2, CH3, and CH4 without going 15 through the CPU apparatus 12 at a timing at which the rising edge of this trigger signal is detected. Further, the D/A converting apparatus 5 can stop the output of the waveform pattern WP for each of the analog output channels CH1, CH2, CH3, and CH4 without going through the CPU 20 apparatus 12 at a timing at which the falling edge of the trigger signal is detected while the output of the waveform pattern WP is being executed.
[0053] Next, a process in which the D/A converting apparatus 5 of the PLC 3 according to the first embodiment 25 changes the waveform pattern WP during the output of the waveform pattern WP will be described. Changing the waveform pattern WP by the D/A converting apparatus 5 during the output of the waveform pattern WP means at least one of changing the waveform pattern WP itself to be 30 outputted by the D/A converting apparatus 5 during the output of the waveform pattern WP and changing an output digital value of the waveform pattern WP to a digital value 30
of a relative address other than a digital value of a next relative address. First, a process of changing only the waveform pattern WP by the D/A converting apparatus 5 of the PLC 3 according to the first embodiment will be described. FIG. 13 is a diagram illustrating an example of 5 an execution table that defines the first waveform pattern of the D/A converting apparatus of the PLC according to the first embodiment. FIG. 14 is a diagram illustrating an example of the change table for setting the waveform pattern after the execution table illustrated in FIG. 13 is 10 changed. FIG. 15 is a diagram illustrating an example of the change request table for executing the change table illustrated in FIG. 14. FIG. 16 is a diagram illustrating an example of the waveform pattern outputted to the device when the change request table illustrated in FIG. 15 is 15 executed. [0054] The D/A converting apparatus 5 of the PLC 3 repeatedly outputs the first waveform pattern WP1 to the first analog output channel CH1 until "10000" is reached as set in the execution table 73 illustrated in FIG. 13. 20
[0055] Then, based on a user’s operation of the engineering tool 48 on the computer 4 or based on the execution of a ladder program which is generated by the engineering tool 48 and written in the CPU apparatus 12, the change table 74 for changing the waveform pattern WP of 25 the first analog output channel CH1 to the second waveform pattern WP2 is written as illustrated in FIG. 14, and thereafter the value “d” for setting the request content of the first analog output channel CH1 of the change request table 75 is changed from "0" to "1" as shown in FIG. 15. 30 Here, a value "1" of the value “d” corresponds to a request to change the waveform pattern WP, that is, means that the requested change content refers only to the waveform 31
pattern WP. Further, since the change timing is "0", the requested change timing is "when a request to change is made." Immediately after detecting the change in the change request table 75 illustrated in FIG. 15, the calculating unit 6 of the D/A converting apparatus 5 5 changes the waveform pattern WP of the first analog output channel CH1 of the execution table 73 from the first waveform pattern WP1 to the second waveform pattern WP2 on the basis of the request content and rewrites a read target address of the first analog output channel CH1 to "0" of 10 the relative address. Thereafter, the calculating unit 6 returns the change request table 75 to "0", and then continues the output control of the waveform pattern WP. FIG. 16 illustrates the change in the analog output waveform and illustrates that the output waveform pattern 15 WP varies greatly at a moment at which the change request is received.
[0056] Similarly, in the state in which the first waveform pattern WP1 is repeatedly outputted to the first analog output channel CH1 until "10000" is reached as set 20 by the execution table 73 illustrated in FIG. 13, the change table 74 is written as illustrated in FIG. 30, and then the calculating unit 6 changes the value “d” for setting the request content of the first analog output channel CH1 of the change request table 75 from "0" to "1" 25 as illustrated in FIG. 15. Here, since the change timing is "1", the requested change timing is "when output is completed". Upon detecting the change in the change request table 75 illustrated in FIG. 15, the calculating unit 6 of the D/A converting apparatus 5 saves the content 30 of the change table 74 in the internal memory 61, reserves the change of the execution table 73, then returns the change request table 75 to "0", and continues the output 32
control of the waveform pattern WP. Thereafter, when the relative address of the first waveform pattern WP1 of the first analog output channel CH1 reaches a final address, and the output of the first waveform pattern WP1 is all completed, the calculating unit 6 reads the content saved 5 in the internal memory 61, and executes rewriting of the reserved execution table 73. FIG. 31 is a figure illustrating the change in the analog output waveform, which shows that even after the change request is received, the output of the first waveform pattern WP1 is continued, 10 and after the terminal end of the relative address is reached, transition to the second waveform pattern WP2 is performed. As described above, the D/A converting apparatus 5 can suppress a large output variation and perform smooth transition by causing the waveform pattern 15 WP to be completed to the end and then connecting the waveform pattern WP to the next waveform pattern WP. [0057] As described above, the D/A converting apparatus 5 is configured to be able to select either "when a request to change is made" or "when output is completed" for the 20 change timing in the change table 74, whereby for example, the D/A converting apparatus 5 can select "when a request to change is made" in a case where emphasis is on responsiveness of the control change due to a situation change or the like of the devices 2a, 2b, 2c, and 2d and 25 select "when output is completed" in another case where emphasis is on the burden on the devices 2a, 2b, 2c, and 2d to minimize output variation at the time of control change, so that the flexible control change satisfying the need of the user is realized. 30
[0058] Next, a process of changing the waveform pattern WP and the number of repetitive outputs by the D/A converting apparatus 5 of the PLC 3 according to the first 33
embodiment will be described. FIG. 17 is a diagram illustrating an example of the execution table in which the second waveform pattern of the D/A converting apparatus of the PLC according to the first embodiment is set. FIG. 18 is a diagram illustrating an example of the change table 5 for setting the waveform pattern and the number of repetitive outputs after the execution table illustrated in FIG. 17 is changed. FIG. 19 is a diagram illustrating an example of the change request table for executing the change table illustrated in FIG. 18. FIG. 20 is a diagram 10 illustrating an example of the waveform pattern outputted to the device when the change request table illustrated in FIG. 19 is executed. [0059] The D/A converting apparatus 5 of the PLC 3 repeatedly outputs the second waveform pattern WP2 to the 15 first analog output channel CH1 an indefinite number of times as set by the execution table 73 illustrated in FIG. 17.
[0060] Then, based on a user’s operation of the engineering tool 48 on the computer 4 or based on execution 20 of a ladder program generated by the engineering tool 48 and written in the CPU apparatus 12, the waveform pattern WP of the first analog output channel CH1 is changed to the fourth waveform pattern WP4 and the setting value for changing the number of repetitive outputs to "1" is written 25 in the change table 74 as illustrated in FIG. 18, and thereafter the value “d” for setting the request content of the first analog output channel CH1 of the change request table 75 is changed from "0" to "4". Here, the value "4" of the value “d” corresponds to the change request of "the 30 waveform pattern plus the number of repetitive outputs", that is, indicates that the requested change content is the change of the waveform pattern WP and the change of the 34
number of repetitive outputs. Further, since the change timing is "0", the requested change timing is "when a request to change is made." Immediately after detecting the change in the change request table 75 illustrated in FIG. 19, the calculating unit 6 of the D/A converting 5 apparatus 5 changes the waveform pattern WP of the first analog output channel CH1 of the execution table 73 from the second waveform pattern WP2 to the fourth waveform pattern WP4 on the basis of the request content thereof and further rewrites the number of repetitive outputs of the 10 first analog output channel CH1 from "-1" indicating the infinite repetition to "1". Further, the calculating unit 6 changes the read target address of the first analog output channel CH1 to "0" of the relative address. Thereafter, the calculating unit 6 returns the change 15 request table 75 to "0", and then continues the output control of the waveform pattern WP. FIG. 20 is a figure illustrating the change in the analog output waveform, which illustrates that the control makes a transition from the infinite repetition to a single output, and the output 20 is completed. As described above, by simultaneously changing the waveform pattern WP and the number of repetitive outputs, the D/A converting apparatus 5 can easily achieve emergency stop control, for example, when an abnormality occurs. 25
[0061] Next, a process in which the D/A converting apparatus 5 of the PLC 3 according to the first embodiment changes the waveform pattern WP and performs the output from the digital value of the relative address set as the offset address among the digital values of the changed 30 waveform pattern WP will be described. FIG. 21 is a diagram illustrating an example of the execution table for setting the third waveform pattern of the D/A converting 35
apparatus of the PLC according to the first embodiment. FIG. 22 is a diagram illustrating an example of the change table for setting the waveform pattern and the offset address after the execution table illustrated in FIG. 21 is changed. FIG. 23 is a diagram illustrating an example of 5 the change request table for executing the change table illustrated in FIG. 22. FIG. 24 is a diagram illustrating an example of the waveform pattern outputted to the device when the change request table illustrated in FIG. 23 is executed. 10 [0062] The D/A converting apparatus 5 of the PLC 3 repeatedly outputs the third waveform pattern WP3 to the first analog output channel CH1 an infinite number of times as set by the execution table 73 illustrated in FIG. 21.
[0063] Then, based on a user’s operation of the 15 engineering tool 48 on the computer 4 or based on the execution of a ladder program which is generated by the engineering tool 48 and written in the CPU apparatus 12, the waveform pattern WP of the first analog output channel CH1 is changed to the second waveform pattern WP2, and 20 "5250" among the digital values of the second waveform patterns WP2 is written in the change table 74 as the offset address for designating the relative address to be used for output first as illustrated in FIG. 22, and then the value “d” for setting the request content of the first 25 analog output channel CH1 of the change request table 75 is changed from "0" to "5". Here, the value "5" of the value “d” corresponds to a change request for "the waveform pattern plus the offset address", that is, indicates that the requested change content has the change of the waveform 30 pattern WP and the offset designation for the relative address at which the output thereof starts. Further, since the change timing is "0", the requested change timing 36
corresponds to "when a request to change is made." Immediately after detecting the change in the change request table 75 illustrated in FIG. 23, based on its request content, the calculating unit 6 of the D/A converting apparatus 5 changes the waveform pattern WP of 5 the first analog output channel CH1 of the execution table 73 from the third waveform pattern WP3 to the second waveform pattern WP2, and further sets "5250" of the relative address as the read target address of the first analog output channel CH1. Thereafter, the calculating 10 unit 6 returns the change request table 75 to "0", and then continues the output control of the waveform pattern WP. FIG. 24 is a figure illustrating the change in the analog output waveform, which illustrates that after the change request is received, the output starts from the relative 15 address "5250" of the third waveform pattern WP3, and after the remaining 1750 pieces of data are outputted, the calculating unit 6 comes back to the relative address "0", and continues the infinite repetitive output. As described above, since the D/A converting apparatus 5 can start the 20 output from an arbitrary address when the waveform pattern WP is switched to a new waveform pattern WP, it is possible to bypass an unnecessary output easily in accordance with the states or the changes of the devices 2a, 2b, 2c, and 2d.
[0064] Next, description is given for a process in which 25 the D/A converting apparatus 5 of the PLC 3 according to the first embodiment performs the output from the digital value of the relative address set as the offset address among the digital values of the waveform patterns WP without changing the waveform pattern WP. FIG. 25 is a 30 diagram illustrating an example of the execution table for setting the second waveform pattern of the D/A converting apparatus of the PLC according to the first embodiment. 37
FIG. 26 is a diagram illustrating an example of the change table for setting the offset address after the execution table illustrated in FIG. 25 is changed. FIG. 27 is a diagram illustrating an example of the change request table for executing the change table illustrated in FIG. 26. FIG. 5 28 is a diagram illustrating the relative address of the second waveform pattern defined in FIG. 26. FIG. 29 is a diagram illustrating an example of the waveform pattern outputted to the device when the change request table illustrated in FIG. 27 is executed. 10 [0065] The D/A converting apparatus 5 of the PLC 3 repeatedly outputs the second waveform pattern WP2 to the first analog output channel CH1 an infinite number of times as set by the execution table 73 illustrated in FIG. 25.
[0066] Then, based on a user’s operation of the 15 engineering tool 48 on the computer 4 or based on the execution of a ladder program which is generated by the engineering tool 48 and written in the CPU apparatus 12, the second waveform pattern WP2 of the first analog output channel CH1 is maintained without change and "5250" is 20 written in the change table 74 as the offset address for designating the relative address to be used for output first among the digital values of the second waveform patterns WP2 as illustrated in FIG. 26, and then the value “d” for setting the request content of the first analog 25 output channel CH1 of the change request table 75 is changed from "0" to "3". Here, the value "3" of the value “d” corresponds to the change request for only the "offset address", that is, indicates that the requested change content refers to the address transition within the 30 waveform pattern WP being currently outputted. Further, since the change timing is "0", the requested change timing is "when a request to change is made." Immediately after 38
detecting the change in the change request table 75 illustrated in FIG. 27, the calculating unit 6 of the D/A converting apparatus 5 changes the read target address of the first analog output channel CH1 to "5250" of the relative address on the basis of the request content. 5 Thereafter, the calculating unit 6 returns the change request table 75 to "0", and then continues the output control of the waveform pattern WP. FIG. 28 represents the address transition in the waveform pattern, and FIG. 29 illustrates the change in the analog output waveform. FIG. 10 29 illustrates that after the calculating unit 6 receives the change request, the calculating unit 6 immediately goes to the relative address "5250" of the second waveform pattern WP2 and continues the output, and after the remaining 1750 pieces of data are outputted, the 15 calculating unit 6 coms back to the relative address "0" and continues the infinite repetitive output. As described above, the D/A converting apparatus 5 can freely go to an arbitrary address in the waveform pattern WP without stopping the output of the currently executed waveform 20 pattern WP. [0067] Next, an operation of the calculating unit 6 of the D/A converting apparatus 5 of the PLC 3 according to the first embodiment will be described. FIG. 32 is a flowchart illustrating the operation of the calculating 25 unit of the D/A converting apparatus of the PLC according to the first embodiment.
[0068] In the D/A converting apparatus 5, the waveform pattern WP is written from the waveform data string support tool 49 on the computer 4 into the waveform data 30 registration area 71 of the shared memory 7 by way of the CPU apparatus 12, and the execution pattern table 72 and the execution table 73 having default values are written. 39
Further, the execution table 73 is rewritten as necessary based on a user’s operation of the engineering tool 48 on the computer 4 or based on the execution of a ladder program which is generated by the engineering tool 48 and written in the CPU apparatus 12. Thereafter, based on a 5 user’s operation of the engineering tool 48 on the computer 4 or based on the execution of the ladder program which is generated by the engineering tool 48 and written in the CPU apparatus 12, the analog output channels CH1, CH2, CH3, and CH4 whose waveform patterns WP are desired to be outputted 10 are set in a D/A conversion allowance condition. Further, upon receiving the output start request of the waveform pattern WP based on detection of the rising edge of the corresponding trigger signal input from the external devices 2a, 2b, 2c, or 2d in response to the analog output 15 channels CH1, CH2, CH3, and CH4 set in the D/A conversion allowance condition or a user’s operation of the engineering tool 48 on the computer 4 or the execution of a ladder program which is generated by the engineering tool 48 and written in the CPU apparatus 12, the calculating 20 unit 6 of the D/A converting apparatus 5 starts the output control of the waveform pattern WP.
[0069] When the analog output channels CH1, CH2, CH3, and CH4 are set in the D/A conversion allowance condition, the counter 9 counts the internal control clock of the 25 calculating unit 6, and the interrupt signal is generated to the calculating unit 6 at a time point at which and end of the D/A conversion period is reached for each of the analog output channels CH1, CH2, CH3, and CH4 set in the D/A conversion allowance condition. FIG. 32 is a flowchart 30 representing an overview of the operation of an interrupt program allocated to the interrupt signal. In the interrupt program, the calculating unit 6 of the D/A 40
converting apparatus 5 first determines whether or not the waveform output operation for outputting the waveform pattern WP is being executed (step ST1). If the waveform output operation for outputting the waveform pattern WP is determined not to be being executed (step ST1: No), the 5 calculating unit 6 of the D/A converting apparatus 5 ends the flowchart illustrated in FIG. 32. [0070] If the waveform output operation for the waveform patterns WP of a corresponding one of the analog output channels CH1, CH2, CH3, and CH4 are determined to be being 10 executed (step ST1: Yes), the calculating unit 6 of the D/A converting apparatus 5 then determines whether or not the output stop request for the waveform pattern WP is received (step ST2). The calculating unit 6 of the D/A converting apparatus 5 receives the output stop request of the 15 waveform pattern WP based on detection of the falling edge of the corresponding trigger signal inputted from the external device 2a, 2b, 2c, or 2d, based on a user’s operation of the engineering tool 48 on the computer 4, or based on the execution of a ladder program which is 20 generated by the engineering tool 48 and written in the CPU apparatus 12.
[0071] If any output stop request for the waveform patterns WP of the corresponding analog output channels CH1, CH2, CH3, and CH4 is determined not to be received (step 25 ST2: No), the calculating unit 6 of the D/A converting apparatus 5 then refers to the values of the corresponding one of the analog output channels CH1, CH2, CH3, and CH4 of the change request table 75. The calculating unit 6 of the D/A converting apparatus 5 determines whether no change 30 request is made or not, that is, whether or not the value “d” for setting the request content of the change request table 75 is "0" (step ST3). If it is determined that there 41
is no change request, that is, if the value “d” for setting the request content of the corresponding one of the analog output channels CH1, CH2, CH3, and CH4 of the change request table 75 is determined to be "0" (step ST3: No), the calculating unit 6 of the D/A converting apparatus 5 5 proceeds to step ST9. [0072] Further, if the output stop request for the waveform pattern WP of the corresponding one of the analog output channels CH1, CH2, CH3, and CH4 is determined to be received (step ST2: Yes), the calculating unit 6 of the D/A 10 converting apparatus 5 stops the output of the waveform pattern WP (step ST17), and ends processing of the flowchart illustrated in FIG. 32.
[0073] If it is determined that there is a change request, that is, if the value “d” for setting the request 15 content of the corresponding one of the analog output channels CH1, CH2, CH3, and CH4 of the change request table 75 is determined to be other than "0" (step ST3: Yes), the calculating unit 6 of the D/A converting apparatus 5 refers to the setting content of the corresponding one of the 20 analog output channels CH1, CH2, CH3, and CH4 of the change table 74 (step ST4). Then, the calculating unit 6 of the D/A converting apparatus 5 determines whether or not the timing for performing the change set in the change table 74 is "when a request to change is made" (step ST5). If it is 25 determined that the change timing is "when a change request is received", that is, "when a current process is performed" (step ST5: Yes), the calculating unit 6 of the D/A converting apparatus 5 immediately changes the execution table 73 in accordance with the requested content 30 (step ST6). At this time, the calculating unit 6 of the D/A converting apparatus 5 sets the relative address to the value of the "offset address" as the read target address 42
when the offset address is designated, and sets the relative address to "0" when the offset address is not designated. When the change timing is determined to be "when the output of the waveform pattern WP is completed" (step ST5: No), the calculating unit 6 of the D/A 5 converting apparatus 5 saves the change content set in the change table 74 in the internal memory 61, and then sets a change reservation flag of the execution table 73 to ON (step ST7). Thereafter, the calculating unit 6 of the D/A converting apparatus 5 returns the value “d” of the 10 corresponding one of the analog output channels CH1, CH2, CH3, and CH4 of the change request table 75 to "0" (step ST8) and proceeds to step ST9. [0074] The calculating unit 6 of the D/A converting apparatus 5 reads the digital value for the waveform 15 pattern WP set in the execution table 73 of the corresponding one of the analog output channels CH1, CH2, CH3, and CH4 from the read target address of the waveform data registration area 71 with reference to the execution pattern table 72. The calculating unit 6 of the D/A 20 converting apparatus 5 transmits the read digital value to the D/A converting unit 8, and outputs the analog value to any of the devices 2a, 2b, 2c, and 2d connected to the corresponding one of the analog output channels CH1, CH2, CH3, and CH4 (step ST9). Each of the devices 2a, 2b, 2c, 25 and 2d receives the analog value changed by the D/A converting unit 8 and operates in accordance with the received analog value.
[0075] The calculating unit 6 of the D/A converting apparatus 5 determines whether or not an end of the next 30 waveform output period is reached (step ST10). The next waveform output period said herein is a period until the read target address is updated to an address directly after 43
the current address, and in the first embodiment, the waveform output period is a value set in the waveform output parameter area 70 in advance based on an user’s operation of the engineering tool 48 on the computer 4 or based on the execution of a ladder program which is 5 generated by the engineering tool 48 and written in the CPU apparatus 12, wherein the waveform output period is a value set as a multiple of the D/A conversion period. The calculating unit 6 of the D/A converting apparatus 5 continues to transmit the same digital value in each D/A 10 conversion period within the waveform output period. The calculating unit 6 of the D/A converting apparatus 5 counts the D/A conversion period within the program illustrated in FIG. 32, and if the unit 6 determines that an end of the next waveform output period is not reached, that is, if the 15 value obtained by counting the D/A conversion period is determined not to reach the multiple of the D/A conversion period set in advance (step ST10: No), the calculating unit 6 ends the flowchart illustrated in FIG. 32.
[0076] If an end of the next waveform output period is 20 determined to be reached, that is, if the value obtained by counting the D/A conversion period is determined to reach the multiple of the preset D/A conversion period (step ST10: Yes), the calculating unit 6 of the D/A converting apparatus 5 then determines whether or not the read target 25 address reaches the final address of the waveform pattern WP (step ST11). If the read target address is determined not to reach the final address of the waveform pattern WP (step ST11: No), the calculating unit 6 of the D/A converting apparatus 5 updates the read target address of 30 the digital value of the waveform pattern WP of the corresponding one of the analog output channels CH1, CH2, CH3, and CH4 to the next address (step ST14), and ends 44
processing of the flowchart illustrated in FIG. 32. [0077] If the read target address is determined to reach the final address of the waveform pattern WP (step ST11: Yes), the calculating unit 6 of the D/A converting apparatus 5 then determines whether or not the change 5 reservation flag of the execution table 73 is ON (step ST12). When the change reservation flag of the execution table 73 is determined to be ON (step ST12: Yes), the calculating unit 6 of the D/A converting apparatus 5 rewrites the information of the corresponding one of the 10 analog output channels CH1, CH2, CH3, and CH4 of the execution table 73 using the change content previously saved in the internal memory 61 (step ST15), and ends processing of the flowchart illustrated in FIG. 32. [0078] When the change reservation flag of the execution 15 table 73 is determined not to be ON (step ST12: No), the calculating unit 6 of D/A converting apparatus 5 then determines whether or not a number for the current output for the repetitive outputs is a last number (step ST13). When a number for the current output for the repetitive 20 outputs is determined to be a last number (step ST13: Yes), the calculating unit 6 of the D/A converting apparatus 5 stops the waveform output operation (step ST17), and ends processing of the flowchart illustrated in FIG. 32. When a number for the current output for the repetitive outputs is 25 determined not to be a last number (step ST13: No), the calculating unit 6 of D/A converting apparatus 5 updates the read target address of the digital value of the waveform pattern WP of the corresponding one of the analog output channels CH1, CH2, CH3, and CH4 to the next address 30 (step ST16), and ends processing of the flowchart illustrated in FIG. 32.
[0079] According to the D/A converting apparatus 5 45
according to the first embodiment, the shared memory 7 includes: the waveform data registration area 71 that stores therein the waveform pattern WP; the execution pattern table 72 for setting the information on the waveform pattern WP; and the execution table 73 for setting 5 the information about the waveform pattern WP to be outputted to the devices 2a, 2b, 2c, and 2d via the first analog output channel CH1, the second analog output channel CH2, the third analog output channel CH3, and the fourth analog output channel CH4. In the D/A converting apparatus 10 5, the execution table 73 specifies the value “a” for setting the waveform pattern WP to be outputted to the devices 2a, 2b, 2c, and 2d via the first analog output channel CH1, the second analog output channel CH2, the third analog output channel CH3, and the fourth analog 15 output channel CH4. Therefore, when the waveform pattern WP set in the execution table 73 is outputted, the apparatus 5 can read the waveform pattern WP from the waveform data registration area 71 with reference to the execution pattern table 72. 20
[0080] Further, in the D/A converting apparatus 5, the execution table 73 specifies the value “a” for setting the waveform patterns WP to be outputted to the devices 2a, 2b, 2c, and 2d via the first analog output channel CH1, the second analog output channel CH2, the third analog output 25 channel CH3, and the fourth analog output channel CH4. Therefore, the waveform patterns WP to be outputted to the devices 2a, 2b, 2c, and 2d via the first analog output channel CH1, the second analog output channel CH2, the third analog output channel CH3, and the fourth analog 30 output channel CH4 are managed by the execution table 73. As a result, the D/A converting apparatus 5 can immediately change the waveform patterns WP to be outputted to the 46
devices 2a, 2b, 2c, and 2d via the first analog output channel CH1, the second analog output channel CH2, the third analog output channel CH3, and the fourth analog output channel CH4 by changing the execution table 73, and can change the waveform pattern WP while the waveform 5 pattern WP is in the process of its output. [0081] In addition, the D/A converting apparatus 5 of the first embodiment has the change table 74 in which the change information for changing the information set in the execution table 73 is set and the change request table 75 10 used to determine whether to change to the change information or not. By virtue of this, the D/A converting apparatus 5 can immediately change the waveform pattern WP by generating the change table 74 and the change request table 75 while the waveform pattern WP is in the process of 15 its output. [0082] According to the D/A converting apparatus 5 of the first embodiment, the change information set in the change table 74 is the offset address. As a result, the D/A converting apparatus 5 can change the waveform pattern 20 WP while the waveform pattern WP is in the process of its output, and further can output the changed waveform pattern WP from the digital value of an arbitrary relative address. [0083] According to the D/A converting apparatus 5 of the first embodiment, the change information set in the 25 change table 74 is the change timing. As a result, the D/A converting apparatus 5 can change the waveform pattern WP while the waveform pattern WP is in the process of its output, and further can set the change timing to an arbitrary timing. 30
[0084] According to the D/A converting apparatus 5 of the first embodiment, since the change timing is a timing at which the change request is set, it is possible to 47
change the waveform pattern WP at an arbitrary timing while the waveform pattern WP is being outputted. [0085] According to the D/A converting apparatus 5 of the first embodiment, since the change timing is a timing at which the output of the currently outputted waveform 5 pattern WP is completed, it is possible to output the currently outputted waveform pattern WP until an end of the pattern. Further, according to the D/A converting apparatus 5 of the first embodiment, since the change timing can be selected from a timing at which the change 10 request is set and a timing at which the output of the waveform pattern WP is completed, it is possible to make a wide variety of changes of the waveform patterns WP. [0086] According to the D/A converting apparatus 5 of the first embodiment, since the change information set in 15 the change table 74 sets the number of repetitive outputs of the changed waveform pattern WP, it is possible to output the changed waveform pattern WP as many times as necessary. [0087] Since the D/A converting apparatus 5 of the first 20 embodiment has the calculating unit 6 that outputs the digital value of the read target address for each output period and accordingly updates the read target address, it is possible continuously output the digital value for each output period. 25
[0088] Since the D/A converting apparatus 5 according to the first embodiment has the D/A converting unit 8 that converts the digital value outputted by the calculating unit 6 into the analog value, it is possible to output the analog value which continuously varies to the devices 2a, 30 2b, 2c, and 2d via the first analog output channel CH1, the second analog output channel CH2, the third analog output channel CH3, and the fourth analog output channel CH4, and 48
it is possible to smoothly perform the operations of the devices 2a, 2b, 2c, and 2d via the first analog output channel CH1, the second analog output channel CH2, the third analog output channel CH3, and the fourth analog output channel CH4. 5 [0089] Since the PLC 3 according to the first embodiment has the D/A converting apparatus 5 described above, it is possible to immediately change the waveform patterns WP to be outputted to the devices 2a, 2b, 2c, and 2d via the first analog output channel CH1, the second analog output 10 channel CH2, the third analog output channel CH3, and the fourth analog output channel CH4 by changing the execution table 73, thereby making it possible to change the waveform pattern WP while the waveform pattern WP is in the process of its output. 15 [0090] The configuration described in the above embodiment is an example of the content of the present invention and can be combined with other publicly known techniques, and partially omitted and/or modified without departing from the scope of the present invention. 20 Reference Signs List [0091] 1 control system; 2a, 2b, 2c, 2d device; 3 PLC (control apparatus); 4 computer (transmitting apparatus); 5 digital to analog converting apparatus (D/A converting 25 apparatus); 6 calculating unit (output unit); 8 D/A converting unit (converting unit); 12 CPU apparatus; 71 waveform data registration area; 72 execution pattern table; 73 execution table; 74 change table; 75 change request table; WP, WP1, WP2, WP3, WP4, WP5 waveform 30 pattern. 49
WE CLAIM: 1. A digital to analog converting apparatus connected to one or more devices, the apparatus comprising: a waveform data registration area in which a waveform 5 pattern produced based on a plurality of digital values is stored; an execution pattern table in which information on the waveform pattern in the waveform data registration area is set; 10 an execution table in which information about the waveform pattern to be outputted to the devices is set; and an output unit to read the waveform pattern set in the execution table from the waveform data registration area with reference to the execution pattern table and output 15 the read waveform pattern to the devices. 2. The digital to analog converting apparatus according to claim 1, comprising: a change table in which change information for 20 changing the information set in the execution table is set; and a change request table used to determine whether or not the information set in the execution table should be changed to the change information set in the change table. 25 3. The digital to analog converting apparatus according to claim 2, wherein the change information set in the change table used to set a digital value to be outputted first after the change among a plurality of digital values 30 constituting the changed waveform pattern.
4. The digital to analog converting apparatus according 50
to claim 2, wherein the change information set in the change table is used to set a timing for changing information set in the execution table. 5. The digital to analog converting apparatus according 5 to claim 4, wherein the timing for changing is a timing at which the change request table is updated from "unchanged" to "change needed". 6. The digital to analog converting apparatus according 10 to claim 4, wherein the timing for changing is a timing at which outputting of the currently outputted waveform pattern is completed. 7. The digital to analog converting apparatus according 15 to claim 2, wherein the change information set in the change table is used to set the number of outputs of the waveform pattern. 8. The digital to analog converting apparatus according 20 to any one of claims 1 to 7, wherein information on the waveform pattern set by the execution pattern table includes a first address of the waveform pattern in the waveform data registration area and the number of the digital values. 25 9. The digital to analog converting apparatus according to any one of claims 1 to 8, wherein the output unit is a calculating unit to read a digital value of a read target address in the waveform pattern set in the execution table 30 for each output period to output the digital value to the devices and update the read target address. 51
10. The digital to analog converting apparatus according to claim 9, comprising a converting unit to convert the digital value outputted by the calculating unit into an analog value. 5 11. A control apparatus comprising: the digital to analog converting apparatus according to any one of claims 1 to 10; and a CPU apparatus connected to both the digital to analog converting apparatus and a transmitting apparatus to 10 transmit the waveform pattern to the digital to analog converting apparatus. 12. A control system comprising: the control apparatus according to claim 11; and 15 the transmitting apparatus.