Claims:1. A device (100) for attenuating radio frequency (RF) signals, said device comprising:
an input port (102) for receiving an input signal to be attenuated;
an output port (104) for outputting the attenuated output signal;
a reference path located between the input port (102) and the output port (104) and an attenuation path between the input port (102) and the output port (104); and
a plurality of attenuator stages (106-1 to 106-5) configured to selectively alter the attenuation of the applied signal, wherein each attenuator stage being assigned a corresponding bit position, the plurality of attenuator stages interconnected by transmission lines that is extended between the input port and the output port to obtain impedance matching in operating band and achieve lower insertion phase shift.

2. The device as claimed in claim 1, wherein the plurality of attenuator stages (106-1 to 106-5) comprise five attenuator stages with corresponding bits that is implemented using modified-T topology (108), wherein the plurality of attenuator stages provides maximum attenuation range of 15.5dB and minimum resolvable level of 0.5dB.

3. The device as claimed in claim 1, the device is fabricated using 0.25 µm E/D mode high performance GaAs pseudomorphic high electron mobility transistor (pHEMT) process with die size of less than 1.5 mm X 1.60 mm in X and Y respectively.

4. The device as claimed in claim 1, wherein wideband impedance matching in the operating band is obtained with the transmission lines coupled between the plurality of attenuator stages (106-1 to 106-5), wherein at the input port and the output port, better than 10dB return losses is obtained over the operating band for all attenuation states, where the operating band is L to Ku band.

5. The device as claimed in claim 1, wherein one or more FETs having a source, gate, and drain coupled to each attenuator stage to obtain better input third order intercept point, wherein peripheries of the one or more FETs is optimized by considering the tradeoff between output third order intercept point (OIP3) and wideband performance.

6. The device as claimed in claim 1, wherein the device comprises one or more resistors of predetermined resistance values coupled to the gate of each FET to obtain less insertion loss without degrading switching speed and to prevent RF signal leakage, wherein the peripheries of the one or more FETs in the reference path and gate resistors are optimized to obtain typical insertion loss in the operating band lesser than 5.5 dB.

7. The device as claimed in claim 1, wherein the device comprises one or more capacitors (302-1, 302-2) of predetermined value that is coupled to the source and the drain of each FET in the attenuation path of each attenuator stage to ensure both drain and source are maintained at same potential and to obtain current consumption of less than 0.1mA, wherein said one or more capacitors less than 12pF incorporated with additional metal 0 layer that aids in miniaturization of the die.

8. The device as claimed in claim 1, wherein the device comprises series resistors (202-1, 202-2) of predetermined resistance values coupled to RF–DC crossover areas (200) to avoid RF signal coupling to DC lines.

9. The device as claimed in claim 1, wherein the device comprises ESD protection circuitry (400) that comprises ESD diodes coupled to control lines and supply line of the device to avoid damage due to electrostatic discharge.

10. The device as claimed in claim 1, wherein the ESD diodes comprises less than six forward biased diodes from the control line to ground and less than three reverse biased diodes from the control line to ground.
, Description:TECHNICAL FIELD
[0001] The present disclosure relates, in general, to electronic attenuators, and more specifically, relates to a multi-octave low power consumption digital attenuator with a minimal phase shift.

BACKGROUND
[0002] Electronic devices often incorporate controllable attenuation devices and/or components for varying the amount of resistance applied to electronic signals such as radio frequency (RF) signals. Such attenuators are used in, among other things, automatic gain control circuits, position locating systems, telephone systems, television systems, and microwave circuit applications.
[0003] Modern miniaturized systems require compact, lightweight and low-cost components with a high yield rate. Attenuators are one of the fundamental components in RADAR, measurement and communication systems. The attenuator is mainly used for amplitude control applications such as damage protection and linearity adjustment. In phased array applications, the attenuator helps to control side lobes in antenna radiation patterns accurately. Large amplitude and phase variation, narrow bandwidth, limited linearity, unidirectional operation, complex system configuration and larger power consumption are the limitations of a variable gain amplifier (VGA), thereby making VGA unfit for use in a wideband phased array system. From this viewpoint, passive digital attenuators are more attractive, since they can compensate for most of the drawbacks of the VGA.
[0004] In an existing approach, a wideband RF digital attenuator is proposed by utilising quarter-wave transmission lines at the signal interface of every attenuation, however, this approach leads to lengthy transmission lines, which impacts miniaturization. Another existing approach discloses a high-power handling low insertion loss, have few or no glitch during transition digital attenuator. However, the proposed design needs more transistors, which increases the complexity of biasing. Another existing approach encompasses a digital attenuator with low phase variation by connecting a low pass filter with a serial resistance to a series switch in parallel. However, the low pass section has frequency limitations and does not detail the effect of low pass section over wideband.
[0005] Another existing approach discloses a wideband RF attenuator circuit that has a reduced impact on the phase of an applied signal when switched between an attenuation state and a non-attenuating reference or bypass state, however, this approach is not feasible for realizing compact solutions. Yet another approach discloses a method to improve phase variation of a digitally controlled attenuator. However, this approach is not feasible for realizing compact solutions since bigger capacitors are needed for wider band applications.
[0006] Therefore, it is desired to develop a compact, power efficient and cost-effective digital attenuator to address and solve the above-mentioned limitations.

OBJECTS OF THE PRESENT DISCLOSURE
[0007] An object of the present disclosure relates, in general, to electronic attenuators, and more specifically, relates to a multi-octave low power consumption digital attenuator.
[0008] Another object of the present disclosure is to provide a compact, power-efficient and low-cost solution device with minimal phase shift.
[0009] Another object of the present disclosure is to provide a device that enables lesser phase variation between attenuation and insertion path obtained by optimization of capacitors and transmission lines of individual attenuation bits.
[0010] Another object of the present disclosure is to provide a device that achieves transmission line matching between individual bits to improve return loss.
[0011] Another object of the present disclosure is to provide a device that achieves miniaturisation of the die.
[0012] Another object of the present disclosure is to provide a device that achieves multioctave performance.
[0013] Another object of the present disclosure is to provide a device that is protected from electrostatic discharge surges.
[0014] Another object of the present disclosure is to provide a device that prevents RF signal leak and achieve better insertion loss without degrading switching speed.
[0015] Another object of the present disclosure is to provide a device that achieves accurate attenuation.
[0016] Yet another object of the present disclosure is to provide a device that enables single-supply operation without any additional digital driver circuit for the toggling the states of individual bits, which helped in attaining compact size.

SUMMARY
[0017] The present disclosure relates, in general, to electronic attenuators, and more specifically, relates to a multi-octave low power consumption digital attenuator with a minimal phase shift.
[0018] In an aspect, the present disclosure relates to a device for attenuating RF signals, the device comprising an input port for receiving an input signal to be attenuated, an output port for outputting the attenuated output signal, a reference path located between the input port and the output port and an attenuation path between the input port and the output port and a plurality of attenuator stages configured to selectively alter the attenuation of the applied signal, wherein each stage being assigned a corresponding bit position, the plurality of attenuator stages interconnected by transmission lines that is extended between the input port and the output port to obtain impedance matching in operating band and to achieve lower insertion phase shift.
[0019] According to an embodiment, the plurality of attenuator stages can be five-attenuator stages with corresponding bits implemented using modified-T topology, wherein the plurality of attenuator stages implemented with maximum attenuation range of 15.5dB and minimum resolvable level of 0.5dB.
[0020] According to an embodiment, the device can be fabricated using 0.25 µm E/D mode high performance GaAs pseudomorphic high electron mobility transistor (pHEMT) process with a die size of less than 1.5 mm X 1.60 mm in X and Y respectively.
[0021] According to an embodiment, the wideband impedance matching in the operating band is obtained with the transmission line between the plurality of attenuator stages, wherein at the input port and the output port, better than 10dB return losses is obtained over the operating band for all attenuation states, where the operating band is L to Ku band.
[0022] According to an embodiment, one or more FETs having a source, gate, and drain coupled to each attenuator stage to obtain better input third order intercept point, wherein peripheries of the one or more FETs optimized by considering the tradeoff between output third order intercept point (OIP3) and wideband performance.
[0023] According to an embodiment, the device can include one or more resistors of predetermined resistance values coupled to the gate of each FET to obtain less insertion loss without degrading switching speed and to prevent RF signal leakage, wherein the peripheries of the one or more FET in the reference path and gate resistors can be optimized to obtain typical insertion loss in the operating band lesser than 5.5 dB.
[0024] According to an embodiment, the device can include one or more capacitors of predetermined value coupled to the source and the drain of each FET in the attenuation path of each attenuator stage to ensure both drain and source are maintained at same potential and to obtain current consumption of less than 0.1mA, wherein the one or more capacitors less than 12pF incorporated with additional metal 0 layer that aids in miniaturization of the die.
[0025] According to an embodiment, the device can include series resistors of predetermined resistance values coupled to RF–DC crossover areas to avoid RF signal coupling to DC lines.
[0026] According to an embodiment, the device comprises ESD protection circuitry that comprises ESD diodes coupled to the control lines and supply line of the device to avoid damage due to electro static discharge.
[0027] According to an embodiment, the ESD diodes comprises less than six forward biased diodes from control line to ground and less than three reverse biased diodes from control line to ground.
[0028] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The following drawings form part of the present specification and are included to further illustrate aspects of the present disclosure. The disclosure may be better understood by reference to the drawings in combination with the detailed description of the specific embodiments presented herein.
[0030] FIG. 1A illustrates an exemplary representation of wide band digital attenuator, in accordance with an embodiment of the present disclosure.
[0031] FIG. 1B illustrates an exemplary view of individual attenuator stage, in accordance with an embodiment of the present disclosure.
[0032] FIG. 2 illustrates an exemplary RF-DC crossover area, in accordance with an embodiment of the present disclosure.
[0033] FIG. 3 illustrates a schematic view of capacitors added to attenuation path of T topology, in accordance with an embodiment of the present disclosure.
[0034] FIG. 4 illustrates a schematic view of ESD protection circuit, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0035] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0036] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0037] The present disclosure relates, in general, to electronic attenuators, and more specifically, relates to a multi-octave low power consumption digital attenuator with a minimal phase shift.
[0038] The device of the present disclosure enables to overcome the limitations of the prior art by providing a multi-octave GaAs MMIC multiple-bit digital attenuator. The device can be a single chip having a suitable die size fabricated using 0.25 µm GaAs pseudomorphic high electron mobility transistor (pHEMT) process. This design has good attenuation accuracy, return loss with low phase variation over L to Ku frequency band. The proposed device can be monolithic, compact in size, less power consumption, better insertion loss, and single-supply operation without any additional digital driver circuit. The device can achieve a maximum attenuation range of 15.5dB with a minimum resolution of 0.5dB. The description of terms and features related to the present disclosure shall be clear from the embodiments that are illustrated and described; however, the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents of the embodiments are possible within the scope of the present disclosure. Additionally, the invention can include other embodiments that are within the scope of the claims but are not described in detail with respect to the following description.
[0039] FIG. 1A illustrates an exemplary representation of wide band digital attenuator, in accordance with an embodiment of the present disclosure.
[0040] Referring to FIG. 1A, digital attenuator 100 (also referred to as device 100, herein) configured for attenuating radio signal over a wide bandwidth range used in electronic warfare applications. In an exemplary embodiment, digital attenuator 100, as presented in the example, can be a wideband five-bit digital attenuator implemented as gallium arsenide (GaAs) monolithic microwave integrated circuit (MMIC) and intended to operate in operating band from L to Ku band with input port and output port matched to 50 Ohms. As can be appreciated, the present disclosure may not be limited to this configuration but may be extended to other configurations where it may be incorporated into circuits for use at higher frequencies.
[0041] The wideband GaAs MMIC digital attenuator 100 as disclosed herein is a single chip MMIC with a suitable die size. The digital attenuator 100 operates in continuous wave mode and is fabricated using 0.25 µm E/D mode high-performance GaAs pseudomorphic high electron mobility transistor (pHEMT) process with the die size of less than 1.5 mm X 1.60 mm in X and Y respectively for wideband applications. The digital attenuator 100 can include the input port 102, the output port 104, one or more attenuator stages (106-1 to 106-5 (which are collectively referred to as attenuator stages 106, and individually referred to as attenuator stage 106, hereinafter) interconnected by transmission lines that are extended between the input port 102 and the output port 104.
[0042] The input port 102 can be configured for receiving an input signal to be attenuated. The radiofrequency (RF) signal to be attenuated are applied to the input port 102 of the device 100. The output port 104 can be configured for outputting the attenuated output signal. A reference path is located between the input port 102 and the output port 104 and an attenuation path is located between the input port 102 and the output port 104. The microstrip transmission lines can be extended between the input port 102 and the output port 104 coupled to the attenuator stages (106-1 to 106-5), where each stage is configured to selectively alter the attenuation of the applied signal, each stage being assigned a corresponding bit position. Each attenuator stage (106-1 to 106-5) may be switched to the attenuation state or the reference state.
[0043] In an exemplary embodiment, the digital attenuator 100 with RF input port 102 and output port 104 are 50ohm matched. The size of RF pad can be less than 200um x100um to accommodate a minimum of two bond wires at the RF input port 102 and output port 104. The dimension of the direct current (DC) pad can be less than 100um x100um used for the external control voltage interface.
[0044] In an exemplary embodiment, the attenuator stages (106-1 to 106-5) can be five-attenuator stages with corresponding bits, where the five attenuation bits are 0.5 dB, 1 dB, 2 dB, 4 dB and 8 dB. The digital attenuator 100 with the attenuator stages (106-1 to 106-5) can be implemented with a maximum attenuation range of 15.5dB and a minimum resolvable level of 0.5dB. The attenuator stages (106-1 to 106-5) are interconnected by transmission lines that are extended between the input port 102 and the output port 104 to obtain impedance matching in the operating band and achieve lower insertion phase shift.
[0045] The attenuator stages (106-1 to 106-5) having corresponding bits is interconnected with matching networks designed by using microstrip transmission lines having a relative dielectric constant of 12.9. The transmission line matching is used for impedance matching and for achieving lower insertion phase shift in individual attenuation bits, where intermediate matching between the attenuation bits aids to improve return loss. The transmission line matches between individual bits to achieve a typical return loss better than 11dB in Ku band. The wideband impedance matching upto Ku band obtained with the microstrip transmission line matching between the attenuator stages, where at both input port 102 and output port 104, better than 10dB return loss can be achieved over the operating band for all attenuation states.
[0046] FIG. 1B illustrates an exemplary view of individual attenuator stage, in accordance with an embodiment of the present disclosure. The individual attenuation stage 106 is shown in FIG. 1B are realized using modified T-topology 108. The attenuation stage 106 can be realized using modified T-attenuation topology, to operate with positive control voltage and supply voltage, to reduce current consumption. The T-topology 108 can be modified for low power consumption designed by removing digital driver dependency, which helped to reduce the current consumption of digital attenuator less than 0.1mA.
[0047] In an embodiment, the device 100 can provide selectable attenuation by incorporating one or more field-effect transistors (FETs) (110-1, 110-2) (also referred to as FETs, herein) or other types of a suitable transistor in accordance with the described embodiments arranged in a variety of network configurations, which may include other circuit elements, e.g., resistor, capacitors and the likes. Each FET can include a source, gate, and drain. The optimised periphery switch i.e., FETs (110-1, 110-2) (also referred to as FET device, herein) can be used in the attenuation stage 106 to get better input third-order intercept point, achieve multioctave performance and insertion loss over wideband. The switches (110-1, 110-2) can be controlled using gate voltage.
[0048] Each resistor may include, for example, a thin-film resistor or other suitable resistors in accordance with the described embodiments. Each capacitor may include, for example, high-value capacitors or other suitable capacitors in accordance with the described embodiments. Lengthy delay lines are used in the bits to compensate phase difference between the through path and the attenuation path.
[0049] The one or more resistors of predetermined resistance values are coupled to the gate of each FET to obtain less insertion loss without degrading switching speed to prevent RF signal leakage. In an exemplary embodiment, MESA resistor of less than 11KiloOhm used at the gate of each FET to prevent RF leakage to DC control circuitry and to obtain better insertion loss without degrading switching speed.
[0050] The FET device peripheries in reference path and gate resistors can be optimized to obtain typical insertion loss in the band better than 5.5 dB. The FET device peripheries optimized by considering the tradeoff between output third order intercept point (OIP3) and wideband performance. Typical measured third order input intercept point (IIP3) of +40dBm.
[0051] The digital attenuator 100 can enable different attenuation states based on control voltage and supply voltage, where switching between the states can be ensured by adding high-value capacitors (302-1, 302-2) shown in FIG. 3 to the T-attenuator topology 108. In an exemplary embodiment, the 5-bit digital attenuator 100 operates in 32 attenuation states with a step size of 0.5dB based on the DC control voltage. The digital attenuator 100 operates with a supply voltage VDD in the range +2V to +5.5V and is controlled with voltage, VDD and 0V to change attenuation states from 0 to 32. This reduces power consumption by avoiding additional digital control circuitry, as FETs are directly controlled with positive voltage.
[0052] Additional digital circuitry is not required for toggling the states of individual attenuator stage 106, which helped in attaining compact size. The gate resistor implemented, improves insertion loss with a slight degradation in switching speed compared to a lower value. The high-value capacitors (302-1, 302-2) added to the source and drain of FET devices (110-1, 110-2) in the attenuation path of individual attenuator stage 106 ensures both drain and source are maintained at the same potential.
[0053] In an embodiment, all the RF lines can be realized using thick metal transmission lines except DC–RF crossover junctions/area 200, where DC–RF crossover junctions 200 can be realized with metal 2 used for routing. Series resistors (202-1, 202-2) of predetermined resistance values used in RF–DC crossover areas 200 is shown in FIG. 2 to avoid coupling. In an exemplary embodiment, the series thin-film resistors of less than 600ohm (202-1,202-2) coupled to the RF to DC crossover areas 200 to reduce leakage. In another exemplary embodiment, the series resistors less than 500Ohm used in RF–DC crossover areas 200 to avoid RF signal coupling to DC lines.
[0054] In another embodiment, to protect attenuator 100 from electrostatic discharge (ESD) surge, ESD protection circuit 400 shown in FIG. 4 can be coupled to the control lines and supply lines of the device 100. The device 100 achieves good attenuation accuracy better than ±0.6dB+10% max.
[0055] FIG. 2 illustrates an exemplary RF-DC crossover areas 200, in accordance with an embodiment of the present disclosure. As shown in FIG. 2, the series resistors (202-1, 202-2) of less than 600ohm can be coupled to the RF to DC crossover areas 200 to reduce leakage. The miniaturisation of the die can be achieved by allowing RF-DC crossover areas 200. The series resistors (202-1, 202-2) less than 500Ohm coupled to the RF–DC crossover areas to avoid coupling.
[0056] FIG. 3 illustrates a schematic view of capacitors added to attenuation path 300 of T topology, in accordance with an embodiment of the present disclosure.
[0057] Referring to FIG. 3, high-value capacitors (302-1, 302-2) can be coupled to the source and the drain of FET devices (110-1, 110-2) in the attenuation path of each attenuator stage 106, which ensures both drain and source are maintained at the same potential. The capacitors (302-1, 302-2) used here uses an additional layer of metal 0 to increase capacitor density, which helped to realize less than 12 picofarad (pF) capacitors in a smaller size. The high-value capacitors (302-1, 302-2) used in each attenuator stage 106 of attenuator 100 are configured for DC blocking, impedance matching and phase compensation. The compact high-value capacitors (302-1, 302-2) were added to the attenuation path of T topology to reduce current consumption. The high-value capacitor less than 12pF for attenuation path incorporated with additional metal 0 layer aids in miniaturization of the die.
[0058] FIG. 4 illustrates a schematic view of ESD protection circuit 400, in accordance with an embodiment of the present disclosure.
[0059] Referring to FIG. 4, ESD protection circuit 400 comprising ESD diodes that can be added in control lines and supply lines to protect the digital attenuator 100 from electrostatic discharge surges. In an exemplary embodiment, the ESD protection circuit 400 can include less than six forward-biased diodes from control line to ground and less than three reverse biased diodes from control line to ground. In an exemplary embodiment, 500V human-body model (HBM) ESD protection can be achieved by incorporating ESD diode on control lines and supply line of the device 100.
[0060] The embodiments of the present disclosure described above provide several advantages. The proposed digital attenuator 100 can provide single supply, power-efficient, low insertion phase shift, highly power-efficient and miniature in size MMIC. The lesser phase variation between attenuation and insertion path can be obtained by optimization of capacitors and transmission lines of individual attenuation bits. Typical phase variation of major states achieved less than 20 degrees in Ku band.
[0061] The present disclosure provides the device 100 that is compact, power-efficient and low-cost solution for electronic warfare applications. The device 100 achieves transmission line matching between individual bits to improve return loss at the operating band, prevents RF signal leak and achieves better insertion loss without degrading switching speed. The device 100 achieves miniaturisation of the die, achieves accurate attenuation, protects from electrostatic discharge surges and enables single-supply operation without any additional digital driver circuit for the toggling the states of individual bits, which helped in attaining compact size.
[0062] It will be apparent to those skilled in the art that the device 100 of the disclosure may be provided using some or all of the mentioned features and components without departing from the scope of the present disclosure. While various embodiments of the present disclosure have been illustrated and described herein, it will be clear that the disclosure is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the disclosure, as described in the claims.

ADVANTAGES OF THE PRESENT DISCLOSURE
[0063] The present disclosure provides a compact, power-efficient and low-cost solution device with minimal phase shift.
[0064] The present disclosure provides a device that enables lesser phase variation between attenuation and insertion path obtained by optimization of capacitors and transmission lines of individual attenuation bits.
[0065] The present disclosure provides a device that achieves transmission line matching between individual bits to improve return loss.
[0066] The present disclosure provides a device that achieves miniaturisation of the die.
[0067] The present disclosure provides a device that is protected from electrostatic discharge surges.
[0068] The present disclosure provides a device that prevents RF signal leak and achieves better insertion loss without degrading switching speed.
[0069] The present disclosure provides a device that achieves accurate attenuation.
[0070] The present disclosure provides a device that achieves multioctave performance.
[0071] The present disclosure provides a device that enables single-supply operation without any additional digital driver circuit for the toggling the states of individual bits, which helped in attaining compact size.