1 Field of the Invention
This invention relates to digital voice communications, particularly conveying data information digitally over a Wifi or any wireless networks, such as providing long distance telephone service over the Wifi or any other wireless network and specifically relates to Digital clock Buffer Manager El over Wireless Network.
2 Description of the Related Art
Data is communicated through the data communication network such as various computers, servers, nodes, routers, switches, hubs, proxies, and other devices coupled to and configured to pass data to one another. The data communication network is transmitting data over an established circuit or packetizing the data and routing the data packets between a series of network elements over the network.
There are two types of networks transmitting data such as Time Division Multiplexed (TDM) networks and packet networks. TDM network relies on time to determine which signals belong to which connection, whereas in a packet network the packets are individually addressed in a manner, which can be understood by the network elements. Timing requirements of TDM networks are relatively stringent because it relies on time to divide signals between multiple logical channels. Timing is less important in a packet network since each packet of data is self-contained and is able to specify to the network its size and other associated

parameters. So the network elements on a packet network are generally not synchronized and are generally implemented as asynchronous networks. TDM networks are synchronous in nature and the equipment connected has to be synchronized to it in some manner. A timing distribution network typically will link the TDM nodes to provide a synchronization signal that is traceable to a Primary Reference Source. Networking synchronization is derived from the primary reference source and distributed through network nodes with lesser stratum clocks. The particular timing requirements on a service interface depend on the services carried over the network, which are typically specified in a standard promulgated for that particular service type. The speed of data transmitted on the physical connection is controlled by clocking at the physical interface of a network element. The transmitter clock and the receiver clock control the arrival rate and the departure rate from the buffer respectively. Data can be lost due to buffer overflow or underflow, resulting in periodic line errors if the physical interfaces on a connection are not synchronized.
Due to asynchronous nature of the packet networks, it is able to carry traffic between the end TDM networks, but it does not naturally carry clock information. It is necessary to enable TDM traffic to be carried over a packet network, which have the end systems directly exchange clock information to allow the data ports on the network elements to be synchronized and to allow the different networks to be synchronized.

Several adaptive timing techniques have been developed, including extracting clock information from arrival patterns over the network, observing the rate at which the buffers are being filled, and using encoded timing signals transmitted from the upstream terminal to the downstream terminal across the packet network. Although several of the developed techniques are relatively good at transmitting clock signals on the network, it would still be advantageous to find a way to transmit better clock information across the network, and to find a way to use a less complicated circuit than a PLL to implement the slave clocks.
Clock synchronization is, a clock signal in a communication network is generated or derived and distributed through the network and its individual nodes for the purpose of ensuring synchronized network operation. Clock synchronization is an important design consideration in time division multiplexing networks, and in packet networks carrying TDM voice or video traffic. TDM data at every hop in a connection must be transmitted and received at the same rate. Clocking at a physical interface of a network device controls the speed at which data is transmitted on a physical connection. Ethernet/IP networks offer essentially an asynchronous transmission service, which makes the synchronization needs of real-time applications difficult to meet in these networks.
Two main performance degradation issues come into play when clocks at a transmitter and a receiver are not synchronized. First, if the physical

interfaces along a connection are not synchronized, data can be lost due to buffer overflow or underflow, resulting in periodic line errors. When the physical interfaces are synchronized, then, within a given time window, the same amount of data is transmitted or forwarded at every point in the connection. Second, imperfections in clock synchronization can lead to observable defects on an end service such as bit errors due to alignment jitter when inter working with a plesiochronous digital hierarchy (PDH) or a synchronous digital hierarchy (SDH) network, or frame slips when inter working with a public switched telephone network (PSTN) or an integrated service digital network (ISDN). 3
Summary of the Invention
In view of the above problems, it is an object of the present invention to significantly control the clock variation with respect to the TDM clock. The main embodiment of the present invention is to negate the underflow or overflow of the 16KB jitter buffer by controlling the variations of TDM clock. Another embodiment of the present invention is a system and method for receiving digital voice/data signals transmitted over a data network. Yet another embodiment of the present invention is to provide a jitter buffer having a fixed storage size of 16 KB, arranged to receive packets of data, which make up a digitized, packetized PCM signal.
Further embodiment of the present invention, a jitter buffer manager monitors packet arrival with respect to its threshold of 8KB. With respect to the

variations in the packet arrival rate jitter buffer generates upper and lower
threshold limits.
Further embodiment of the present invention is to provide a Digital clock
manager which generates the 3 different clock frequencies 2.048 MHz, 2.080
MHz & 2.016 MHz with respect to normal threshold, upper threshold and
lower threshold respectively which will negate minimal delays of packetized
PCM signal.
4 BRIEF DESCRIPTION OF THE DRAWINGS
Aspects of the present invention are pointed out with particularity in the appended claims. The present invention is illustrated by way of example in the following drawings in which like references indicate similar elements. The following drawings disclose various embodiments of the present invention for purposes of illustration only and are not intended to limit the scope of the invention. For purposes of clarity, not every component may be labeled in every figure. In the figures:
Fig 1 is a block diagram of TDM over Wireless network. Fig 2 is a block diagram of a typical point-to-point TDM over Wireless network.
Fig 3 is a block diagram for TDM over Wireless network under normal. Fig 4 is a block diagram of jitter buffer under normal.

Fig 5 is a block diagram of digital clock manager block for generating constant clock of 2.048 MHz generated with respect to the normal threshold of 8 KB jitter Buffer. Fig. 6 is a block diagram for TDM over Wireless network under
overflow/FIFO FULL.
Fig.7 is a block diagram of jitter buffer under overflow.
Fig 8 is a block diagram of digital clock manager block for generating constant
clock of 2.080 MHz generated with respect to the upper threshold of 12 KB
jitter Buffer.
Fig. 9 is a block diagram for TDM over Wireless network under underflow/
FIFO EMPTY.
Fig. 10 is a block diagram of jitter buffer under underflow.
Fig 11 is a block diagram of digital clock manager block for generating
constant clock of 2.016 MHz generated with respect to the lower threshold of 4
KB jitter buffer.
Detailed description:
The following detailed description sets forth numerous specific details to
provide a thorough understanding of the invention. However, those skilled in
the art will appreciate that the invention may be practiced without these
specific details. In other instances, well-known methods, procedures,
components, protocols, algorithms, and circuits have not been described in
detail so as not to obscure the invention.

The present invention provides a transport facility adapted to transport TDM streams using Ethernet packets. The TDM bit streams are received, buffered and encapsulated into Ethernet frames using the method of the present invention. Using the present invention, TDM streams such as El, Tl, etc. can be transported via Ethernet frames. The resulting Ethernet frames can then be transported over existing transport facilities such as optical fiber, wireless network etc. thus enabling Network Service Providers (NSPs) to offer more services for reduced cost. At the destination, the Ethernet frames are segmented, stored in the jitter buffer and TDM bit streams are regenerated.
The simplest implementation of TDM over Wireless as shown in Fig 1, Each El frame (8 x El frame =256 Bytes i.e. after every lms) is buffered and encapsulated in an MII packet by tacking on the appropriate header. For reliable connection-oriented service we are using Media Independent Interface (MII), which requires a 26-byte MAC, for a total of 26 bytes overhead bytes per packet.

On Egress Side, the overhead is removed from each packet and TDM data is put on to the Jitter Buffer (16 KB). When 8KB(Le. after 32ms) Normal threshold is generated, TDM data is pushed out at 2.048 Mbps as shown in Fig 4 and Fig 5. Jitter Buffer is prone to Underflow and Overflow due to packet delay variation and jitter in the clocks.
The present invention solves the above problem of Jitter Buffer, by regenerating variable TDM clock according to the threshold level on the Jitter Buffer as shown in Fig 8 and Fig 11.
In general, there are at least two factors which determine the perceived quality of the resulting phone conversation: (1) Packet arriving too early or too late to be corrected, thus avoiding the sync loss (2) Jitter in the two asynchronous clocks to be corrected.
A large static jitter buffer can be designed into the receiving gateway to optimize performance against large amounts of network delay jitter at the cost of large delays (i.e. more than 32ms, in our case) which will be noticed by users; on the other hand, a small jitter buffer (16KB) can be used which will negate minimal delays. In this case call quality will not be degraded if network Jitter doesn't exceed the size of the Buffer.
The present invention is not to be limited in scope by the specific embodiments described herein. Indeed, various modifications of the present invention, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying

drawings. Thus, such modifications are intended to fall within the scope of the following appended claims. Further, although the present invention has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present invention can be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breath and spirit of the present invention as disclosed herein.
5. APPLICATION
a. The present invention can be used where asynchronous buffer is used.



El services to be carried over a packet switched network, such as an Ethernet and IP. The El data into user-defined packets and passes it transparently over the packet network to be reconstructed at the far end. This has a number of applications, including emulation of TDM circuits and packet backplanes for TDM-based equipment.
El over MII works by chopping El data streams into MII packets and adding headers. MIIPackets are then bridged or routed over the Fiber network. At the destination site the original bit stream is reconstructed by removing headers, concatenating packets, and regenerating the clock. The main aim of the invention is to transport El data on Media Independent Interface.
Accordingly A system for transmitting TDM signals over an asynchronous Wifi Network, comprising: digitized voice/data is introduced through Gateway (1) and divided into small Media Independent Interface (MII)

data packets by Gateway (2); wherein the MII data packets are sent over the asynchronous network (3) which results in them arriving at the far end Gateway (4) with varying amount of delay on each packet; wherein the original bit stream at Gateway (4) is reconstructed by chopping headers and processed in a buffer(5) and taken out for TDM stream assembly at Gateway (6) thus provides a continuous voice signal which sounds like a slightly delayed copy wherein jitter buffer manager monitors packet arrival with respect to its variations in the packet arrival rate jitter buffer generated upper and lower threshold limits of 8KB; a Digital clock manager generates plurality of frequencies with respect to normal threshold, upper threshold and lower threshold respectively which will negate minimal delays of packetized PCM signal.
A system for transmitting TDM signals over an asynchronous Wifi Network as claimed in claim 1, further comprises
a. the El SIPO Block (11) takes serial El stream and converts the data into byte;
b. the Ethernet Frame Transmit (13) at the positive edge of the nibble clock, byte clock is generated;
c. the MII packet formation process starts at the MII Block(14) and reads DPRAM data during data byte positions of MII packets; the MII data packets are sent over the asynchronous network (15)

d. nibble data received at nibble clock domain in the Ethernet Frame Receive (16) is converted into byte wherein the MII packet recovery process is started and data is written on to the DPRAM according to data byte position;
e. MII data is processed in the jitter buffer manager (17) that monitors packet arrival with respect to its variations in the packet arrival rate and generated upper and lower threshold limits of 8KB and generated two flags depending on the MII data accumulated,
f. the Digital Clock Manager (28), depending on the flag generated from the jitter buffer the varied El read clock is generated; wherein the two different El read clock frequencies are 2.080 MHz, 2.016 MHz with respect to the FIFO FULL and FIFO EMPTY respectively.
g. E1PISO Block (18) works at 2.048 clock, generates Read Address, Read clock and Read Enable for Receive DPRAMs wherein byte to bit conversion, with respect to 2.048MHz El data is taken out from Line Interface unit (20).
A method for transmitting TDM signals over an asynchronous Wifi Network comprises
h. the El SIPO Block (11) takes serial El stream and converts the data into
byte;
i. the Ethernet Frame Transmit (13) at the positive edge of the nibble clock, byte clock is generated;

j. the MII packet formation process starts at the MII Block(14) and reads DPRAM data during data byte positions of MII packets; the MII data packets are sent over the asynchronous network (15);
k. nibble data received at nibble clock domain in the Ethernet Frame Receive (16) is converted into byte wherein the MII packet recovery process is started and data is written on to the DPRAM according to data byte position;
1. MII data is processed in the jitter buffer manager (17) that monitors packet arrival with respect to its variations in the packet arrival rate and generated upper and lower threshold limits of 8KB and generated two flags depending on the MII data accumulated;
m. the Digital Clock Manager (28), depending on the flag generated from the jitter buffer the varied El read clock is generated; wherein the two different El read clock frequencies are 2.080 MHz, 2.016 MHz with respect to the FIFO FULL and FIFO EMPTY respectively,
N. E1PISO Block (18) works at 2.048 clock, generates Read Address, Read clock and Read Enable for Receive DPRAMs wherein byte to bit conversion, with respect to 2.048MHz El data is taken out from Line Interface unit (20).
Figure 1 illustrates an exemplary embodiment of the present invention wherein El SIPO Block takes Serial El Stream at 2.048 MHz (El JTCLK) and converts into Byte. Converted Byte is written into 256 x 8 DPRAM. Write Address,

Write Enable (E1JTCLK/8), Write Clock (E1JTCLK) for 256 x 8 are also generated. Data is written into DPRAM at 2.048 MHz / 8. Once it reaches to 256 x 8 Address location it shifts other DPRAM for Writing and also it creates Multi-frame Indication for every lms ((256*8)/ (2.048 xl0**6)). It generates a flag ElFrameFull which is the reference for Forming MII Frame in "MII Frame Formation Block".
Ethernet Frame Transmit (ETHTX) at the positive edge of the nibble clock, Byte clock (works at 12.5MHz) is generated. If the multi frame Indication signal is set (generated from the El SIPO block) the MII packet formation process starts and reads DPRAM data during data byte positions of MII packets. Frame starts with the Preamble, Start Frame Delimiter, Destination Address, and Source Address, Length/Type, Tag Control and Mac Client Length are loaded into DPRAM. After reading all the bytes Tx Frame Last byte flag signal is generated and MII TX Enable signal is disabled.
In Ethernet Frame Receive (ETHRX) nibble data received at nibble clock (25 MHz) domain. The nibble data is converted into Byte form at byte clock (12.5 MHz) and if the valid PA and SFD are recovered then MII packet recovery process starts and data is written on to the DPRAM according to data byte position.
E1PISO Block works at 2.048 clock, Generates Read Address, Read clock and Read Enable for Receive DPRAMs. Byte to Bit conversion, with respect to 2.048MHz El data is taken out from LIU.

In the above architecture if the entire clock is ideally synchronized (fig. 4) there will be no issues. If there is a change in the variation of clock (fig. 7 & fig. 10) which is prone to full and empty of the received buffer leading to sync loss. To overcome the above issue Jitter buffer logic is implemented (fig. 2).
Figure 3 illustrates that the SIPO Block takes Serial El Stream at 2.048 MHz (E1TCLK) and converts into Byte, Converted Byte is written into 256 x 8 DPRAM. Write Address, Write Enable (El_TCLK/8), Write Clock (E1TCLK) for 256 x 8 are also generated. Data is written into DPRAM at 2.048 MHz / 8. Once it reaches to 256 x8 Address location it shifts other DPRAM for Writing and also it creates Multi-frame Indication for every 1ms ((256*8)/ (2.048 xl0**6)). It generates a flag El_Frame_Full which is the reference for Forming MII Frame in "MII Frame Formation Block".
Ethernet Frame Transmit (ETHTX) at the positive edge of the nibble clock, Byte clock (works at 12.5MHz) is generated. If the multi frame Indication signal is set (generated from the El SIPO block) the MII packet formation process starts and reads DPRAM data during data byte positions of MIIpackets. Frame starts with the Preamble, Start Frame Delimiter, Destination Address, and Source Address, Length/Type, Tag Control and Mac Client Length are loaded into DPRAM.
After reading all the bytes Tx Frame Last byte flag signal is generated and MII TX Enable signal is disabled.

In the Ethernet Frame Receive (ETHRX) nibble data received at nibble clock domain. The nibble data is converted into Byte form at byte clock (12.5 MHz) and if the valid PA and SFD are recovered then MII packet recovery process starts and data is written on to the DPRAM according to data byte position.
Jitter Buffer (JBUFFER) is 16KB DPRAM where MII data is processed. The purpose of the jitter buffer is to generate two flags depending on the MII data accumulated. It generates 2 flags such as FIFO FULL threshold, wherein 12KB of data is filled and FIFO EMPTY threshold 4 KB of data is filled. Depending on the flag generated from the jitter buffer the varied read clock is generated from the digital clock manager. By using the varied read clock, jitter buffer is not prone to full or empty issues. PISO Byte to Bit conversion, with respect to 2.048MHz El data is taken out from LIU.
Digital Clock Manager (DCM) block is used to generate the two different El read clock frequencies 2.080 MHz, 2.016 MHz, 2.048 MHz with respect to the FIFO FULL and FIFO EMPTY respectively. On board 16.384 MHz is used as an input to the Digital clock manager (Xilinx resource) and multiplier operation is done to obtain 131.702 MHz. Using 131.702 MHz and FIFO FULL, 2.080 MHz clock is generated. Using 131.702 MHz and FIFO EMPTY, 2.016 MHz clock is generated.

Under Normal operation 2.048 MHZ clock is generated. With the above mentioned variable read clock frequencies the level of the jitter buffer is maintained in the mid level (8KB).
Figure 2 illustrates a typical TDM over Wireless system, Person X's voice is digitized by Gateway 1 and divided into small MII data packets by Gateway 2 (numbered in temporal sequence in the Figure, for convenience). The MII data packets are sent over the asynchronous network 3 which results in them arriving at the far end Gateway 4 with varying amount of delay on each packet. At Gateway 4, the original bit stream is reconstructed by chopping headers and processed in a buffer and taken out for TDM stream assembly at Gateway 5, thus provides a continuous voice signal to person Y which sounds like a slightly delayed copy of what person X said. The same process typically happens in the reverse direction at the same time, thus supplying a full duplex conversation.
According to figure 3 SIPO block takes Serial El Stream at 2.048 MHz (E1TCLK) and converts into Byte. Converted Byte is written into 256 x8 DPRAM. Write Address, Write Enable (E1JTCLK/8), Write Clock (E1JTCLK) for 256 x8 is also generated. Data is written into DPRAM at 2.048 MHz / 8. Once it reaches to 256 x8 Address location it shifts other DPRAM for Writing and also it creates Multi-frame Indication for every lms ((256*8)/ (2.048 xl0**6)). It generates a flag El_Frame_Full which is the reference for Forming MII Frame in "MII Frame Formation Block".

Ethernet Frame Transmit (ETH TX) at the positive edge of the nibble clock, Byte clock is generated. If the multi frame Indication signal is set (generated from the El SIPO block)the MII packet formation process starts and reads DPRAM data during data byte positions of MII packets. Frame starts with the Preamble, Start Frame Delimiter, Destination Address, and Source Address, Length/Type, Tag Control and Mac Client Length are loaded into DPRAM. After reading all the bytes Tx Frame Last byte flag signal is generated and MII TX Enable signal is disabled.
In the Ethernet Frame Receive (ETH RX) nibble data received at nibble clock domain. The nibble data is converted into Byte form at byte clock and if the valid PA and SFD are recovered then MII packet recovery process starts and data is written on to the DPRAM according to data byte position.
According to Figure 4 Jitter Buffer (JBuffer) is 16KB DPRAM where MII data is processed. Assumed to be working in ideal condition, there are no issues of clock synchronization. The arrival data packet into the jitter buffer is arrived for equal intervals of time (lms). The data also read at 2.048 MHz clock. Thus always midlevel is maintained. Here FIFO EMPTY and FIFO FULL are not enabled.
Figure 5 illustrates Digital Clock Manager (DCM); on board 16.384 MHz is used as an input to the Digital clock manager (Xilinx resource) and multiplier operation is done to obtain 131.702 MHz. Maximum tolerable frequency which the FPGA operates is with 130 MHz. Hence 8 are chosen as a

multiplier with 16.384 MHz input clock frequency which will yield 131.702MHz. Under Normal operation FIFO FULL and FIFO EMPTY are not enabled. Hence 2.048 MHz (referred as CLK2.048) is generated as a read clock in the control logic using 131.702 MHz. (fig5). The control logic is a divider circuit, which generates the 2.048 MHz using 131.702 MHz. PISO Byte to Bit conversion, with respect to 2.048 MHz El data is taken out from LIU.
Figure 6 illustrates that the SIPO Block takes Serial El Stream at 2.048 MHz (E1TCLK) and converts into Byte. Converted Byte is written into 256 x8 DPRAM. Write Address, Write Enable (El_TCLK/8), Write Clock (E1JTCLK) for 256 x8 is also generated. Data is written into DPRAM at 2.048 MHz / 8. Once it reaches to 256 x8 Address location it shifts other DPRAM for Writing and also it creates Multi-frame Indication for every lms ((256*8)/ (2.048 xlO**6)). It generates a flag ElFrameFull that is the reference for Forming MII Frame in "MII Frame Formation Block".
Ethernet Frame Transmit (ETHTX) at the positive edge of the nibble clock, Byte clock (works at 12.5MHz) is generated. If the multi frame Indication signal is set (generated from the El SIPO block) the MII packet formation process starts and reads DPRAM data during data byte positions of MII packets. Frame starts with the Preamble, Start Frame Delimiter, Destination Address, and Source Address, Length/Type, Tag Control and Mac

Client Length are loaded into DPRAM. After reading all the bytes Tx Frame Last byte flag signal is generated and MII TX Enable signal is disabled.
In the Ethernet Frame Receive (ETHRX) nibble data received at nibble clock domain. The nibble data is converted into Byte form at byte clock (12.5 MHz) and if the valid PA and SFD are recovered then MII packet recovery process starts and data is written on to the DPRAM according to data byte position.
According to Figure 7 Jitter Buffer (JBUFFER) is 16KB DPRAM where MIIdata is processed faster due to clock jitter, assumed to be working in overflow condition. Due to this FIFO FULL is enabled and FIFO EMPTY is not enabled. FIFO FULL is generated when the Jitter buffer is filled with 12 KB of MII Data.
Figure 8 illustrates the Digital Clock Manager (DCM) on board 16384 MHz is used as an input to the Digital clock manager (Xilinx resource) and multiplier operation is done to obtain 131.702 MHz. Maximum tolerable frequency, which the FPGA operates, is with 130 MHz. Hence 8 are chosen as a multiplier with 16384 MHz input clock frequency, which will yield 131.702MHz. Using FIFO FULL and 131.702 MHz, 2.080 MHZ (referred as CLK2.080) read clock is generated in the control logic. Thus by reading data with the varied clock CLK_2.080 the jitter buffer level is maintained at mid level.

PISO Byte to Bit conversion, with respect to 2.080MHz El data is taken out from LIU.
Figure 9 illustrates SIPO Block takes Serial El Stream at 2.048 MHz (E1TCLK) and converts into Byte. Converted Byte is written into 256 x8 DPRAM. Write Address, Write Enable (E1JTCLK/8), Write Clock (E1JTCLK) for 256 x8 is also generated. Data is written into DPRAM at 2.048 MHz / 8. Once it reaches to 256 x8 Address location it shifts other DPRAM for Writing and also it creates Multi-frame Indication for every 1ms ((256*8)/ (2.048 xlO**6)). It generates a flag ElFrameFull which is the reference for Forming MIIFrame in "MIIFrame Formation Block".
Ethernet Frame Transmit (ETHTX) at the positive edge of the nibble clock, Byte clock (works at 12.5MHz) is generated. If the multi frame Indication signal is set (generated from the El SIPO block)the MII packet formation process starts and reads DPRAM data during data byte positions of MIIpackets. Frame starts with the Preamble, Start Frame Delimiter, Destination Address, and Source Address, Length/Type, Tag Control and Mac Client Length are loaded into DPRAM. After reading all the bytes Tx Frame Last byte flag signal is generated and MII TX Enable signal is disabled.
In the Ethernet Frame Receive (ETHRX) nibble data received at nibble clock domain. The nibble data is converted into Byte form at byte clock (12.5 MHz) and if the valid PA and SFD are recovered then MII packet recovery

process starts and data is written on to the DPRAM according to data byte position.
Figure 10 illustrates Jitter Buffer (JBUFFER) is 16KB DPRAM where MIIdata is processed slower due to clock jitter, assumed to be working in underflow condition. Due to this FIFO EMPTY is enabled and FIFO 1 t 1 L is not enabled. FIFO EMPTY is generated when the Jitter buffer is filled w ith 4 KB of MII Data.
According to Fig 11 Digital Clock Manager (DCM) on board 10.384 MHz is used as an input to the Digital clock manager (Xilinx resource) and multiplier operation is done to obtain 131.702 MHz. Maximum loL-rable frequency which the FPGA operates is with 130 MHz. Hence 8 are chosen as a multiplier with 16.384 MHz input clock frequency. Using FIFO EMPLY and 131.702 MHz, 2.016 MHZ (referred as CLKJ2.016) read clock is generated in the control logic. Thus by reading data with the varied clock CLK 2016 the jitter buffer level is maintained at mid level. PISO Byte to Bit conversion, with respect to 2.016MHz El data is taken out from LIU.
Dated this the 16th day of October 2006
R.Harikrishuan [Agent for the applicant]
R.Harikrishnan [Agent for the applicant]

We claim:
1. A system for transmitting TDM signals over an asynchronous Wifi Network, comprising: digitized voice/data is introduced through Gateway (1) and divided into small Media Independent Interface (Mil) data packets by Gateway (2); wherein the Mil data packets are sent over the asynchronous network (3) which results in them arriving at the far end Gateway (4) with varying amount of delay on each packet; wherein the original bit stream at Gateway (4) is reconstructed by chopping headers and processed in a buffer(5) and taken out for TDM stream assembly at Gateway (6) thus provides a continuous voice signal which sounds like a slightly delayed copy wherein jitter buffer manager monitors packet arrival with respect to its variations in the packet arrival rate jitter buffer generated upper and lower threshold limits of 8KB; a Digital clock manager generates plurality of frequencies with respect to normal threshold, upper threshold and lower threshold respectively which will negate minimal delays of packetized PCM signal.
2. A system for transmitting TDM signals over an asynchronous Wifi Network as claimed in claim 1, further comprises
a. the El SIPO Block (11) takes serial El stream and converts the data into byte;
b. the Ethernet Frame Transmit (13) at the positive edge of the nibble clock, byte clock is generated;

c. the MII packet formation process starts at the MII Block(14) and reads DPRAM data during data byte positions of MII packets; the MII data packets are sent over the asynchronous network (15);
d. nibble data received at nibble clock domain in the Ethernet Frame Receive (16) is converted into byte wherein the MII packet recovery process is started and data is written on to the DPRAM according to data byte position;
e. Mil data is processed in the jitter buffer manager (17) that monitors packet arrival with respect to its variations in the packet arrival rate and generated upper and lower threshold limits of 8KB and generated two flags depending on the MII data accumulated;
f. the Digital Clock Manager (28), depending on the flag generated from the jitter buffer the varied El read clock is generated; wherein the two different El read clock frequencies are 2.080 MHz, 2.016 MHz with respect to the FIFO FULL and FIFO EMPTY respectively.
g. E1PISO Block (18) works at 2.048 clock, generates Read Address, Read clock and Read Enable for Receive DPRAMs wherein byte to bit conversion, with respect to 2.048MHz El data is taken out from Line Interface unit (20).
3. A system for transmitting TDM signals over an asynchronous Wifi Network as claimed in claim 2, byte clock works at 12.5MHz

4. A system for transmitting TDM signals over an asynchronous Wifi Network as claimed in claim 2, the MII packet formation process starts in the MII block and reads DPRAM data during data byte positions of MII packets; frame starts with the Preamble (PA), Start Frame Delimiter (SFD), Destination Address, and Source Address, Length/Type, Tag Control and Mac Client Length are loaded into DPRAM; Tx Frame Last byte flag signal is generated after reading all the bytes and MII TX Enable signal is disabled;
5. A system for transmitting TDM signals over an asynchronous Wifi Network as claimed in claim 2, nibble data received at nibble clock 25 MHz domain is converted into byte form at byte clock 12.5 MHz when the valid PA and SFD are recovered.
6. A system for transmitting TDM signals over an asynchronous Wifi Network as claimed in claim 2, MII data is processed in the Jitter Buffer that generate two flags depending on the MII data accumulated,
7. A system for transmitting TDM signals over an asynchronous Wifi Network as claimed in claim 2, TDM streams such as El, Tl, etc. are transported through Ethernet frames.
8. A system for transmitting TDM signals over an asynchronous Wifi Network as claimed in claim 2, packet variation is handled in a fixed storage of 16KB.

9. A system for transmitting TDM signals over an asynchronous Wifi
Network as claimed in claim 2, 16 KB of Xilinx Block RAM is used as
Jitter buffer. 10.A system for transmitting TDM signals over an asynchronous Wifi
Network as claimed in claim 2, variable read clock is generated using
Xilinx Digital clock manager. 11.A system for transmitting TDM signals over an asynchronous Wifi
Network as claimed in claim 2, 256 Bytes of frame size pattern is used. 12.A system for transmitting TDM signals over an asynchronous Wifi
Network as claimed in claim 2, TDM data is transported in a bandwidth of
2,4 Mbps via Wifi network. 13.A system for transmitting TDM signals over an asynchronous Wifi Net rk
as claimed in claim 2, three thresholds are generated depending on the
variation in the packet arrival rate, (a) Normal Threshold (b) Upper
Threshold (c) Lower Threshold. 14.A system for transmitting TDM signals over an asynchronous Wifi
Network as claimed in claim 2, when there is no packet variation constant
read clock of 2.048 MHz is generated. 15.A system for transmitting TDM signals over an asynchronous Wifi
Network as claimed in claim 2, when there is a packet variation i.e. moving
towards the full flag of block RAM, constant read clock of 2.080 MHz is

generated wherein the upper threshold (12KB) reaches the normal threshold
(8kB) after the duration of 1 sec. 16.A system for transmitting TDM signals over an asynchronous Wifi
Network as claimed in claim 2, when there is a packet variation i.e. moving
towards the empty flag of block RAM, constant read clock of 2.016 MHz is
generated wherein the lower threshold (4KB) reaches the normal threshold
(8kB) after the duration of 1 sec. 17.A method for transmitting TDM signals over an asynchronous Wifi
Network comprises
a. the El SIPO Block (11) takes serial El stream and converts the data into byte;
b. the Ethernet Frame Transmit (13) at the positive edge of the nibble clock, byte clock is generated;
c. the Mil packet formation process starts at the Mil Block(14) and reads DPRAM data during data byte positions of MII packets; the MII data packets are sent over the asynchronous network (15);
d. nibble data received at nibble clock domain in the Ethernet Frame Receive (16) is converted into byte wherein the MII packet recovery process is started and data is written on to the DPRAM according to data byte position;
e. Mil data is processed in the jitter buffer manager (17) that monitors packet arrival with respect to its variations in the packet arrival rate and

generated upper and lower threshold limits of 8KB and generated two flags depending on the MII data accumulated;
f. the Digital Clock Manager (28), depending on the flag generated from the jitter buffer the varied El read clock is generated; wherein the two different El read clock frequencies are 2.080 MHz, 2.016 MHz with respect to the FIFO FULL and FIFO EMPTY respectively;
g. EIPISO Block (18) works at 2.048 clock, generates Read Address, Read clock and Read Enable for Receive DPRAMs wherein byte to bit conversion, with respect to 2.048MHz El data is taken out from Line Interface unit (20);
18.A method for transmitting TDM signals over an asynchronous Wifi Network as claimed in claim 17, byte clock works at 12.5MHz
19.A method for transmitting TDM signals over an asynchronous Wifi Network as claimed in claim 17, the MII packet formation process starts in the Mil block and reads DPRAM data during data byte positions of MII packets; frame starts with the Preamble (PA), Start Frame Delimiter (SFD), Destination Address, and Source Address, Length/Type, Tag Control and Mac Client Length are loaded into DPRAM; Tx Frame Last byte flag signal is generated after reading all the bytes and MII TX Enable signal is disabled;
20.A method for transmitting TDM signals over an asynchronous Wifi Network as claimed in claim 17, nibble data received at nibble clock 25

MHz domain is converted into byte form at byte clock 12.5 MHz when the
valid PA and SFD are recovered. 2 LA method for transmitting TDM signals over an asynchronous Wifi
Network as claimed in claim 17, MII data is processed in the Jitter Buffer
that generate two flags depending on the MII data accumulated. 22.A method for transmitting TDM signals over an asynchronous Wifi Net
work as claimed in claim 17, TDM streams such as El, Tl, etc. is
transported through Ethernet frames. 23.A method for transmitting TDM signals over an asynchronous Wifi Net
work as claimed in claim 17, packet variation is handled in a fixed storage
of l6kB. 24.A method for transmitting TDM signals over an asynchronous Wifi
Network as claimed in claim 17, 16 KB of Xilinx Block RAM is used as
Jitter buffer. 25.A method for transmitting TDM signals over an asynchronous Wifi
Network as claimed in claim 17, variable read clock is generated using
Xilinx Digital clock manager. 26.A method for transmitting TDM signals over an asynchronous Wifi Net
work as claimed in claim 17, 16.384 MHz is used as an input to the Digital
clock manager and multiplier operation is done to obtain 131.702 MHz. 27.A method for transmitting TDM signals over an asynchronous Wifi Net
work as claimed in claim 17, digital clock manager for Normal operation,

FIFO FULL and FIFO EMPTY three clocks such as 2.048 MHZ, 2.080
MHz and 2.016 MHz respectively, is generated using 131.702 MHz clock. 28.A method for transmitting TDM signals over an asynchronous Wifi Net
work as claimed in claim 17y 256 Bytes of frame size pattern is used. 29.A method for transmitting TDM signals over an asynchronous Wifi Net
work as claimed in claim 17, TDM data is transported in a bandwith of 2.4
Mbps via Wifi network. 30.A method for transmitting TDM signals over an asynchronous Wifi
Network as claimed in claim 17, three thresholds is generated depending on
the variation in the packet arrival rate (a) Normal Threshold (b) Upper
Threshold(c) Lower Threshold. 3 LA method for transmitting TDM signals over an asynchronous Wifi Net
work as claimed in claim 17, when there is no packet variation constant
read clock of 2.048 MHz is generated. 32.A method for transmitting TDM signals over an asynchronous Wifi Net
work as claimed in claim 17, when there is a packet variation i.e. moving
towards the full flag of block RAM, constant read clock of 2.080 MHz is
generated wherein the upper threshold (12KB) reaches the normal threshold
(8kB) after the duration of 1 sec. 33.A method for transmitting TDM signals over an asynchronous Wifi
Network as claimed in claim 17, when there is a packet variation i.e.
moving towards the empty flag of block RAM, constant read clock of 2.016

MHz is generated wherein the lower threshold (4KB) reaches the normal
threshold (8kB) after the duration of 1 sec. 34.Use a system for transmitting TDM signals over an asynchronous Wifi
Network Digital clock Buffer Manager: El over Wireless Network. 35.Use a method transmitting TDM signals over an asynchronous Wifi
Network using Digital clock Buffer Manager: El over Wireless Network.
Dated this the 16th day of October 2006