The present invention relates to a frequency digital converter.
Such digital converters are used for carrying out a frequency down-conversion, transforming actual samples from an analogue/digital converter and centered on a transposed frequency f0, into complex samples I/Q in a base band, followed by low-pass 5 filtering and decimation.
These frequency digital converters are often implemented on a printed circuit of the array of programmable gates type, further called FPGA (“field-programmable gate array”), operating at a processing speed FFPGA of less than the sampling frequency Fe of the analogue/digital converter. The frequency conversion is therefore not accomplished 10 continuously and in real time, or else it is necessary to limit the sampling frequency by the processing frequency FFPGA if continuous and real time processing is desired.
Sometimes several analogue/digital converter blocks are used at sampling frequencies less than FFPGA in order to have a wide band piece of equipment, but junction problems between the different blocks arise. 15
With reference to the graph of Fig. 1 illustrating in abscissas the sampling frequency Fe and in ordinates the processing frequency FFPGA, and by noting as FFPGA_MAX the maximum processing value of the FPGA, the hatched area Z1 is the area which may be used during continuous processing and in real time, and the frequency Fe1 is the maximum sampling frequency which may be used for continuous and real time 20 processing.
Therefore it is desirable to have a digital converter giving the possibility of reducing the number of calculations required for converting on the one hand, and carrying out the processing on the other hand, at the processing frequency FFPGA of the FPGA giving the operating rhythm of the converter, of the samples sampled at a sampling frequency Fe 25 greater than this processing frequency FFPGA.
For this purpose, according to a first aspect, the invention proposes a frequency digital converter suitable for receiving signal samples and comprising:
- at least one frequency transposition block adapted for transposing in frequency said received samples; 30
- at least one filtering block adapted for filtering said transposed samples and for delivering filtered samples y(n) verifying the formula y(n) =c(0).x(n) + c(1).x(n-1) + c(2).x(n-2)+… + c(p-1).x(n-p+1) + c(p).x(n-p) + c(p-1).x(n-p-1)+…+…+c(1).x(n-2.p+1) + c(0).x(n-2.p), wherein x() are the transposed samples and c(0),…c(p) are real coefficients of the filter; and 35
2
- a set of memories,
said frequency converter being adapted for, during a cycle for determining the value of the filtered sample y(n), carrying out the operations of
- calculating the first terms c(0).x(n), c(1).x(n-1), c(2).x(n-2),…, c(p).x(n-p) by multiplying the respective coefficients and transposed samples, and storing at 5 least certain of said first calculated terms in the set of memories;
- reading in the set of memories, at least certain of the second terms c(p-1).x(n-p-1),…, c(1).x(n-2.p+1), c(0).x(n-2.p), calculated and stored during previous cycles for determining the value of filtered samples y(n-m), with m being a strictly positive integer; and 10
- determining y(n) by summing the first and second terms.
Such a converter, by making use of the properties of the symmetrical filters gives the possibility of reducing the calculation volume to be carried out and therefore limiting the resources required for the conversion.
In embodiments, the frequency digital converter according to the invention further 15 includes one or several of the following features:
- the converter is adapted for receiving real sampled samples of the signal and for delivering complex signals I/Q, stemming from the filtering by the filtering block after transposition with the transposition block, of said real sampled samples,
said converter including parallel chains for processing the signals I and the signals Q, at 20 least one of said processing chains I, Q comprising V parallel routes each adapted for carrying out a frequency transposition, said power converter being adapted for selectively distributing the real samples among said routes, each real sample being provided to the ith route, i = 1 to V, n being a positive integer;
- the converter is adapted for operating in a clocked way by a frequency clock 25 signal, a so called operating frequency, and adapted for receiving the sampled real samples according to a sampling frequency, V being equal to the quotient of the sampling frequency by the operating frequency;
- the frequency transposition comprises a multiplication of the samples by a sine or cosine with a frequency equal to Fe/4, V/2 routes thereby delivering always zero 30 transposed samples;
- at least the kth and jth parallel routes of said processing chain, k≠j and k, j being integers between 1 and N, comprise a filtering sub-block adapted for determining the filtered signal y(N.n+i-1) =c(0).x(N.n+i-1) + c(1).x(N.n+i-1-1) + c(2).x(N.n+i-1-2)+… + c(p-1).x(N.n+i-p)+ c(p).x(N.n+i-1-p)+ c(p-1).x(N.n+i-1-p-1)…+c(1).x(N.n+i-1-2.p+1) + 35
3
c(0).x(N.n+i-1-2.p), wherein x() are signals stemming from the transposition in said processing chain, with i = j on the jth route, and i = k on the kth route,
the filtering sub-block (12Q_1, 12Q_2) of the kth route, respectively of the jth route, being adapted for calculating the first terms c(0).x(N.n+i-1),…,c(p).x(N.n+i-1-p) by multiplying the respective transposed samples and coefficients, in order to store at least certain of 5 said first calculated terms in the set of memories and for reading, in the set of memories, at least certain of the second terms c(p-1).x(N.n+i-1-p-1),…, c(0).x(N.n+i-1-2.p), calculated and stored during previous cycles for determining the value of filtered samples y(n-m), with m being a strictly positive integer, certain of said second terms having been calculated by the filtering block (12Q_1, 12Q_2) of the jth route, respectively of the kth route. 10
According to a second aspect, the present invention proposes a processing method in a frequency converter adapted for receiving signal samples, the method comprising the following steps:
- receiving signal samples;
- frequency transposition of said received samples; 15
- filtering said transposed samples, the filtered samples y(n) verifying the formula y(n) =c(0).x(n) + c(1).x(n-1) + c(2).x(n-2)+… + c(p-1).x(n-p+1) + c(p).x(n-p) + c(p-1).x(n-p-1)+…+…+c(1).x(n-2.p+1) + c(0).x(n-2.p), wherein x() are the transposed samples and c(0),…c(p) are real coefficients of the filter;
said processing method comprising the following steps, during a cycle for determining the 20 value of the filtered sample y(n):
- calculating the first terms c(0).x(n), c(1).x(n-1), c(2).x(n-2),…, c(p).x(n-p) by multiplying the respective coefficients and transposed samples, and storing at least certain of said first calculated terms in a set of memories;
- reading, in the set of memories, at least certain of the second terms c(p-1).x(n-25 p-1),…, c(1).x(n-2.p+1), c(0).x(n-2.p), calculated and stored during previous cycles for determining the value of filtered samples y(n-m), with m being a strictly positive integer; and
- determining y(n) by summing the first and seconds terms.
These features and advantages of the invention will become apparent upon 30 reading the description which follows, only given as an example, and made with reference to the appended drawings, wherein:
- Fig. 1 represents a graph illustrating the relationship between the sampling frequency and the processing frequency in the prior art on the one hand and according to the invention on the other hand; 35
4
- Fig. 2 is a view of a frequency converter of the down type in an embodiment of
the invention;
- Fig. 3 is a detailed view of a frequency converter of the down type in an
embodiment of the invention;
5 - Fig. 4 is a flow chart of steps applied in an embodiment of the invention.
Fig. 2 is a view of a frequency converter of the down type 10 in an embodiment of
the invention.
The frequency converter of the digital down type 10 or DDC (« Digital Down
Converter ») 10 is adapted for receiving as an input real samples z(n) in a transposed
10 band.
The DDC (“Digital Down Converter”) 10 is adapted for delivering at the output
complex samples Z(n) in a base band, i.e. for which the spectrum is centered on 0.
z(n) is the sample corresponding to the sampling time tn = n/Fe and Z(n) is the
sample delivered at Tinit+n/Fe wherein n is a positive integer and the initial sampling
15 instant.
Each complex sample is written as Z(n) = I(n) +i.Q(n), wherein I(n) is the in-phase
component and Q(n) is the quadrature component.
The spectrum of these samples z(n) is thus centered around the carrier frequency
f0.
20 The sampling frequency Fe of these samples z(n) is for example the sampling
frequency of an analogue/digital converter located upstream from the DDC 10.
The DDC 10 is an integral part of a FPGA and its operations are clocked by a
clock signal of the FPGA having a frequency equal to FFPGA, designated as a processing
frequency.
25 DDC 10 is adapted for continuously processing in real time the received samples
z(n). The DDC 10 includes a processing route VI and a processing route VQ.
The DDC 10 is adapted for providing each real sample z(n) at the input of each
processing route VI and VQ.
The DDC 10 comprises, on the route VI, a base band transposition block 11I, a low
30 pass filter 12I and a decimating block 13I.
The DDC 10 comprises, on the route VQ, a base band transposition block 11Q, a
low pass filter 12Q and a decimating block 13Q.
The frequency transposition block 11I si adapted for multiplying a real sample z(n)
received at the input with a cosine function at the frequency f0 : cos(2 f0tn).
5
The frequency transposition block 11Q is adapted for multiplying a real sample z(n)
with the sine function at the frequency f0 : -sin(2 f0tn).
Each decimating block 13I, 13Q is adapted for reducing the number of samples, in
the relevant case, the number of samples is reduced by a factor 2. This decimation
reduces the clocking on the route I, respectively Q, from 5 800 MHz to 400 MHz.
In the relevant case, each filter 12I, 12Q is a finite impulse response filter, a so
called FIR (“Finite Impulse Response”) filter.
The output y(n) of each of these filters 12I, 12Q is written in the form of a same
linear combination function of the input signal x(n) of the filter:
10 y(n) = c(0).x(n) + c(1).x(n-1) + c(2).x(n-2)…+ c(M-1).x(n-M+1) (formula 1)
wherein M is a positive integer.
In the described embodiment, each filter is a symmetrical filter, with the following
properties:
- the number M of coefficients is odd: M= 2.p+1 with p being a positive integer;
15 - the coefficients are real numbers and are symmetrical c(i) = c(2.p-i) i = 0 to p;
- the odd coefficients are zero except if the odd coefficient is from among c(p)
and c(p+1).
In the described embodiment, each filter is further normalized by the value of the
central coefficient c(p).
20 The formula giving y(n) may therefore be written as:
y(n) =c(0).x(n) + c(1).x(n-1) + c(2).x(n-2)+… + c(p-1).x(n-p+1) + c(p).x(n-p) + c(p-
1).x(n-p-1)…+c(1).x(n-2.p+1) + c(0).x(n-2.p).
It is noted that the last p terms of the linear combination, starting from the term c(p-
1).x(n-p-1) until the term c(0).x(n-2.p) are terms used for determining previous outputs of
25 the filter:
c(0).x(n-2.p) enters the calculation of y(n-2.p),
c(1).x(n-2.p+1) enters the calculation of y(n-2.p+2),
c(p-1).x(n-p-1) enters the calculation of y(n-2); and
more generally c(i).x(n-2p+i) enters the calculation of y(n-2p+2i), i = 0 to p-1.
30 Similarly, the first p terms of the linear combination, from the term c(0).x(n) up to
the term c(p-1).x(n-p+1) are terms used for determining the subsequent outputs of the
filter.
According to an aspect of the invention, the number of multiplications to be
performed, and therefore the number of multipliers to be set into place will be reduced by
35 setting into place, during the calculation of an output y(n) of the filter, the storage in
6
memory of the first p terms of the linear combination following their calculation, called
hereafter intermediate results, and extraction and reuse of the intermediate results stored
in memory previously during the calculation of the preceding outputs, in order to
determine the last p terms of the linear combination.
5 The DDC 10 according to the invention is adapted for producing processing
operations on each route parallel to the frequency FFPGA and delivering at the output a flow
I and a flow Q, each flow being a continuous flow and in real time of samples at Fe/2.
In the relevant particular case:
- p is selected to be equal to 27, the number of coefficients is therefore equal to 55;
10 - the coefficients are the following: c(0), c(1), c(2), …, c(25), c(26), c(27), c(28),
c(29), …, c(52), c(53), c(54);
- c(0), c(2), …, c(52), c(54) have a value between -1 and 1 after normalization with
the central coefficient c(27);
- the odd coefficients are zero c(1)=c(3)= … =c(25)=c(29)= … =c(51)=c(53)=0
15 except if c(27) is equal to 1 following the normalization of the coefficients;
- the transposed frequency f0 is equal to 200 MHz, the sampling frequency Fe is
equal to 800 MHz, the processing frequency FFPGA of the FGPA is equal to 200 MHz.
But the invention may of course be applied with other values for p and these
frequencies.
20 Successive samples y(n), y(n+1) on the route I at the output of the filter 12I are
therefore written as depending on the samples x(i) at the input of the filter 12I because the
transposition gives rise to a sample equal to 0 every two samples because of the value of
the 2 f0ti :
25
as the zero samples at the input following the transposition and the zero coefficients are
superposed and y(n) is a sum of 28 terms; and
30
Because of the canceling out of the terms except for one term, either with zero
samples or with zero coefficients, y(n+1) = x(n-26). Therefore there is no calculation to be
done, just a delay is applied.
7
Successive samples y(n), y(n+1) on the route Q at the output of the filter 12Q are
therefore written similarly depending on the samples x(i) at the input of the filter 12Q
because the transposition gives rise to a sample equal at every two samples because of
the value of the 2 f0ti: y(n) = x(n-27) and y(n+1) is written as a sum of 28 terms.
The decimation of the samples by 5 2 amounts to only retaining one sample out of 2,
i.e. according to the embodiments either y(n) or y(n+1).
In the relevant case described below, it is considered that the samples y(n) are
suppressed and the samples y(n+1) are retained, which induces the application of a delay
on the route I and of an FIR filter with 28 coefficients as described below.
10 As the coefficients are symmetrical (c(0) = c(54), c(1)=c(53)=0, c(2)=c(52), ...), this
therefore implies 14 multiplications.
Fig. 3 illustrates a particular embodiment of the DDC 10 illustrated in Fig. 2.
The DDC 10 in this embodiment comprises a distributor 15 adapted for receiving
the samples z(n) at the frequency Fe =800 MHz and for processing the samples N by N,
15 with N = Fe/ FFPGA, here N= 4.
The processing of this distributor 15 comprises the provision in parallel of each of
these N samples at the input of the route VI and the provision in parallel of each of these
N samples at the input of the route VQ.
The route VI of the DDC 10 thereby comprises N sub-routes VI_0,…, VI_N-1.
20 Each sub-route VI_i i =0 to N-1, selectively receives the samples z(kN+i), with k
being a natural integer.
Each sub-route VI_i is adapted for carrying out in parallel the other sub-routes of the
route VI, frequency transposition in a base band by multiplication with cos(2 f0tn) in a
transposition block in a base band 11I_i, and the FIR filtering by a filtering block 12I_i.
25 Similarly, the route VQ of the DDC 10 thereby comprises N sub-routes VQ_0,…,
VQ_N-1.
Each sub-route VQ_i i =0 to N-1, selectively receives the samples z(kN+i), with k
being a natural integer.
Each sub-route VQ_i is adapted for carrying out in parallel the other sub-routes of
30 the route VQ, the frequency transposition in a base band by the multiplication by -
sin(2 f0tn) in a transposition block in a base band 11Q_i, and the FIR filtering by a filtering
block 12Q_i.
The filtering blocks 12Q_1 and 12Q_3 are further adapted for calculating and storing
in memory the intermediate results, for example in shift registers and communicating
8
between them these intermediate results, for example via input/output means of said
access registers.
In the relevant particular case with the values indicated above for p and the
frequencies, because Fe/f0 = 4, it is found that the base band transposition on the sub5
routes VI_1, VI_3, VQ_0 and VQ_2 always delivers a zero value. Accordingly, in the relevant
particular case, the DDC 10 only includes in reality in each of the routes VI and VQ N/2 = 2
sub-routes: VI_0 and VI_2 in the route VI and VQ_1 and VQ_3 in the route VQ.
In the relevant embodiment, because Fe/f0 = 4, tn= n/Fe and signals received on
each sub-route:
10 - on route VI_0, multiplication by cos(2 f0tn) in the transposition block in a base
band 11I_0 is equivalent to the multiplication by a factor 1 ;
- on route VI_2, the multiplication by cos(2 f0tn) in the transposition block in a base
band 11I_2 is equivalent to the multiplication by a factor -1 ;
- on the route VQ_1, the multiplication by -sin (2 f0tn) in the transposition block in a
15 base band 11Q_1 is equivalent to the multiplication by a factor -1 ;
- on the route VQ_3, the multiplication by -sin(2 f0tn) in the transposition block in a
base band 11Q_3 is equivalent to multiplication by a factor 1.
On the sub-routes VI_0 and VI_2, application of the filtering is equivalent to the
application of a delay by applying the transfer function z -13: if the output of the filter on the
20 sub-route VI_0 is called I0 and the output of the filter on the sub-route VI_2 is called I2:
I0(n=4k)= z(n-14) and I2(n=4k+2)= z(n-12). Indeed, the theoretical delay corresponds to p-
1 (= 26) as indicated earlier divided by two subsequent to the decimation operation, i.e. (p-
1)/2 (= 13); as the filtering calculation on the route Q lasts for a longer time than 13 clock
cycles, the route I is further delayed so as to be synchronized with the route Q.
25 The samples from the passing in the base band of route VQ_1 and of the route VQ_3
are provided at the input of each FIR filtering block 12Q_1 and 12Q_3.
The filtering block 12Q_1 on the sub-route VQ_1 is adapted for determining the result
of the linear combination; if the output of the filter on the sub-route VQ_1 is called Q1 I:
Q1(n=4k+1)= -c(0)z(4k+1) + c(2)z(4k-1) -c(4)z(4k-3) …+ c(26)z(4k-25) - c(26)z(4k-27)…-
30 c(0)z(4k-53).
To do this, it is adapted for calculating each term of the first half of the linear
combination, i.e. the terms c(0)z(4k+1), c(2)z(4k-1), c(4)z(4k-3) …, c(26)z(4k-25)
depending on the coefficients of the filter c(0), …, c(26) and on the received base band
samples –z(4k+1), + z(4k-1)…, z(4k-25), and for storing in memory as an intermediate
9
result the result of each of these terms. Each of these intermediate results stored in memory is made accessible additionally to the filtering block 12Q_3.
The filtering block 12Q_1 is further adapted for extracting from the memories in which they were stored previously, the terms of the second half of the linear combination, i.e. c(26)z(4k-27), c(24)z(4k-29),…,c(0)z(4k-53), and for determining the sum of the terms 5 of the first half and of the terms of the second half in return for taking into account the signs of these terms.
Similarly, the filtering block 12Q_3 on the sub-route VQ_3 is adapted for determining the result of the linear combination; if the output of the filter on the sub-route VQ_3 is called Q3: 10
Q3(n=4k+3)= c(0)z(4k+3) - c(2)z(4k+1) +c(4)z(4k-1) …- c(26)z(4k-23) + c(26)z(4k-25)…+ c(0)z(4k-51).
To do this, it is adapted for calculating each term of the first half of the linear combination, i.e. the terms c(0)z(4k+3), c(2)z(4k+1), c(4)z(4k-1) …, c(26)z(4k-23) depending on the coefficients of the filter c(0), …, c(26) and on the received base band 15 samples z(4k+3), z(4k+1)…, -z(4k-23), and for storing in memory as an intermediate result the result of each of these terms. Each of these intermediate results stored in memory is made further accessible to the filtering block 12Q_1.
The filtering block 12Q_3 is further adapted for extracting from the memories in which they were stored previously, the terms of the second half of the linear combination, 20 i.e. c(26)z(4k-25), c(24)z(4k-27),…,c(0)z(4k-51), and for determining the sum of the terms of the first half and of the terms of the second half in return for the taking into account of the signs of these terms.
The DDC 10 thus delivers simultaneously at the output of the route I, the samples I0(n=4k) et I2(n=4k+2), and, at the output of the route Q, the samples Q1(n=4k+1) and 25 Q3(n=4k+3).
It is considered that the even samples I of the DDC 10 are provided by the sub-route I0, that the odd samples I of the DDC 10 are provided by the sub-route I2, that the even samples Q of the DDC 10 are provided by the sub-route Q1, that the odd samples Q of the DDC 10 are provided by the sub-route Q3. 30
The invention proposes, according to an aspect, a processing method in a frequency converter.
In an embodiment, with reference to Fig. 4, the following steps are applied. 10
In a step 101, the samples z(n) at the frequency Fe =800 MHz are received in the
DDC 10 and provided in parallel, N per N, as an input to the route VI and as an input to
the route VQ.
In a step 102, in each sub-route VP_i in parallel with the other sub-routes of the
route VI, the base band frequency transposition by multiplication 5 by cos(2 f0tn) in a base
band transposition block 11I_i is carried out, P=I or Q and i =0 to N-1.
Each sub-route VP_i selectively receives the samples z(kN+i), with k being a natural
integer.
The samples from the transposition carried out in a sub-route VP_i are provided to
10 the other sub-routes of the same route VP.
In a step 103, in each sub-route VP_i in parallel with the other sub-routes of the
route VP, the filtered samples P(kN+i) are determined by means of the formula P(kN+i)
=c(0).x(kN+i) + c(1).x(kN+i -1) + c(2).x(kN+i -2)+… - c(p).x(kN+i -p) + c(p).x(kN+i -p-
1)…+c(1).x(kN+i -2.p+1) + c(0).x(kN+i -2.p), wherein x(n) is the result of the frequency
15 transposition of the sample z(n).
The intermediate results determined in each sub-route are stored in memory and
communicated and/or accessible between sub-routes of a same route for reuse in steps
for determining the values of the filtered samples of a higher rank.
In step 104, the samples I0(n=4k) and I2(n=4k+2) and, at the output of the route Q,
20 the samples Q1(n=4k+1) and Q3(n=4k+3) are simultaneously delivered at the output of the
DDC 10.
Of course, the specific embodiments described above with reference to Fig. 3 may
also be implemented by the method according to the invention.
The converter according to the present invention therefore gives the possibility of
25 processing in a continuous flow the sampled real samples at Fe, here 800 MHz, at the
frequency FFPGA for processing FGPA, here 200 MHz, delivering a continuous flow and in
real time of samples I at Fe/2, here 400 MHz, and delivering a continuous and real time
flow of samples Q to Fe/2.
Again with reference to the graph of Fig. 1, the area covered by points Z2 is the
30 area which may be utilized in continuous and real time processing according to the
invention. The limitation brought by the sampling frequency which may be used for
continuous and real time processing corresponds to the maximum sampling rate of the
analogue/digital converter upstream from the frequency converter and is no longer limited
by the FPGA.
11
The parallelization of the processing operations on several sub-routes I and several sub-routes Q, the utilization of the properties of the filter and of the storage in memory and reuse of the intermediate results give the possibility both of carrying out the processing operations at reduced rates, which the FPGAs may support, and of limiting the number of required resources. 5
It will be noted that the parallelization of the processing operations on several sub-routes I and several sub-routes Q may be applied in a converter according to the invention, and this without applying storage in memory and reuse of the intermediate results.
Conversely, the storage in memory and reuse of the intermediate results making 10 use of the properties of the symmetrical filters may be applied in a frequency converter according to the invention without applying parallelization of the processing operations on several sub-routes I and several sub-routes Q. In particular, an application was described above to a frequency converter of the down type, but the utilization of the properties of the symmetrical filters according to the invention may in another embodiment be applied in a 15 up type frequency converter.
In the particular embodiment described above as a reference, a transposed frequency f0 of 200 MHz, a sampling frequency Fe of 800 MHz and a processing frequency FFPGA of 200 MHz were considered. However, the invention may be applied for other values of these frequencies. 20
As N is equal to the quotient Fe / FFPGA, the processing will be typically parallelized on N routes for the route I, and on N routes for the route Q. The processing frequency FFPGA thus sets the number N of parallel routes to be set into place, which may thus be equal notably to a power of 2: 2, 4, 8, 16 etc.
In embodiments, the value of the transposed frequency f0 will further be set equal 25 to Fe/4, like in the particular embodiment described, so that all the samples delivered by certain of these parallel routes are systematically zero, so as to thus achieve in a simple way decimation and reduce the number of parallel sub-routes.
Moreover the relevant FIR filter had normalized coefficients relatively to the central coefficient and was symmetrical. The proposed implementation gives the possibility of 30 easily modifying the number of its coefficients. The value of the latter depends on the sampling frequency Fe and is therefore to be adapted accordingly. In other embodiments, the coefficients are not normalized, the reuse of the intermediate results may of course be also applied in this case. 12
In the case of an embodiment of the invention with a non-symmetrical FIR filter, the intermediate results may not be reused. In this case, the number of multipliers required for applying the filtering is doubled.

I/We Claim:
1.- A frequency converter (10) adapted for receiving signal samples and comprising:
- at least one frequency transposition block (11Q_1, 11Q_2) adapted for transposing in 5 frequency said received samples;
- at least one filtering block (12Q_1, 12Q_2) adapted for filtering said transposed samples and for delivering filtered samples y(n) verifying the formula y(n) =c(0).x(n) + c(1).x(n-1) + c(2).x(n-2)+… + c(p-1).x(n-p+1) + c(p).x(n-p) + c(p-1).x(n-p-1)+…+…+c(1).x(n-2.p+1) + c(0).x(n-2.p), wherein x() are transposed samples and c(0),…c(p) are real coefficients of 10 the filter; and
- a set of memories;
said frequency converter being adapted for, during a cycle for determining the value of the filtered sample y(n), carrying out operations for
- calculating the first terms c(0).x(n), c(1).x(n-1), c(2).x(n-2),…, c(p).x(n-p) by 15 multiplying the respective coefficients and transposed samples, and storing at least certain of said first calculated terms in the set of memories;
- reading, in the set of memories, at least certain of the second terms c(p-1).x(n-p-1),…, c(1).x(n-2.p+1), c(0).x(n-2.p), calculated and stored during the previous cycles for determining the value of filtered samples y(n-m), with m 20 being a strictly positive integer; and
- determining y(n) by summation of the first and second terms.
2.- The frequency converter (10) according to claim 1, adapted for receiving sampled real signal samples and for delivering complex signals I/Q, from the filtering by 25 the filtering block after transposition with the transposition block of said sampled real samples,
said converter including parallel chains for processing (VI, VQ) of the signals I and of the signals Q, at least one of said processing chains I, Q comprising V parallel routes (VQ_1, VQ_2) each adapted for carrying out frequency transposition, said power converter being 30 adapted for selectively distributing the real samples between said routes, each (V.n+i-1)th real sample being provided to the ith route, i = 1 to V, n being a positive integer.
3.- The frequency converter (10) according to claim 2, adapted for operating in a way clocked by a clock frequency signal, a so called operating frequency (fFPGA), and 35
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adapted for receiving the real samples sampled according to a sampling frequency (Fe), V being equal to the quotient of the sampling frequency by the operating frequency.
4.- The frequency converter (10) according to claim 3, wherein the frequency transposition comprises a multiplication of the samples with a sine or cosine of frequency 5 (f0) equal to Fe/4, V/2 routes thereby delivering always zero transposed samples.
5.- The frequency converter (10) according to one of claims 2 to 4, wherein at least the kth and jth parallel routes of said processing chain (VQ), k≠j and k, j integers between 1 and N, comprising a filtering sub-block adapted for determining the filtered signal y(N.n+i-10 1) =c(0).x(N.n+i-1) + c(1).x(N.n+i-1-1) + c(2).x(N.n+i-1-2)+… + c(p-1).x(N.n+i-p)+ c(p).x(N.n+i-1-p)+ c(p-1).x(N.n+i-1-p-1)…+c(1).x(N.n+i-1-2.p+1) + c(0).x(N.n+i-1-2.p), wherein x() are signals from the transposition in said processing chain, with i = j on the jth route, and i = k on the kth route,
the filtering sub-block (12Q_1, 12Q_2) of the kth route, respectively of the jth route, being 15 adapted for calculating the first terms c(0).x(N.n+i-1),…,c(p).x(N.n+i-1-p) by multiplying the respective coefficients and transposed samples, in order to store at least certain of said first terms calculated in the set of memories and for reading, in the set of memories, at least certain of the second terms c(p-1).x(N.n+i-1-p-1),…, c(0).x(N.n+i-1-2.p), calculated and stored during previous cycles for determining the value of filtered samples 20 y(n-m), with m being a strictly positive integer, certain of said second terms having been calculated by the filtering sub-block (12Q_1, 12Q_2) of the jth route, respectively of the kth route.
6.- The processing method in a frequency converter adapted for receiving signal 25 samples, the method comprising the following steps:
- receiving the signal samples;
- transposing in frequency said received samples;
- filtering said transposed samples, the filtered samples y(n) verifying the formula y(n) =c(0).x(n) + c(1).x(n-1) + c(2).x(n-2)+… + c(p-1).x(n-p+1) + c(p).x(n-p) + c(p-1).x(n-p-30 1)+…+…+c(1).x(n-2.p+1) + c(0).x(n-2.p), wherein x() are the transposed samples and c(0),…c(p) are the real coefficients of the filter;
said processing method comprising the following steps, during a cycle for determining the value of the filtered sample y(n): 15
- calculating the first terms c(0).x(n), c(1).x(n-1), c(2).x(n-2),…, c(p).x(n-p) by multiplying the respective coefficients and transposed samples, and storing at least certain of said first terms calculated in a set of memories;
- reading, in the set of memories, at least certain of the second terms c(p-1).x(n-p-1),…, c(1).x(n-2.p+1), c(0).x(n-2.p), calculated and stored during previous 5 cycles for determining the value of filtered samples y(n-m), with m being a strictly positive integer; and
- determining y(n) by summation of the first and second terms.
7.- The processing method according to claim 6, for a frequency converter adapted 10 for receiving sampled real signal samples and delivering complex I/Q signals from the filtering after transposition of said sampled real samples, said method comprising the steps:
- processing in parallel the real samples on a processing chain I for signals I and a Q processing chain for signals Q (VI, VQ); 15
- on at least one of said parallel processing chains comprising V parallel routes (VQ_1, VQ_2), selective distribution of the real samples among said routes, each real (V.n+i-1)th sample being provided to the ith route, i = 1 to V, n being a positive integer.
8.- The processing method according to claim 7, according to which the processing 20 operation is clocked by a clock frequency signal, a so called operating frequency (fFPGA), and according to which the sampled real samples are received according to a sampling frequency (Fe), and V is equal to the quotient of the sampling frequency by the operating frequency.
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9.- The processing method according to claim 8, according to which the frequency transposition comprises a multiplication of the samples by a sine or cosine of frequency (f0) equal to Fe/4, V/2 routes thereby delivering always zero transposed samples.
10.- The processing method according to one of claims 7 to 9, comprising, on at 30 least the kth and jth parallel routes of said processing chain (VQ), k≠j and k, j integers between 1 and N, the determination of the filtered signal y(N.n+i-1) =c(0).x(N.n+i-1) + c(1).x(N.n+i-1-1) + c(2).x(N.n+i-1-2)+… + c(p-1).x(N.n+i-p)+ c(p).x(N.n+i-1-p)+ c(p-1).x(N.n+i-1-p-1)…+c(1).x(N.n+i-1-2.p+1) + c(0).x(N.n+i-1-2.p), wherein x() are signals 16
from the transposition in said processing chain, with i = j on the jth route, and i = k on the kth route,
and comprising on the kth route, respectively the jth route, the calculation of the first terms c(0).x(N.n+i-1),…,c(p).x(N.n+i-1-p) by multiplying the respective coefficients and transposed samples, the storage of at least certain of said first calculated terms in the set 5 of memories and the reading in the set of memories, of at least certain of the second terms c(p-1).x(N.n+i-1-p-1),…, c(0).x(N.n+i-1-2.p), calculated and stored during previous cycles for determining the value of filtered samples y(n-m), with m being a strictly positive integer, on the jth route, respectively the kth route.