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Digital To Analog Conversion System And Method Of Conversion Thereof Based On Serial Communication

Abstract: Low cost micro-controller based systems suffer from lack of adequate on-chip resources for generating PWM/analog output voltages. Traditionally on-chip "capture and compare blocks " coupled with a dedicated timer can be used to generate PWM voltages, this approach ties up on-chip timer resource and event counting hardware for PWM generation , restricting the system capabilities for timer/counter intensive applications. This invention proposes use of on-chip serial synchronous communication channel for generating analog output. This approach does not restrict system capabilities for timing/event counting tasks. Many low-cost stand-alone systems do not need synchronous communications and hence the associated hardware can be gainfully employed for analog voltage generation.

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Notices, Deadlines & Correspondence

Patent Information

Application #
Filing Date
15 October 2007
Publication Number
50/2007
Publication Type
INA
Invention Field
COMPUTER SCIENCE
Status
Email
Parent Application
Patent Number
Legal Status
Grant Date
2018-03-17
Renewal Date

Applicants

TATA MOTORS LIMITED
BOMBAY HOUSE, 24 HOMI MODY STREET, HUTATMA CHOWK, MUMBAI

Inventors

1. VISHWAS VAIDYA
BOMBAY HOUSE, 24 HOMI MODY STREET, HUTATMA CHOWK, MUMBAI 400001.
2. NAMITA JOSHI
BOMBAY HOUSE, 24 HOMI MODY STREET, HUTATMA CHOWK, MUMBAI 400001.

Specification

FORM 2
THE PATENTS ACT 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See Section 10; rule 13)
TITLE OF THE INVENTION
Digital To Analog Conversion System And Method Of Conversion Thereof Based On Serial Communication
APPLICANTS
TATA MOTORS LIMITED, an Indian company
having its registered office at Bombay House,
24 Homi Mody Street, Hutatma Chowk,
Mumbai 400 001 Maharashtra, India
INVENTORS
Mr. Vishwas Vaidya, Ms. Namita Joshi both Indian nationals
of TATA MOTORS LIMITED,
an Indian company having its registered office
at Bombay House, 24 Homi Mody Street, Hutatma Chowk,
Mumbai 400 001 Maharashtra, India
PREAMBLE TO THE DESCRIPTION
The following specification particularly describes the invention and the manner in
which it is to be performed.

FIELD OF INVENTION
This invention relates to Digital to Analog Conversion System and more particularly it relates to Digital to Analog Conversion System which is based on serial communication.
BACKGROUND OF THE INVENTION
Electronic systems based on micro-controllers need analog output signals to drive analog output devices such as various meters having needle point indicators, pneumatic/ hydraulic solenoids, slave control systems requiring analog commands such as motion controllers, battery chargers etc.
Micro-controller based electronic systems generally suffer from lack of on-chip Digital to Analog Conversion (DAC) channels. The chip manufacturers generally recommend the use of on-chip timer based Pulse Width Modulated (PWM) signal generators followed by external filters. Although this technique is widely used, it suffers from following drawbacks:
- It ties-up a timer resource only for PWM purpose, thereby making it unavailable for other tasks in the application.
- Use of PWM generator is mutually exclusive with on chip event counting hardware.
Hence applications requiring event counting cannot use PWM generation.
US 5,764,165 describes a pulse width modulated Digital to Analog Converter (PWM DAC) that includes a pulse generator for generating width modulated pulses in accordance with a digital control value is set forth. The generator includes a
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clock for generating a clocking signal, a counter, responsive to the clocking signal for generating repeating sequences of N bit counts, each sequence representing a count interval. The PWM DAC further includes a bit rotator for receiving the sequences of N-bit counts and rotating bit positions of at least a most significant of N bits. A latch holds digital control value, whereby a comparator compares the control value with each one of the rotated bit count to put out the width modulated pulses during the count interval. The rotated bit count increase the frequency of the comparator, by substantially linear manner, such that subsequent filtering can be accomplished with minimum time requirements
This approach uses complex hardware circuits, significantly increasing component count and hence not suitable for use in micro-controller based systems, where main purpose of using micro-controller is to reduce component count. Also this approach lacks flexibility of programming, clock rate, duty cycle etc. which is required to cater real time demands of various applications
US5,691,721 teaches a pulse-width-modulated digital-to-analog converter is responsive to a digital control value for switching between a high gain mode and a low gain mode. The converter includes a free-running rollover counter, a reference register and a comparator. Pulses from a comparator are split into two paths, one path including a switch, and fed into a plurality of resistive elements connected to a common output node. Depending on the state of the switch, the network's output value will either follow its input or be a fraction thereof, without change of duty cycle or output impedance. The output node may be connected to a capacitive element to form a low pass filter for generating an analog waveform.
This approach uses similar hardware based approach like US 5,764,165 discussed above except for providing two different paths for different gains. Hence it suffers
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from similar drawbacks pertaining to lack of programmability and high component count.
"Make a DAC with a Micro-controller's PWM timer" published in EDN magazine September 5, 2002 issue by Mike Mitchell, Texas Instruments teaches a DAC technique based on micro-controller's on-chip timer and event counting hardware to generate both AC and DC analog signals.
This approach though suitable for implementation with micro-controller based systems, consumes timer/event counter resources of the micro-controller thus making them unavailable for event counting/timing applications.
OBJECTS OF INVENTION
The main object of this invention is to provide a Digital to Analog Conversion
system based on serial communication.
Another object of this invention is to provide Digital to Analog Conversion system
with Pulse Width Modulated (PWM) output based on on-chip serial transmission
resources.
Yet another object of this invention is to provide Digital to Analog Conversion system based on serial communication which is simple in construction and cost-effective.
STATEMENT OF INVENTION
Digital to Analog Conversion technique, which makes use of on-chip resources comprising of serial synchronous transmitter circuits. This technique basically uses
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an on-chip embedded algorithm to generate PWM output at of the "Transmitter Pin" which is connected to a low-pass filter network. Output of the filter network is connected to analog output devices like analog meters, analog set-points to motion control systems, simulated sensor signals for Hardware In the Loop (HIL) applications etc.
Method of generating analog output signal consists of following steps:
a. Converting the input "raw" digital byte into a sequence of 32 bytes for PWM
generation, (which in turn produces a 256 bit sequence for an 8-bit DAC
implementation)
b. The byte sequence is transmitted on the synchronous serial transmission
output pin of the micro-controller, so that number of "on-state bits"
corresponds to the digital value of the input data.
c. Demodulation of the PWM signal to produce an analog output signal
BRIEF SUMMARY OF THE INVENTION
Digital to Analog conversion system based on serial communication in accordance with this invention basically comprises of embedded micro-controller with input and output interfaces, a PWM generator based on an on-chip serial synchronous transmitter and pulse-width demodulator. Wherein said micro-controller is connected with said input and output interfaces. The said micro-controller is further interfaced with PWM generator using its on-chip serial transmitter hardware means. The serial transmitter output means of said micro-controller is connected to pulse width demodulator network based on low-pass filter. The micro-controller apart from interacting with the said input/output interfaces, runs an algorithm to generate a PWM bit pattern on serial transmitter channel. The 256-bit pattern gives 8-bit resolution for the PWM signal thus generated. The above-said low-pass filter
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connected to the above-said serial transmitter channel demodulates the PWM signal in order to produce filtered analog signal at the output channel.
DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION
Referring now to the drawings wherein the showings are for the purpose of
illustrating a preferred embodiment of the invention only, and not for the purpose of
limiting the same
Fig 1 shows block diagram of Digital to Analog Conversion system based on serial
communication
Fig 2 Shows Flow-chart of overall software used in Digital to Analog Conversion
system based on serial communication
Fig 3 shows Flow-chart of PWM bit pattern Generation used in Digital to Analog
Conversion system based on serial communication
Fig. 4 shows Example waveform of PWM with raw data of 165
Referring to Fig.l, Digital to Analog Conversion system based on serial communication comprises of embedded micro-controller with input and output interfaces, a PWM generator based on an on-chip serial synchronous transmitter and pulse-width demodulator. Wherein said micro-controller is connected with said input and output interfaces. The said micro-controller is further interfaced with PWM generator using its on-chip serial transmitter hardware means. The serial transmitter output means of said micro-controller is connected to pulse width demodulator network based on low-pass filter.
The micro-controller apart from interacting with the said input/output interfaces runs an algorithm to generate a PWM bit pattern on serial transmitter channel. The 256-bit pattern gives 8-bit resolution for the PWM signal thus generated. The
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above-said low-pass filter connected to the said serial transmitter channel
demodulates the PWM signal in order to produce filtered analog signal at the output
channel.
As per application requirements the low-pass filter may be omitted for loads, which
need PWM, driving signals. Table 1 below lists some examples for both PWM and
analog signals
Table 1: Signal Interfaces and Applications

Sr.No. Signal Description Typical Automotive Applications Remarks
1.0 PWM output signal Solenoidsfor pneumatic/hydraulic control.Motor control applications. Low - pass filter not required
2.0 Analog Outputs Analog meters, Set-point commands to slave systems like motion controllers, battery chargers, temperature controllers etc. Low - pass filter required
Referring to Fig 2
Overall software strategy used in said DAC system basically comprises of four
steps.
Step 1, the driver routine for Digital to Analog Conversion (DAC) receives raw digital data from the calling program.
Step 2, the routine converts the input data read in step 1 to a 256-bit pattern (i.e. an equivalent 32 byte pattern) corresponding to the associated PWM output. For example, if the raw data is 165 then the 256 bit pattern generated
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consists of 165 'on-state bits' and 91 'off-state bits. This gives a PWM
signal of duty cycle = (165/256) x 100 = 64.45 %. (This signal is transmitted
on the serial transmit pin and demodulated into a pure analog signal by
means of low-pass filters).
Step 3, the 256 bit sequence prepared in said step 2 is put out on the serial
transmit output channel
Step 4, the PWM cycle is monitored for end of the 256-bit sequence prepared
in said step 3 so that next PWM sequence can be started after that.
Fig 3 explains the core-algorithm, which converts the raw data into a 256-bit pattern or equivalently a 32-byte pattern. The algorithm follows three steps to generate three portions of a typical PWM cycle:
Step 1 transmits appropriate number of 'On-state bytes' each with a value '0xFF'. Number of On-state bytes is given by dividing the Raw Data by 8. (For raw data = 165, Total On-state Bytes generated are 165/8 = 20.
Step 2 transmits a 'Transition Byte', which marks end of 'On-Period' and start of 'Off-period'. Transition byte is based on the remainder of above division (i.e. remainder of 165 Mod 8 = 5 in our case.) This byte consists of a number of consecutive Ts starting from LSB backwards. Value of remainder determines the number of Ts. For remainder = 5, the number T s to be packed are 5, giving transition byte as '0001 1111b' in binary or Ox IF in hexadecimal. All other bits in the transition byte are '0.
Table 2 lists all possible values of the remainder and associated values for the transition bytes.
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Number of "Off-state Bytes" each with a value of 0x00 are computed by subtracting number of 'On' Bytes from 31 (One byte less than 32 to account for Transition Byte.)
Table 2: Values of Transition bytes for Different Remainders

Remainder Transition Byte In Binary form Transition Byte In Hex form
0 0000 0000 0x00
1 0000 0001 0x01
2 0000 0011 0x03
3 0000 0111 0x07
4 0000 1111 0x0F
5 0001 1111 0x1F
6 0011 1111 0x3F
7 0111 1111 0x7F
Step 3 transmits 'Off-state bytes' each with a value of 0x00 for the remaining portion of the PWM cycle.
Fig 4 shows the actual PWM waveform corresponding to a raw data of 165. As already described, 20 bytes in On-Period, Transition byte with a value of 0x1F followed by 11 number of off-state bytes comprise the associated PWM cycle.
The foregoing description is a specific embodiment of the present invention. It should be appreciated that this embodiment is described for purpose of illustration only, and that those skilled in the art may practice numerous alterations and
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modifications without departing from the spirit and scope of the invention. It is intended that all such modifications and alterations be included insofar as they come within the scope of the invention as claimed or the equivalents thereof.
10

WE CLAIM
1. Digital to Analog conversion system based on serial communication comprises of micro-controller, at least one input and output interfaces, and a PWM generator based on an on-chip serial synchronous transmitter, wherein said micro-controller is connected with said input and output interfaces, said micro-controller is further interfaced with PWM generator using its on-chip serial synchronous transmitter , said micro-controller is embedded with an algorithm to generate a PWM bit pattern on serial transmitter channel.
2. Digital to Analog conversion system based on serial communication as claimed in claim 1 wherein said serial synchronous transmitter of said micro controller is further connected to pulse width demodulator network to demodulate the PWM signal in order to produce filtered analog signal at the output channel.
3. Digital to Analog conversion system based on serial communication as claimed in claims 1 and 2 wherein said PWM generator is having 256-bit pattern so as to provide 8-bit resolution for the PWM signal thus generated.
4. Digital to Analog conversion system based on serial communication as claimed in claims 1 to 3 wherein said micro-controller is embedded micro controller.
5. Digital to Analog conversion system based on serial communication as claimed in claims 1 to 4 wherein said demodulator is based on low-pass filter.
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6. Digital to Analog conversion method based on serial communication
comprises of
a. Receiving a raw digital data by driver routine from calling program;
b. Converting the input data of said step (a) to a 256 bit pattern;
c. Transmitting 256 bit pattern formed in said step (b) on serial transmit
output channel;
d. Monitoring end of PWM cycle.
7. Digital to Analog conversion method based on serial communication as
claimed in claim 6 wherein said step (b) further comprises of
a. Dividing raw data by 8 to obtain appropriate number of 'On-state
bytes'
b. Transmitting appropriate number of 'On-state bytes' each with a value
'0xFF'.
c. Forming a transition byte based on reminder of the division carried
out in said step (a)
d. Transmitting a 'Transition Byte' obtained in said step (c)
e. Transmitting 'Off-state bytes' each with a value of 0x00 for the
remaining portion of the PWM cycle.
8. Digital to Analog conversion method based on serial communication as
claimed in claim 7 wherein said step (d) further comprises of
a. Initializing transition byte with a value 0x00;
b. Setting number of bits starting from least significant bit of transition
byte to T such that, total number of Ts in transition byte are equal
to the value of the remainder of the division carried out in step (a) of
claim 7.
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Test set up with Digital to Analog conversion system and method based on serial communication as claimed in claims 1 to 8.
Digital to Analog conversion system and method of generating analog signal based on serial communication substantially as herein described with reference to accompanying drawings.
Dated this 15th day of October 2007.

13


ABSTRACT
Digital To Analog Conversion System And Method Of Conversion Thereof Based On Serial Communication
Low cost micro-controller based systems suffer from lack of adequate on-chip resources for generating PWM/analog output voltages. Traditionally on-chip "capture and compare blocks " coupled with a dedicated timer can be used to generate PWM voltages, this approach ties up on-chip timer resource and event counting hardware for PWM generation , restricting the system capabilities for timer/counter intensive applications. This invention proposes use of on-chip serial synchronous communication channel for generating analog output. This approach does not restrict system capabilities for timing/event counting tasks. Many low-cost stand-alone systems do not need synchronous communications and hence the associated hardware can be gainfully employed for analog voltage generation.

Documents

Orders

Section Controller Decision Date

Application Documents

# Name Date
1 2050-mum-2007-form 2(title page)-(15-10-2007).pdf 2007-10-15
1 2050-MUM-2007-RELEVANT DOCUMENTS [29-03-2020(online)].pdf 2020-03-29
2 2050-MUM-2007-RELEVANT DOCUMENTS [29-03-2019(online)].pdf 2019-03-29
2 2050-mumnp-2007-form 18(22-11-2007).pdf 2007-11-22
3 2050-mum-2007-form 9(22-11-2007).pdf 2007-11-22
3 2050-mum-2007-abstract.doc 2018-08-09
4 2050-mum-2007-form 8(22-11-2007).pdf 2007-11-22
4 2050-mum-2007-abstract.pdf 2018-08-09
5 2050-mum-2007-correspondence(22-11-2007).pdf 2007-11-22
5 2050-MUM-2007-CLAIMS(AMENDED)-(26-3-2014).pdf 2018-08-09
6 2050-MUM-2007-REPLY TO EXAMINATION REPORT(27-12-2011).pdf 2011-12-27
7 2050-MUM-2007-GENERAL POWER OF ATTORNEY(27-12-2011).pdf 2011-12-27
7 2050-mum-2007-claims.pdf 2018-08-09
8 2050-mum-2007-correspondence-received.pdf 2018-08-09
8 2050-MUM-2007-CLAIMS(MARKED COPY)-(27-12-2011).pdf 2011-12-27
9 2050-MUM-2007-CLAIMS(AMENDED)-(27-12-2011).pdf 2011-12-27
9 2050-mum-2007-description (complete).pdf 2018-08-09
10 2050-MUM-2007-DRAWING(26-3-2014).pdf 2018-08-09
10 2050-MUM-2007-Written submissions and relevant documents (MANDATORY) [13-03-2018(online)].pdf 2018-03-13
11 2050-mum-2007-drawings.pdf 2018-08-09
11 2050-MUM-2007-PatentCertificate17-03-2018.pdf 2018-03-17
12 2050-MUM-2007-FORM 13(26-3-2014).pdf 2018-08-09
12 2050-MUM-2007-IntimationOfGrant17-03-2018.pdf 2018-03-17
13 2050-mum-2007-form-1.pdf 2018-08-09
13 abstract1.jpg 2018-08-09
14 2050-MUM-2007_EXAMREPORT.pdf 2018-08-09
15 2050-mum-2007-form-2.pdf 2018-08-09
15 2050-MUM-2007-SPECIFICATION(AMENDED)-(26-3-2014).pdf 2018-08-09
16 2050-mum-2007-form-26.pdf 2018-08-09
16 2050-MUM-2007-REPLY TO HEARING(26-3-2014).pdf 2018-08-09
17 2050-MUM-2007-MARKED COPY(26-3-2014).pdf 2018-08-09
17 2050-mum-2007-form-3.pdf 2018-08-09
18 2050-mum-2007-form-3.pdf 2018-08-09
18 2050-MUM-2007-MARKED COPY(26-3-2014).pdf 2018-08-09
19 2050-mum-2007-form-26.pdf 2018-08-09
19 2050-MUM-2007-REPLY TO HEARING(26-3-2014).pdf 2018-08-09
20 2050-mum-2007-form-2.pdf 2018-08-09
20 2050-MUM-2007-SPECIFICATION(AMENDED)-(26-3-2014).pdf 2018-08-09
21 2050-MUM-2007_EXAMREPORT.pdf 2018-08-09
22 2050-mum-2007-form-1.pdf 2018-08-09
22 abstract1.jpg 2018-08-09
23 2050-MUM-2007-FORM 13(26-3-2014).pdf 2018-08-09
23 2050-MUM-2007-IntimationOfGrant17-03-2018.pdf 2018-03-17
24 2050-MUM-2007-PatentCertificate17-03-2018.pdf 2018-03-17
24 2050-mum-2007-drawings.pdf 2018-08-09
25 2050-MUM-2007-DRAWING(26-3-2014).pdf 2018-08-09
25 2050-MUM-2007-Written submissions and relevant documents (MANDATORY) [13-03-2018(online)].pdf 2018-03-13
26 2050-MUM-2007-CLAIMS(AMENDED)-(27-12-2011).pdf 2011-12-27
26 2050-mum-2007-description (complete).pdf 2018-08-09
27 2050-MUM-2007-CLAIMS(MARKED COPY)-(27-12-2011).pdf 2011-12-27
27 2050-mum-2007-correspondence-received.pdf 2018-08-09
28 2050-mum-2007-claims.pdf 2018-08-09
28 2050-MUM-2007-GENERAL POWER OF ATTORNEY(27-12-2011).pdf 2011-12-27
29 2050-MUM-2007-REPLY TO EXAMINATION REPORT(27-12-2011).pdf 2011-12-27
30 2050-MUM-2007-CLAIMS(AMENDED)-(26-3-2014).pdf 2018-08-09
30 2050-mum-2007-correspondence(22-11-2007).pdf 2007-11-22
31 2050-mum-2007-form 8(22-11-2007).pdf 2007-11-22
31 2050-mum-2007-abstract.pdf 2018-08-09
32 2050-mum-2007-form 9(22-11-2007).pdf 2007-11-22
33 2050-mumnp-2007-form 18(22-11-2007).pdf 2007-11-22
33 2050-MUM-2007-RELEVANT DOCUMENTS [29-03-2019(online)].pdf 2019-03-29
34 2050-MUM-2007-RELEVANT DOCUMENTS [29-03-2020(online)].pdf 2020-03-29
34 2050-mum-2007-form 2(title page)-(15-10-2007).pdf 2007-10-15

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