Claims:1. An apparatus comprising:
a package assembly comprising a plurality of chiplets (3602) and a plurality of interconnect structures, the plurality of chiplets (3602) including:
a first chiplet comprising a first base chiplet (3604; 2910) coupled to a bridge interconnect (2917; 3606) and an interconnect structure (2903), the first base chiplet (3604; 2910) including:
an interconnect fabric (2915), and
a first plurality of level 3 cache banks (2809A-2809N) to cache data read from and transmitted to a memory;
a second chiplet comprising a second base chiplet (3608), the second chiplet coupled to the first chiplet over the bridge interconnect; and
a third chiplet including a second plurality of level 3 cache banks, the third chiplet stacked on the first base chiplet (3604; 2910) in a 3D arrangement and coupled to the first base chiplet over the interconnect structure.
, Description:FIELD
[0003] Embodiments relate generally to the design and manufacturing of general-purpose graphics and parallel processing units.

BACKGROUND OF THE DESCRIPTION
[0004] Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors used fixed function computational units to process graphics data; however, more recently, portions of graphics processors have been made programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.
[0005] To further increase performance, graphics processors typically implement processing techniques such as pipelining that attempt to process, in parallel, as much graphics data as possible throughout the different parts of the graphics pipeline. Parallel graphics processors with single instruction, multiple thread (SIMT) architectures are designed to maximize the amount of parallel processing in the graphics pipeline. In an SIMT architecture, groups of parallel threads attempt to execute program instructions synchronously together as often as possible to increase processing efficiency. A general overview of software and hardware for SIMT architectures can be found in Shane Cook, CUDA Programming Chapter 3, pages 37-51 (2013).

BRIEF DESCRIPTION OF THE DRAWINGS
[0006] So that the manner in which the above recited features of the present embodiments can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings, and in which:
[0007] FIG. 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;
[0008] FIG. 2A-2D illustrate parallel processor components, according to an embodiment;
[0009] FIG. 3A-3C are block diagrams of graphics multiprocessors and multiprocessor-based GPUs, according to embodiments;
[0010] FIG. 4A-4F illustrate an exemplary architecture in which a plurality of GPUs is communicatively coupled to a plurality of multi-core processors;
[0011] FIG. 5 illustrates a graphics processing pipeline, according to an embodiment;
[0012] FIG. 6 illustrates a machine learning software stack, according to an embodiment;
[0013] FIG. 7 illustrates a general-purpose graphics processing unit, according to an embodiment;
[0014] FIG. 8 illustrates a multi-GPU computing system, according to an embodiment;
[0015] FIG. 9A-9B illustrate layers of exemplary deep neural networks;
[0016] FIG. 10 illustrates an exemplary recurrent neural network;
[0017] FIG. 11 illustrates training and deployment of a deep neural network;
[0018] FIG. 12 is a block diagram illustrating distributed learning;
[0019] FIG. 13 illustrates an exemplary inferencing system on a chip (SOC) suitable for performing inferencing using a trained model;
[0020] FIG. 14 is a block diagram of a processing system, according to an embodiment;
[0021] FIG. 15 is a block diagram of a processor according to an embodiment;
[0022] FIG. 16 is a block diagram of a graphics processor, according to an embodiment;
[0023] FIG. 17 is a block diagram of a graphics processing engine of a graphics processor in accordance with some embodiments;
[0024] FIG. 18 is a block diagram of hardware logic of a graphics processor core, according to some embodiments described herein;
[0025] FIG. 19A-19B illustrate thread execution logic including an array of processing elements employed in a graphics processor core according to embodiments described herein;
[0026] FIG. 20 is a block diagram illustrating a graphics processor instruction formats according to some embodiments;
[0027] FIG. 21 is a block diagram of a graphics processor according to another embodiment;
[0028] FIG. 22A-22B illustrate a graphics processor command format and command sequence, according to some embodiments;
[0029] FIG. 23 illustrates exemplary graphics software architecture for a data processing system according to some embodiments;
[0030] FIG. 24A is a block diagram illustrating an IP core development system, according to an embodiment;
[0031] FIG. 24B illustrates a cross-section side view of an integrated circuit package assembly, according to some embodiments described herein;
[0032] FIG. 25 is a block diagram illustrating an exemplary system on a chip integrated circuit, according to an embodiment;
[0033] FIG. 26A-26B are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein;
[0034] FIG. 27 shows a parallel compute system, according to an embodiment;
[0035] FIG. 28A-28B illustrate a hybrid logical/physical view of a disaggregated parallel processor, according to embodiments described herein;
[0036] FIG. 30 illustrates a message transportation system for an interconnect fabric, according to an embodiment;
[0037] FIG. 31 illustrates transmission of messages or signals between functional units across multiple physical links of the interconnect fabric;
[0038] FIG. 32 illustrates transmission of messages or signals for multiple functional units across a single physical link of the interconnect fabric;
[0039] FIG. 33 illustrates a method of configuring a fabric connection for a functional unit within a disaggregated parallel processor;
[0040] FIG. 34 illustrates a method of relaying messages and/or signals across an interconnect fabric within a disaggregated parallel processor;
[0041] FIG. 35 illustrates a method of power gating chiplets on a per-workload basis;
[0042] FIG. 36 illustrates a parallel processor assembly including interchangeable chiplets;
[0043] FIG. 37 illustrates an interchangeable chiplet system, according to an embodiment;
[0044] FIG. 38 is an illustration of multiple traffic classes carried over virtual channels, according to an embodiment;
[0045] FIG. 39 illustrates a method of agnostic data transmitting between slots for interchangeable chiplets, according to an embodiment;
[0046] FIG. 40 illustrates a modular architecture for interchangeable chiplets, according to an embodiment;
[0047] FIG. 41 illustrates the use of a standardized chassis interface for use in enabling chiplet testing, validation and integration;
[0048] FIG. 42 Illustrates the use of individually binned chiplets to create a variety of product tiers; and
[0049] FIG. 43 illustrates a method of enabling different product tiers based on chiplet configuration.

DETAILED DESCRIPTION
[0050] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to host/processor cores to accelerate graphics operations, machine-learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor/cores over a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the cores and communicatively coupled to the cores over an internal processor bus/interconnect (i.e., internal to the package or chip). Regardless of the manner in which the GPU is connected, the processor cores may allocate work to the GPU in the form of sequences of commands/instructions contained in a work descriptor. The GPU then uses dedicated circuitry/logic for efficiently processing these commands/instructions.