FIELD OF INVENTION
The present invention relates to reliable, accurate and fast counting of discrete pulses coming
to the circuitry. The circuitry utilizes a minimum space of 70mm X 70mm on a multilayer printed
circuit board (PCB). For pulse counting a general purpose data processing device is interfaced
with a programmable logic device through anintegrated circuit of buffer.
BACKGROUND OF THE INVENTION
The electronic components used in the invention had been gone through severe working
environment and had been tested satisfactorily for its working in airborne applications also.
Mechanism comprises of the good signal integrity and excellent signal conditioning to handle
the sensor generated discrete pulse. The invention is adoptable for commercial as well as
industrial applications also.
SUMMARY OF PRESENT INVENTION
In accordance with one aspect of present invention is to provide fast and reliable discrete pulse
counting mechanism with general purpose data processing device and programmable logic
device.
In accordance with second aspect of present invention is to provide an easy signal conditioning
and accurate counting of discrete pulses coming to the circuit in various rates.
In accordance with another aspect present invention is to provide highly reliable circuitry using
minimum space on multilayer printed circuit board.
Annexure‐II
In accordance with yet another aspect present invention is to providediscrete pulse counts in
parallel data format to the data acquisition and processing device.
Advantage of the present invention is that it is based on very accurate signal acquisition along
with reliable signal conditioning and counting mechanism for its use in various general purpose
applications.
BRIEF DESCRIPTION OF DRAWING
Figure 1 is an event flow schematic of the activities carried out by the interface.
Figure 2is a descriptive block diagram of discrete pulse conditioning and conversion to the
digital domain.
Figure 3 is a descriptive block diagram of digital pulse acquisition and accumulation interface.
DETAILED DESCRIPTION
Introduction:
Discrete pulse signals of varying magnitude and varying pulse width are become a natural
choice for various event counting devices and discrete sensing elements in the field of
electronics. On the other hand, voltage tolerance and acceptance range of digital data
processing and acquisition devices are shrinking with advent of silicon technology. Thus, the
proposed mechanism bridges the gap by interfacing signals of discrete pulse kind, with different
magnitudes and different pulse widths with state of the art accurate data processing and
acquisition hardware elements. (refer fig 1)
Discrete pulse conditioning and conversion:
The input discrete pulse has fed through a noise remover electronic circuit to remove un
intended noise components from the original signal. It has to be further converted into the
lower voltage levels as per the input magnitude and conversion circuit requirements. The down
Annexure‐II
converted input signal then goes through a TTL output generator circuit and a digitally
compliant TTL pulse output will be generated.(Refer fig 2)
Digital pulse acquisition and count accumulation:
The digital pulse interfaces with any programmable logic device, which accepts the TTL output
pulse. The logic device can be configured with the acquisition parameters like minimum
threshold pulse width to be detected and maximum limit (if any) for the incoming pulse. All the
valid instance of pulses are counted and accumulated inside the programmable logic device.
The cumulative or immediate accumulated count value, as per the configuration is readily
available for the data acquisition and processing devices for further processing and
applications. (Refer fig 3)

WE CLAIMS:-
Accordingly, the description of the present invention is to be considered as illustrative only and is for the purpose of teaching those skilled in the art of the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and exclusive use of all modifications which are within the scope of the appended claims is reserved.

We Claim that:

1. The discrete pulse accumulation mechanism comprises, i) A noise removing circuit ii) A voltage down conversion circuit iii) A digital TTL output generator circuit iv) A programmable logic device v) Configuration information for the programmable logic device

2. The system as in the claim1, capable of receiving and acquiring discrete signal of any magnitude up to 28V DC

3. The system as in claim1, capable of receiving and acquiring discrete signal of any pulse width with frequency as high as 25MHz

4. The system as in claim 1, capable of interfacing with any data processing device or equipment with memory access capability.

5. The system as in claim 1, capable of accumulating the cumulative pulse count value up to the numeric value of 4294967295. ,TagSPECI:As per Annexure-II