Field of the Invention:
The present invention relates to design of two dimensional matrix memory and particularly relates to a method and a system for storing and processing the data using low cost Dynamic Random Access Memory (hereinafter referred to as DRAM) which improves the system processing capability.
Background of the Invention:
To process two dimensional signals (video, graphics etc), there is a need for two dimensional memory access. This processing is easy if the memory is Static Random Access Memory (hereinafter referred to as SRAM), as it may not require refresh and different control signals to mange the memory access. SRAM is convenient to handle because of direct addressing of data but it not available in large sizes and dissipates lot of heat. Also cost of the SRAM is high compared to other memory especially for high speed access.
DRAM memory is available at low cost, large size and high speed. Due to the internal architecture of the DRAM, it requires sequence of operation to be performed to write/ read the data from the memory, namely precharge, activate, read, write, refresh. To process two dimensional signals (video, graphics etc), there is a need for two dimensional memory access.
All two dimensional signal algorithms are processed in a matrix manner, which is convenient to handle in SRAM memory because of the direct addressing of data. As DRAMs are not amenable to such direct addressing, it becomes very difficult to use DRAMs in cases where complex algorithms requiring complex data access patterns are to be implemented.
As an example, the DRAM (512K x 32 x 4 banks) is implemented as 4 parallel banks with a synchronous interface. Each of the banks is organized into a number of rows and columns with each memory location being 32-bits wide'. Read and write accesses to the DRAM can be both single word read/write or burst oriented read/write. In case of Burst access, the access starts at a selected location and continues for a programmed number of locations without any intermediate precharge, activate or refresh cycles.
Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BAO and BA1 select the bank, A0-A10 select the row). The address bits (A0-A7) registered coincident with the READ or WRITE command is used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized.
To obtain a high data transfer rate, the DRAM needs to be addressed in a burst mode. The burst length is in generally a power of 2 (e.g., 2, 4, 8, 16, etc.). As the data rate during burst mode is very high, generally the data is stored in an intermediate buffer before being processed. Normally a FIFO with handshaking is used for this purpose. However, in our suggested scheme, we propose to do away with the FIFO in video path without interrupting the data flow at the digital video clocking rate.
In the conventional method, a FIFO is used between the DRAM controller and the DRAM. Handshaking signals between FIFO and the controller ensure the continuous data flow from this memory. However, it must be noted that all DRAM controllers implement linear memory access, which is not suitable for two-dimensional signals. Therefore, the spatial relation of the data arrangement is lost and data rearrangement is required during the processing stage leading to considerable overheads.
For video processing, if the memory access is faster, then more time is available to perform signal processing functions. In US patent 6489964 the DRAM's Row and column address have to be activated at different time instants. Therefore, to convert a continuous input data stream into a frame buffer data stream the samples of two successive data bursts of N samples are situated N+AN samples apart from each other, and/or for converting such a frame buffer data stream into a continuous output data stream there is a need for FIFO.
SRAM is normally not used for storing large volumes of high-speed data because the cost of high speed and large size SRAMs is prohibitive. In addition, the power consumption of such devices will also be substantially higher. This will cause heat dissipation and is therefore not suitable for use in confined spaces. For such applications, high speed DRAM is normally used.
Due to the architecture of DRAMs, they require a sequence of commands to access one location. As a result they are not easily amenable for use in applications which require two dimensional signal processing methods.
In the present invention, the external system connected to the DRAM accesses a location by supplying only the Row Address and the Column Address. The external system does not have to generate the other signals like refresh, precharge, row strobe, column strobe. Therefore, the interface to the memory occurs in the native matrix mode which is very user friendly and is very amenable to two-dimensional signal processing. The invention utilizes the inherent parallelism available in the DRAM architecture and the time available during the blanking period to perform this function.
Object of the invention:
The processing of two dimensional signals requires two dimensional memory access for reading/writing in order simplify the subsequent signal processing functions. A huge amount of data is required to be processed to handle full-motion video leading to the requirement of matrix
based storage and retrieval systems with Signal Standard Specification. DRAM is the best option for low cost, huge storage and high speed. However, the internal memory cells organization in a DRAM is very different from the two-dimensional signal standard. As a result, accessing data from DRAMs (which requires a sequence of operations) is inconvenient from the processing point of view.
In the conventional method, a FIFO is used between the DRAM controller and the DRAM. Handshaking signals between FIFO and the controller ensure the continuous data flow from this memory. However, it must be noted that all DRAM controllers implement linear memory access, which is not suitable for two-dimensional signals. Therefore, the spatial relation of the data arrangement is lost and data rearrangement is required during the processing stage leading to considerable overheads.
Mega pixel imaging sensors and different digital standards are emerging on a regular basis to meet the changing market requirements of high speed coupled with low bandwidth. Editing, clipping, merging, displaying multiple video windows in single screen from different inputs with different standards will become very cumbersome to mange using existing low cost DRAMs.
The principal object of this invention is to provide a method and a system for large sized, two-dimensional digital signal storage and access using low cost DRAMs. This method will generate two-dimensional addresses in terms of row and column (video, graphics signal) in row-major form. The extra logic elements provided by the said method provides matrix based access without adding the overheads required by the traditional DRAM read/write operations. The invention therefore can be called a low cost two-dimensional matrix memory or virtual two-dimensional SRAM. In addition, the present invention also provides a system for processing of two-dimensional signals.
Another object of the present invention is to use a single clock domain. Since the invention does not make use of a FIFO in the data path, it reduces numbers of logic elements used thereby allowing implementation in low cost FPGAs. The present method will also allow selection of display memory allocated for multiple sources automatically depending on the address.
Yet another object of the present invention is to provide a two-dimensional memory access method that can be effectively used for DRAMs (both Single and Double Data Rate type).
Yet another object of the present invention is to provide a two-dimensional memory, which is accessible over a single address bus. The Row and Column addresses are multiplexed on this bus and there is an active start signal which indicates the validity of the addresses. The display coordinates of the signal (row and column) are correlated with the data arrangement inside the memory to allow easy signal processing capability for two-dimensional signals.
Yet another object of the present invention is to provide a data structure which may be easily used for video processing algorithms like deinterlacing, frame rate conversion which are processed the row by row, by comparing with the previous frame/field data. In addition, algorithms which process localized pixels and normally use line buffers, may also be easily used by reading the data from two-dimensional memory (row by row).
STATEMENT OF INVENTION:
Accordingly, the invention provides a method for accessing a DRAM as an addressable two-dimensional memory using a two-dimensional address (row and column), an active start signal and a read/write control signal. The invention comprises the following sequence of functions:
a) generates a two-dimensional address stream, an active start signal and the read/write control signal with a SSAGM, which receives a two-dimensional digital signal;
b) links the two dimensional addresses with the active start signal, the read/write control signal and the digital data to the two dimensional memory;
c) sends a precharge command to the DRAM memory, while the active start signal becomes low;
d) keeps a state machine (SM) waiting to meet a Trcd period of time;
e) sets a bank decoder address zero by keeping the two-dimensional address applied on the address line as a row address;
f) issues an activation command and waiting to meet the Trcd time;
g) repeat the steps (c) - (e) for all the banks by incrementing the said bank decoder address and following the commands from said state machine;
h) keep the bank decoder address as zero, column addresses as zero and issue write/read
command while the active start signal becomes high and waiting to meet CAS latency time; i) start the data counter after the CAS latency time has been elapsed; j) check that the said data counter value has reached the Bank cell depth minus CAS latency
clock count; k) increment the said bank decoder address by one, keeping column address zero and issue the
read/write command for said bank decoder address when said data counter value equals the
value obtained in step (j); 1) check the data counter value for locating the Bank cells depth; m) allow a data burst from previous bank to current decoded bank by switching banks from
previous bank to current bank when the data counter reaches exactly same value as said data
counter in (1) and follow the commands from said state machine; n) repeat the above steps (j) to (m) for the other banks up to the depth of all the Banks by
following the commands from said state machine; o) identify read operation or write operation based on whether read/write control signal becomes
low or high; p) store the digital data based on the active start, in DRAM memory, read / write control signal as
two dimensional memory for multiple frames of digital data.
The present invention also provides a system for processing a two-dimensional signal, which can be stored in DRAM used as an addressable two dimensional memory, comprising of:
a) an analog to digital conversion module capable of converting two-dimensional signals into a two-dimensional digital signals;
b) a memory controller which controls the sequence of operation involved in storing and retrieving the digital data from DRAM;
c) a digital processing module which reads the digital data for processing and sending the digital data outside the system in specified manner by applying several image processing algorithms, providing the two dimensional digital signal to a SSAGM which will convert the two
dimensional digital signal into a row address, a column address, a active start signal and a read/write control signal;
d) a module for accelerating and buffering the digital data by using a synchronized dual port double line buffer;
e) a switcher which switches the DRAM memory between a read controller and a write controller to make continuous data flow from input to output;
f) two sets of DRAM memory in the system such that each set total bank count equals to two dimensional memory column size divide by each bank's cell depth size;
g) a module for connecting a state machine (read controller/ write controller) to DRAM;
h) a mode of switching the DRAM between read controller and write controller independent of
one another; i) a signal generated by the write controller state machine which follows a state flow to store the
digital data; j) a generator of two dimensional addresses as per the functional requirement of the system to
provide row address, column address and active start signal to read controller; k) a generator of signal by the read controller state machine which follows the state flow to
retrieve the digital data; 1) a module for storing and retrieving the digital data in DRAM memory, which act as two
dimensional memory for multiple frames of digital data.
Brief descriptions of the Drawings:
Fig. 1 illustrating the standard SDRAM architecture used in the Two dimensional memory. Fig. 2 illustrates the Conventional way of implementing the DRAM Memory Controller.
Fig. 3 illustrating System architecture using DRAM as addressable two dimensional memory
Fig. 4 illustrates the standard signal address generation module (SSAGM).
Fig 5. Illustrating architecture of the two dimensional memory.
Fig.6. illustrates logical implementation of two dimensional memory port handling.
Fig.7 illustrate the logical implementation of Synchronized dual port double line buffer
Fig.8 illustrating the State machine (or read/write controller) implementation of two dimensional memory interface.
Fig 9 illustrating the state flow diagram of two dimensional memory.
Detailed descriptions of the invention with reference to the drawings:
In the following description, the object of this invention is described in accordance with accompanying drawings. This invention is capable of providing two-dimensional memory at low cost.
The architecture and description of the new two dimensional memory using DRAM, is described in figures Fig 3, Fig 4, Fig 5and Fig 6. The Fig 7, Fig 8, Fig 9 gives the logic implementation, state flow and state machine implementation of the memory.
Synchronous DRAM (SDRAM) is illustrated as an example to explain the two dimensional memory. Similarly Video signal is taken as an example for two dimensional signals. SDRAM has four banks in parallel and able to support the required the signal resolution. For more than 1024 x 1024 size two or more DRAM are used in parallel with address and data buses.
Fig 1 illustrates the internal architecture of the SDRAM memory. It has an array of four Banks in parallel and each bank is independently decoded by bank row address latch and decoder. This decoder logic is coupled with row address multiplexer for activating the row address in the bank arrangement. Similarly column decoders are connected in parallel to all four banks and each such decoder is connected with columns address decoder latch. However, both the row and column addresses sharing the common address bus. Consequently, the rows and columns have to be activated at different time instants as per the required sequence of commands.
The DRAM is initialized in the following steps:
a) Applying Power and feeding clock to SDRAM;
b) NOP condition is applied at the inputs during this condition;
c) Maintaining stable power, stable clock, and a NOP condition applied for a minimum of 200us;
d) Issuing pre charge commands for all banks of the device;
e) Issuing 8 or more auto-refresh commands;
f) Issuing a mode register set command to initialize the mode register.
After this initialization sequence, the SDRAM have to follow the following sequence to read or write a data in the memory.
Burst Read/Write Sequence of SDRAM can be activated using a bank active command. The bank active command is initiated by activating CS, RAS and deactivating CAS, WE with row and bank address at the same clock rising edge. Once a row active command has been issued to the bank selected by the bank address, the selected bank leaves its idle state and goes into its row activating state. Accordingly, the row address is latched and the appropriate row in the Bank selected. Data from that row of memory is sensed and latched by the bank's sense amplifiers, to be used for later read or write operations. Burst read or writes command can be issued on the activated row after the minimum time delay between active and read/write command (tRCD time). A bank can be activated even when the opposite bank is active. Minimum time delay to activate one bank to
another bank ( tRRD time) is required to active another bank. A row active command cannot be given to a bank if that bank is already active. Also, a row active command cannot be given to either bank if the SDRAM is currently in the power down, self refresh, auto refresh or clock suspend states.
Read command is used to access burst read of data in activated row. The read command is initiated by activating CS, CAS and asserting high on WE with column address at the same clock rising edge. The first data is available after CAS (Column address strobe) latency time of clock cycles. The length of the burst and the CAS latency will be determined by mode register set values. The burst read can be terminated by another command - burst stop, burst read or burst write command to the same bank or the other active bank or a pre charge command to the same bank. At the end of burst length, the data outputs will go to high impedance and the bank will re-enter the row active state.
Write command is used to write data into SDRAM. The write command is initiated by activating CS, CAS and WE with column address at the same clock rising edge. The first data can be input with write command and column address in same clock cycle regardless of what value of CAS latency is programmed into the mode register. The length of the burst will be determined by the values programmed during the LMS (Load Mode set) command.
Fig 2 illustrate DRAM controller providing sequence of commands to access a particular location to write. This method are not correlating the two dimensional special relationship of the signal. New method of addressing scheme uses the Parallel architecture of DRAM, Video standard related control signal to make the memory access more compact and easy for further processing.
Fig 3 illustrates a two-dimensional signal processing system comprising two dimensional memory and switcher (3b) which will switch the memory between the incoming and outgoing path. The two dimensional digital signal (3a) is coupled with Video standard signal address generation module (SSAGM) to generate the row address and column address for the two dimensional memory. The digital video coming from the ADC (analog to digital conversion) /decoder is first buffered into a synchronized (7a) dual port double line buffer (7b) for stable operation. Then this data is read into the DRAM using the on DRAM clock. Switching of the memory is controlled by input Vsync. Multiple memory can be arranged in parallel to enable editing of multiple signal sources.
In Fig 4, the video signal (example for two-dimensional Digital Video data) (3a) shown may be obtained from the Analog to digital converter (ADC) or from the video decoder. In the case of ADC, field detection is obtained from the video digital data. In the case of High End video Decoder, field out is available as a digital output. By counting the vsync, hysync, pixel clock and odd/even field indicator output, the row and column addresses can be offset in the area of signal interest at the stage of generation by generating a discrete signal namely active start signal. The active start signal is generated by synchronizing the generated column addresses and the useful area of the two- dimensional address space. A high active start signal indicates digital data (useful area) send to two dimensional memory along with two dimensional address have to be stored in the DRAM, while a low active start signal means digital data (unwanted area) will not be
considered for storage and uses the time period for activating rows and column of DRAM banks. A frame count of the Video digital Data is maintained to generate proper address offset for each frame. This is done so that, depending on the requirement, related rows of different frames can be arranged in close proximity for easy processing irrespective of the frame to which it belongs.
Fig 4 also gives an overview of the two dimensional address generation which will decide whether the Video digital data is interlaced or Progressive. In case of interlaced video for Odd field starting Address offset will be an Odd number and for even Field will be an Even number. Afterward for every line in the Video, row address is incremented depending upon the frame depth image processing algorithms. The related pixel can be arranged together independent of Field and Frame for easy implementation of signal processing algorithms.
For designing a DRAM as addressable two dimensional memory , two dimensional addresses are generated by the SSAGM in following steps: Identifying the useful area in the two dimensional signal space for row and column address generation ;Generating row addresses by differentiating useful area and unwanted area in terms of number of horizontal sync after vertical sync with the standard signal address generation module; Generating Column addresses by differentiating useful area and unwanted area in terms of number of pixel clock after the horizontal sync with the standard signal address generation module.
Fig 5 is illustrates the architecture of two dimensional memory and its external interface. It has row address and column address along with active start signal. This architecture is valid for a two dimensional memory of resolution less than or equal to 1024 x 1024. When the active start signal is low, the address will be considered as row address and when the video start signal is high (5b), data appearing on the address line will be considered as column address of the two- dimensional memory. Figure 5 also shows the State Machine required to implement the two-dimensional memory. The Initialization state machine is separate from the read/write state machine. Splitting the state machine helped in controlling the timing during multiplexing efficiently. After the initialization is over, the two dimensional memory will control the machine sequence between the active start high (5b) and the active start low (5a). During the OFF period all Rows are closed and address coming from the address lines are considered as Column address.
Fig 6 is shows the logical implementation of Row and column addressing coupled with the active start. By providing this implementation, number of lines required for addressing the two dimensional address space is decreased with out losing the spatial relationship of the signal. Also the active start is the indicating parameter for the memory to identify the length of the row.
Fig. 7 explains the synchronized dual port double line buffer (7b) for speed acceleration in signal path. For some cases, the incoming signal may be lower than the DRAM minimum speed of operation. It can be accelerated by providing double line buffer in the data path (or dual PORT RAM). Double line buffer provides the bridge between the Slow Data and High Speed data Read/Write in DRAM. The data write/read is done at slow rate but it buffered in SDRAM much faster depending on the output requirements.
Interfacing the Slow Clock domain and High Clock Domain in to a common Memory and putting a synchronizer (7a) between the Domains. Dual port RAM memory is used to separate the two clock domain and the MSB bit of the Address range is inverted with respect to one another so that independent Read and write of two clocks will happen without collision in the Address. Windowing function of multiple video is done easily by controlling the Active start signal in the memory interface.
Fig 8 is illustrates the implementation of the state machine (read controller /write controller) comprising the steps as follows:
When the read/write control signal becomes high it will issue read command and follow the state diagram to act as read controller. When write control signal becomes low, it will issue write command and follow the state diagram to act as write controller. The vice versa also hold true.
When active start is OFF, Row activation command is issued for bank one and row address is kept as such but the bank address is incremented. Then activation command is issued. The Bank number is incremented up to the maximum bank depth and depends on row length. Trcd timing is maintained after every activation Command.
State machine (read /write controller) is activating all the banks for the same address ROW by switching the Bank address one after the other to the maximum extent of Bank depth. The whole activity is done during active start - Low period (8a). Depending on the Maximum signal dimension, DRAM organization is selected. DRAM is added in parallel to meet the length of the Row in two dimensional memory in such a way that no of banks multiplied by column depth equals the entire Row size.
Fig 9 explaining the state flow diagram, wherein the said state machine (read controller or write controller) data flow follow state diagram linear and cyclic manner as
Path flow (9a) (Active start -Low) is calculating the next state by considering the previous state. It maintains the time counter for Precharge and activate. In the state Diagram, Fl - is the state where Precharge command is issued and maintains the time counter for Trp (time required for precharing a bank). Then state machine moves to F2 where Bank address increment is done for the given row address. In F3 activating the same ROW for that bank is done by considering the Trcd for each row. After activating the all the ROWs it is put in the ideal state (F4) for up to receiving the Active start command. If the ideal state in more than Tref (time required for refreshing) time period, it will ender in to the F5 where it apply the refresh command then again will wait in the ideal state.
Now in Path flow (9b) State machine is calculating the bank switching event by managing the address pointer. When the Active Start becomes high, State changed from D to Rl. Here Bank Read / Write command is issued in state Rl. After the CAS latency time, it will enter in the R2 state where it starts count the burst data length. Before reaching the end of burst, At (Data count minus CAS latency number of clock), Write /Read command is issued to make another bank to ready for the Data follow. So it moves from R2 to Rl. In Rl state Bank write/Read command is issued when the burst flow in the previous Bank.
Then it Moves to R2 where it take care of Burst Data flow from next bank (i.e.) Bank switching is done to make the Flow continuous.
As the state machine (read controller or write controller) is going to control the signal associated with DRAM memory, data path contains digital data is separated from the state machine; Based on the family of DRAM namely DDR SDRAM or SDRAM digital data rate can be conveniently managed based on system requirements through the said data path separation from the state machine of two dimensional memory.
In another embodiment of the present invention multiple DRAM can be arranged to meet the column depth in such a way that total number of banks in multiple DRAM multiplied by number of bank cells in each bank equals column width of two dimensional memory. A decoder is placed between the Banks of multiple DRAMs to decode each bank one by one and all DRAM shares the common address lines.
Decoding all the banks in an incremental manner while multiple DRAM Banks connected with decoder to make the two dimensional memory much wide in size to handle huge digital data.
Although the invention has been described with reference to specific embodiments, this description is not meant to be construed in limiting sense. Various modifications of the disclosed embodiments, as well as alternate embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that such modifications can be made without departing from the spirit or scope of the present invention as defined.

We Claim
1. A method for designing a DRAM as addressable two dimensional memory using a two dimensional signal standard Address, an active start signal and a read/write control signal comprising the steps of:
a) generating a two dimensional address stream including the active start signal and the read/write control signal with a SSAGM which is receiving a two dimensional digital signal;
b) connecting the two dimensional addresses with the active start signal , the read/write control signal and the digital data to the two dimensional memory;
c) applying a precharge command to the DRAM memory, while the active start signal becomes Low;
d) keeping a state machine (SM) waiting to meet a Trcd period of time ;
e) setting a bank decoder address zero by keeping the two dimensional address applied on the address line as a row address;
f) issuing activation command and waiting to meet the Trcd time;
g) repeating the step (c) - (e) for all the banks by incrementing said bank decoder address and following the commands from said state machine;
h) keeping the bank decoder address as zero, column addresses as zero and issuing
Write/Read command while the active start signal becomes high and waiting to meet CAS latency time;
i) staring the a data counter after the CAS latency time has been elapsed;
j) checking said data counter value to reach the Bank cell depth minus CAS latency clock count;
k) incrementing the said bank decoder address by one ,keeping column address as zero and issuing the read/write command for said bank decoder address when said data counter value equals the value obtained in step (j);
1) checking the data counter value for locating the Bank cells depth;
m) allowing a data burst from previous bank to current decoded bank by switching banks from previous bank to current bank when the data counter reaches exactly same value as said data counter in (1) and following the commands from said state machine;
n) repeating the above steps (j) to (m) for the other banks up to the depth of all the Banks by following the commands from said state machine;
o) identifying read operation or write operation based on whether read/write control signal becomes low or high;
p) Storing the digital data based on the active start, in DRAM memory, read / write control signal as two dimensional memory for multiple frames of digital data.
2. The method for designing a DRAM as addressable two dimensional memory as claimed in
claim 1, wherein, two dimensional addresses are generated by the SSAGM comprising
following steps:
a) Identifying the useful area in the two dimensional signal space for row and column address generation ;
b) Generating row addresses by differentiating useful area and unwanted area in terms of number of horizontal sync after vertical sync with the standard signal address generation module;
c) Generating Column addresses by differentiating useful area and unwanted area in terms of number of pixel clock after the horizontal sync with the standard signal address generation module.
3. The method for designing a DRAM as addressable two dimensional memory as claimed
in claim 1 , wherein, the active start signal is generated by synchronizing the generated column addresses and the useful area of the two dimensional address spaces.
4. A method for designing multiple DRAMs as addressable two dimensional memory using a
two dimensional signal standard address, an active start signal and a read/write control signal
comprising the steps of:
a) arranging multiple DRAMs to meet the column depth in such a way that total no of banks in multiple DRAM multiplied by number of bank cells in each bank equals column width of two dimensional memory;
b) placing a decoder between the banks of multiple DRAMs to decode each bank one by one and allowing all DRAM to share the common address lines;
c) decoding all the banks in an incremental manner as multiple DRAM banks connected with the decoder;
d) repeating the all the steps form (a) to (p) of claim 1 for decoding all the banks one by one for the entire DRAM banks. 5. A system for processing a two dimensional signal which can be stored in DRAM as addressable two dimensional memory, the system comprising:
an analog to digital conversion module capable of converting two dimensional signals into two dimensional digital signals;
a set of DRAM memory for storing and retrieving the digital data;
a memory controller which controls the sequence of operation involved in storing and retrieving the digital data from DRAM;
a digital processing module which reads the digital data for processing and sending the digital data outside the system in specified manner by applying several image processing algorithms; and
providing the two dimensional digital signal to a SSAGM which will convert the two dimensional digital signal into a row address, a column address, an active start signal and a read/write control signal.
accelerating and buffering the digital data by using a synchronized dual port double line buffer.
providing a switcher which switches the DRAM memory between a read controller and a write Controller to make continuous data flow from input to output;
arranging two set of DRAM memory in the system such that each set total bank count equals to two dimensional memory column size divide by each bank's cell depth size;
connecting a state machine (read controller/ write controller) to DRAM;
switching the DRAM between read controller and write controller independent of one another;
generating signal by the write controller (state machine) which follows a state flow to store the digital data;
generating two dimensional addresses as per the functional requirement of the system to provide row address, column address and active start signal to read controller;
generating signal by the read controller (state machine) which follow the state flow to retrieve the digital data;
Storing and retrieving the digital data in DRAM memory, which act as two dimensional memory for multiple frames of digital data.
6. A method for designing a DRAM as addressable two dimensional memory substantially
herein described with reference to the accompanying drawings.
7. A system for processing a two dimensional signal which can be stored in DRAM as
addressable two dimensional memory substantially herein described with reference to the accompanying drawings.