WE CLAIM:
1. A drive circuit for a semiconductor element, comprising:
a controller configured to control open and closed states of the semiconductor element based on a command received from outside;
a gate voltage detector configured to detect a gate voltage of the semiconductor element and generate a voltage detection signal indicating the detected gate voltage;
a gate current detector configured to detect a current flowing into a gate electrode of the semiconductor element;
a signal generation circuit configured to generate, as an output signal, one of a first differential amplification signal of the voltage detection signal and a first delay signal of the voltage detection signal, a second differential amplification signal of the first delay signal and a second delay signal of the voltage detection signal, and a differentiation signal of the voltage detection signal;
a first comparator configured to compare a value of the output signal with a first reference value;
a second comparator configured to compare a current detection value by the gate current detector with a second reference value; and
a short circuit determination unit configured to determine whether or not the semiconductor element is in a short-circuited state, based on a result of comparison by the first comparator and a result of comparison by the second comparator, and generate a determination signal indicating a determination result.
2. The drive circuit for the semiconductor element according to claim 1,
wherein
the signal generation circuit includes:
a first delay circuit configured to receive the voltage detection signal and generate the first delay signal; and
a first differential amplification circuit configured to receive the voltage

detection signal and the first delay signal, and generate the first differential amplification signal.
3. The drive circuit for the semiconductor element according to claim 1,
wherein
the signal generation circuit includes:
a first delay circuit configured to receive the voltage detection signal and output the first delay signal;
a second delay circuit configured to receive the voltage detection signal and output the second delay signal; and
a first differential amplification circuit configured to receive the first delay signal and the second delay signal, and generate the second differential amplification signal.
4. The drive circuit for the semiconductor element according to claim 1,
wherein
the signal generation circuit includes a differentiation circuit configured to receive the voltage detection signal and generate the differentiation signal.
5. The drive circuit for the semiconductor element according to any one of
claims 1 to 4, wherein
the gate current detector includes:
a gate resistor connected between the controller and the gate electrode; and
a second differential amplification circuit configured to amplify a voltage across the gate resistor to thereby generate a third differential amplification signal, and
the current detection value is a value of the third differential amplification signal.
6. The drive circuit for the semiconductor element according to any one of

claims 1 to 4, wherein
the gate current detector includes:
a gate resistor connected between the controller and the gate electrode of the semiconductor element;
a second differential amplification circuit configured to amplify a voltage across the gate resistor to thereby generate a third differential amplification signal; and
a third delay circuit configured to receive the third differential amplification signal and generate a third delay signal that is the delayed third differential amplification signal, and
the current detection value is a value of the third delay signal.
7. The drive circuit for the semiconductor element according to any one of claims 1 to 4, wherein
the gate current detector includes:
a gate resistor connected between the controller and the gate electrode of the semiconductor element;
a fourth delay circuit configured to receive a voltage signal of one end of the gate resistor on the semiconductor element side and generate a fourth delay signal that is the delayed voltage signal of the one end of the gate resistor;
a fifth delay circuit configured to receive a voltage signal of the other end of the gate resistor on the controller side and generate a fifth delay signal that is the delayed voltage signal of the other end of the gate resistor; and
a second differential amplification circuit configured to receive the fourth delay signal and the fifth delay signal, and amplify a difference between the fourth delay signal and the fifth delay signal to thereby generate a third differential amplification signal, and
the current detection value is a value of the third differential amplification signal.

8. The drive circuit for the semiconductor element according to any one of
claims 1 to 7, further comprising
a signal holding unit configured to hold the determination signal when the short circuit determination unit determines that the semiconductor element is in the short-circuited state.
9. The drive circuit for the semiconductor element according to any one of
claims 1 to 8, wherein
the controller is configured to bring the semiconductor element into the open state when the determination signal indicates that the semiconductor element is in the short-circuited state.
10. The drive circuit for the semiconductor element according to any one of
claims 1 to 9, wherein
the first reference value is identical to the second reference value.