Claims:1. A logic device (100) for controlling digital circuits, the logic device comprising:
a driver logic cell comprising a level shifter (102) that receives input signal;
a first stage inverter (104) electrically coupled to the level shifter, the first stage generates a first complement voltage; and
a second stage inverter (106) electrically coupled to the first stage inverter, the second stage inverter generates a second complement voltage,
wherein, the level shifter (102), the first stage inverter (104) and the second stage inverter (106) integrated on a monolithic microwave integrated circuit (MMIC) structure, and
wherein, the first complement voltage and the second complement voltage directly control the bits of digital circuits comprises any or a combination of radio frequency (RF) switches, attenuator, and phase shifters.
2. The driver logic device as calmed in claim 1, wherein the level shifter (102), the first stage inverter (104) and the second stage inverter (106) integrated to realize an 8-bit driver logic MMIC pseudomorphic high electron mobility transistor (pHEMT) using enhancement/depletion (E/D) mode with a die size of 3.3mm x 1.4mm, wherein the fabrication materials are selected from a group comprising indium gallium arsenide (InGaAs) and gallium arsenide (GaAs).
3. The logic device as claimed in claim 1, wherein the driver logic cell operates at supply voltages +5V,-5V, supply current consumption of 1.5mA/bit, and driver switching speed below 20ns.
4. The logic device as claimed in claim 1, wherein a reusable single bit driver logic cell is connected to individual control bit of RF switches.
5. The logic device as claimed in claim 1, wherein the driver logic cell comprises supply bond pads with on chip bypass capacitor and ESD diodes for electrostatic discharge (ESD) protection.
6. The logic device as claimed in claim 1, wherein the drain side current limiting protection comprising of high value epitaxial (epi) resistors and diodes provided to the inverters.
7. The logic device as claimed in claim 1, wherein the first stage inverter (104) is a combination of direct coupled FET logic (DCFL).
8. The logic device as claimed in claim 7, wherein the DCFL comprises depletion-mode field-effect transistor (DFET) and enhancement -mode field-effect transistor (EFET), wherein the DFET with customized gate width connected with the EFET to generate negative output voltage.
9. The logic device as claimed in claim 1, wherein the second stage inverter (106) is a combination of super buffer FET logic (SBFL).
10. The logic device as claimed in claim 9, wherein the SBFL comprises DFET with customized gate width, wherein the gate of a second enhancement mode FET being connected to the gate of a first enhancement mode FET, wherein the customized gate width of 2.4um is configured to reduce current consumption.
, Description:TECHNICAL FIELD
[0001] The present disclosure relates, in general, integrated logic circuits, and more specifically, relates to a means for using customized gate width on enhancement/depletion (E/D) mode Gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) structures to design driver logic circuits.

BACKGROUND
[0002] Recently, logic circuits in Gallium arsenide (GaAs) technology use a field-effect transistor (FET) and diodes in combination with a large resistor. However, these circuits require high supply currents during on-state because of the required voltage drop over the resistor and the FET/diodes consume larger chip area which increases overall size and cost of the circuits.
[0003] Few exemplary existing logic circuits in GaAs technology suffer for the limitations, where the control levels for these switches have traditionally been either 0V/-5 V or 0V/-3.3 V derived from a silicon control application-specific integrated circuit (ASIC). In the depletion mode pHEMT technology used in most monolithic microwave integrated circuit (MMIC) designs, with zero volts gate to source, a switch device is on, and with -5 V on the gate electrode, the device is off.
[0004] Although multiple technological improvements exist within the art of GaAs mixed-signal realization, these improvements suffer from significant drawbacks. However, it is mandatory to have both enhancement-mode and depletion-mode devices available on the same substrate which offers less current consumption and potential for a higher level of integration and includes simple functions such as complimentary generation to the inclusion of inverters and serial to parallel converters, since inverters with only depletion-mode FET consumes huge current consumption
[0005] Therefore, there is a need in the art to provide a low-current driver logic circuit with customised unit gate width DFET which is used in inverter for integrated logic circuits applications in GaAs technology.

OBJECTS OF THE PRESENT DISCLOSURE
[0006] An object of the present disclosure relates, in general, integrated logic circuits, and more specifically, relates to a means for using customized gate width on enhancement/depletion (E/D) mode Gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) structures to design driver logic circuits.
[0007] Another object of the present disclosure is to provide a logic device that enable fast response.
[0008] Another object of the present disclosure is to provide a logic device that lowers power consumption.
[0009] Another object of the present disclosure is to provide a logic device that is compact and has higher efficiency.
[0010] Another object of the present disclosure is to provide a logic device with super buffered FET logic (SBFL) that exhibits better fan-out capability, and better noise margins.
[0011] Another object of the present disclosure is to provide a logic device that exhibits higher level of integration.
[0012] Another object of the present disclosure reduces overall size and cost of the circuits.
[0013] Yet another object of the present disclosure is to driver logic device with depletion-mode FET (DFET) with customized gate width to reduce current.

SUMMARY
[0014] The present disclosure relates, in general, integrated logic circuits, and more specifically, relates to a means for using customized gate width on enhancement/depletion (E/D) mode Gallium arsenide GaAs pseudomorphic high electron mobility transistor (pHEMT) structures to design driver logic circuits.
[0015] The present disclosure describes a fast response, compact and low power consumption driver design. The integrated logic circuit receives transistor-transistor logic (TTL) logic at the input and generates two complementary output. This integrated logic circuit comprises a logic circuits like super buffer logic, level shifters and output inverters stage. Level shifting is done using enhancement FET with a string of diodes, and a resistor used for protection. A complementary logic circuit contains two inverters with a customised gate width of depletion mode field-effect transistor (DFET) to reduce current as low as possible that converts the input signal to a required complementary output voltage which directly controls the bits of attenuators and phase shifters.
[0016] In an aspect, the present disclosure provides a logic device for controlling digital circuits, the logic device includes a driver logic cell comprising a level shifter that receives input signal, a first stage inverter electrically coupled to the level shifter, the first stage generates a first complement voltage, and a second stage inverter electrically coupled to the first stage inverter, the second stage inverter generates a second complement voltage, wherein, the level shifter, the first stage inverter and the second stage inverter integrated on a monolithic microwave integrated circuit (MMIC) structure, and wherein, the first complement voltage and the second complement voltage directly control the bits of digital circuits comprises any or a combination of radio frequency (RF) switches, attenuator, and phase shifters.
[0017] In an embodiment, the level shifter, the first stage inverter and the second stage inverter integrated to realize an 8-bit driver logic MMIC pseudomorphic high electron mobility transistor (pHEMT) using enhancement/depletion (E/D) mode with a die size of 3.3mm x 1.4mm, wherein the fabrication materials are selected from a group comprising indium gallium arsenide (InGaAs) and gallium arsenide (GaAs).
[0018] In another embodiment, the driver logic cell operates at supply voltages of +5V,-5V, supply current consumption of 1.5mA/bit, and driver switching speed below 20ns.
[0019] In another embodiment, a reusable single bit driver logic cell is connected to individual control bit of RF switches.
[0020] In another embodiment, the driver logic cell comprises supply bond pads with on chip bypass capacitor and ESD diodes for electrostatic discharge (ESD) protection.
[0021] In another embodiment, the drain side current limiting protection comprising of high value epitaxial (epi) resistors and diodes provided to the inverters.
[0022] In another embodiment, the first stage inverter may be a combination of direct coupled FET logic (DCFL).
[0023] In another embodiment, the DCFL comprises depletion-mode field-effect transistor (DFET) and enhancement -mode field-effect transistor (EFET), wherein the DFET with customized gate width connected with the EFET to generate negative output voltage.
[0024] In another embodiment, the second stage inverter is a combination of super buffer FET logic (SBFL).
[0025] In another embodiment, the SBFL comprises DFET with customized gate width, wherein the gate of a second enhancement mode FET being connected to the gate of a first enhancement mode FET, wherein the customized gate width of 2.4um is configured to reduce current consumption.
[0026] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The following drawings form part of the present specification and are included to further illustrate aspects of the present disclosure. The disclosure may be better understood by reference to the drawings in combination with the detailed description of the specific embodiments presented herein.
[0028] FIG. 1 illustrates an exemplary architecture of integrated control logic circuit, in accordance with an embodiment of the present disclosure.
[0029] FIG. 2 is an exemplary schematic view of a direct-coupled FET logic (DCFL) logic used in first stage inverter, in accordance with an embodiment of the present disclosure.
[0030] FIG. 3 illustrates an exemplary schematic view of a super buffered FET logic (SBFL) logic used in second stage inverter, in accordance with an embodiment of the present disclosure.
[0031] FIG. 4 illustrates an exemplary layout of a single bit control logic, in accordance with an embodiment of the present disclosure
[0032] FIG. 5 illustrates an exemplary layout of 8-bit integrated control logic, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0033] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0034] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0035] The present disclosure relates, in general, integrated logic circuits, and more specifically, relates to a means for using customized gate width on enhancement/depletion (E/D) mode Gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) structures to design driver logic circuits.
[0036] The present disclosure describes a fast response, compact and low power consumption driver design. The integrated logic circuit receives transistor-transistor logic (TTL) logic at the input and generates two complementary output. This integrated logic circuit comprises a logic circuits like super buffer logic, level shifters and output inverters stage. Level shifting is done using enhancement FET with a string of diodes, and a resistor used for protection. A complementary logic circuit contains two inverters with a customised gate width of depletion mode field-effect transistor (DFET) to reduce current as low as possible that converts the input signal to a required complementary output voltage which directly controls the bits of attenuators and phase shifters. The present disclosure can be described in enabling detail in the following examples, which may represent more than one embodiment of the present disclosure.
[0037] FIG. 1 illustrates an exemplary architecture of integrated control logic circuit, in accordance with an embodiment of the present disclosure.
[0038] Referring to FIG. 1, integrated logic circuit 100 (also referred to as a logic device 100, herein) may be configured with customised unit gate width depletion-mode field-effect transistor (DFET), which may be used in inverter for integrated logic circuits applications in Gallium arsenide (GaAs) technology. The integrated control logic design may include driver logic cell that includes a level shifter 102, a first stage inverter 104 and a second stage inverter 106. The circuit according to embodiments of the present disclosure may be realized in GaAs technology and may not require large currents. The low-current circuit delivers the desired voltages while always limiting its currents to a minimum.
[0039] In an exemplary embodiment, the logic circuit 100 as presented in the example may be fabricated on 0.25um GaAs enhancement/depletion (E/D) process using custom-designed FET structures to achieve low current less than 1.5mA per individual bit and size 300 X 300 um per bit. The present disclosure relates to 8-bit low current control logic design with a die size of 3.3 X 1.4 mm fabricated on using PD25 0.25um E/D process, where the process results in a reduction in current consumption by using E/D mode FETs and offers ease of integration.
[0040] In an embodiment, the integrated control logic design may include three-stage topology that may include level shifter 102, the first stage inverter 104 and the second stage inverter 106. The level shifter 102, direct coupled FET logic (DCFL) and super buffer FET logic (SBFL) in output stage accepts transistor-transistor logic (TTL)/complementary metal oxide semiconductor (CMOS) input levels and provide negative output voltage to switch GaAs pHEMTs.
[0041] The level shifter 102 may receive the control input signal. The first stage inverter 104 electrically coupled to the level shifter 102, the first stage inverter 104 may generate first complement voltage and drive the gate of the second stage inverter 106. The second stage inverter 106 electrically coupled to the first stage inverter 104, the second stage inverter 106 generate second complement voltage, where both the first complementary output voltage and the second complementary output voltage directly control the bits of attenuator and phase shifters.
[0042] The level shifter 102, the first stage inverter 104 and the second stage inverter 106 integrated to realize an 8-bit driver logic monolithic microwave integrated circuit (MMIC) on 0.25um indium gallium arsenide (InGaAs) pseudomorphic high electron mobility transistor (pHEMT) using enhancement/depletion (E/D) mode with a die size of 3.3mm (X) x 1.4mm (Y) respectively. The fabrication materials may be selected from InGaAs and GaAs.
[0043] In another exemplary embodiment, the GaAs driver logic cell having the following features: low current consumption by using gate width reduction of D-mode FET, driver switching speed less than 20ns, two inverters which generate complementary output voltages to drive bits of digital circuits, operating supply voltages of +5V,-5V and supply current consumption of 1.5mA/bit, reusable single bit driver logic cell which can be connected to individual control bit of RF switches, and supply bond pads with on-chip bypass capacitor for ESD protection. Nonstandard D-mode FET with a gate width of 2.4um to reduce current consumption of the driver logic cells. Drain side current limiting protection comprising of high value epitaxial (epi) resistors and diodes provided to the inverters used in driver logic cells.
[0044] In another embodiment, the level shifter 102 may accept the control input in the range of 0V