Claims:WE CLAIM:
1. A dual action current limit operation apparatus [100] for pulse-width modulation (PWM) converters [100], comprising of:
a digital PWM controller [1];
a dual action current limit controller [2];
two gate drivers [3 and 4]; and
a PWM based half bridge power converter [6] with a current sensing circuit [5],
wherein the digital PWM controller [1] generates pre-conditioned gate driver signals Gate_1_Pre [1a] and Gate_2_Pre [1b] as outputs, said outputs [1a and 1b] enters the dual action current limit controller[2],
wherein the gate drivers [3 and 4] are buffer circuit which increases current sourcing capability of Gate_1 [2a] and Gate_2 [2b] signals coming out of the dual action current limit controller [2],
wherein the gate drive signals Gate_1 [2a] and Gate_2 [2b] are buffered by the gate drivers [3 and 4] and are used to drive the PWM based half bridge power converter [6] by driving semiconductor devices (Q1 and Q2),
wherein the dual action current limit controller [2]enables current limit operation and optimizes power loss by reducing loss in reverse conduction of the semiconductor devices (Q1 and Q2) by turning ON a main device channel and thereby enables the apparatus to withstand current limit operation for longer duration, said main device channel is a semiconductor device,
wherein the apparatus enables low power loss during current limit operation by allowing inductor freewheeling current to flow through the main device channel, and
wherein when the main device channel starts conducting during reverse conduction mode of operation for the semiconductor devices(Q1 and Q2), the voltage drop reduces significantly and thus power loss also reduces in the same proportion.

2. The apparatus [100] as claimed in claim 1, wherein the semiconductor devices (Q1 and Q2) include MOSFET and wide band gap devices, said wide band gap devices include silicon carbide (SiC) and gallium nitride (GaN).

3. The apparatus [100] as claimed in claim 1, wherein during normal operation, when current through the PWM based half bridge power converter [6] is within normal limit,
the gate drive signals generated by the digital PWM controller [1] passes by the dual action current limit controller [2] via the gate drivers [3 and 4],
the digital PWM controller [1] provides a fixed or modulated duty cycle with fixed switching period Tsw to the semiconductor devices (Q1 and Q2),
wherein when the semiconductor device Q1 is turned ON, the current in inductor ramps up and when the semiconductor device Q1 is turned OFF and the semiconductor device Q2 is turned ON with an appropriate dead time, current in the inductor ramps down.

4. The apparatus [100] as claimed in claim 1, wherein during overcurrent, the inductor current increases to a pre-set value,
the current sensor [5] detects the increase in current to said pre-set value and provides data to the dual action current limit controller [2],
the dual action current limit controller [2] conditions the gate drive signals to limit the current and reduce the power loss by controlling the semiconductor devices (Q1 and Q2).

5. A method for reducing power loss during current limit operation, comprising steps of:
Detecting increase in inductor current when semiconductor device Q1 turns ON during short circuit;
Limiting the inductor current to a pre-set value, I_Set by terminating the pulse coming from digital PWM controller [1] by dual action current limit controller [2]; and
performing turning ON semiconductor device Q2, with a fixed dead time for current to freewheel through the semiconductor device Q2by the dual action current limit controller [2],
wherein since the semiconductor device Q2 is turned ON, the current flows through device main channel and reverse conduction would not result in substantial power loss, and
wherein the operation repeats if again the inductor current threshold crosses pre-set value I_Set.

6. The method as claimed in claim 5, wherein in the dual action current limit controller [2] current sense [CS] is compared with a fixed reference (Vref) in a comparator, wherein when the current sense [CS] crosses the pre-set threshold of current value, I_Set, output of the comparator (OC) goes low and said output of the comparator (OC) is processed through logic gates, and
wherein when the inductor current and current sense [CS] falls below a pre-set threshold of current value, I_Reset, the output of the comparator (OC) goes high and is processed through logic gates by letting the PWM controller [1] to drive the semiconductor devices Q1 and Q2.

7. The method as claimed in claim 6, wherein the power loss during the reverse conduction of the semiconductor device Q2 is reduced by turning ON the main channel which offers Rds(on) of 22 mohms and thus device drop is reduced to 1.32V for a period of 200 microseconds. , Description:DUAL ACTION CURRENT LIMIT OPERATION APPARATUS AND A METHOD THEREOF FOR PWM CONVERTERS

FIELD OF INVENTION
The present invention generally relates to the field of power converters with high switching frequency operation, particularly to reduce semiconductor size and volume in power converters. More particularly, the present invention relates to apparatus and method for reducing power loss during current limit operation in PWM converters.

BACKGROUND OF INVENTION
In general, a power converter process and control the flow of electric energy by supplying voltages and currents in a form that is optimally suited for the user loads. Most of the power converters have been developed on silicon (Si) power devices. Even if Si semiconductors present a good balance between performances and cost, the Si based systems have reached their limits in terms of power density, operation temperature, and the switching frequency. Recently evolved WBG device performance is better than the Si counterpart. The improvement is attributed to high saturation velocity of WBG devices resulting in improved high switching frequency operation frequency while reducing power losses. In these terms, silicon carbide (SiC) and gallium nitride (GaN) are the most promising materials because of their beneficial properties.

Prolonged short circuit and high surge power requirements are unavoidable operating conditions for the power converters. For example, on board charger (in electric vehicle) operation for voltage sag which results in higher current for short period, stand-by inverters or inverters in online UPS need to supply surge current of 3.5 times of its full rated current to start the certain loads which requires higher surge power during start-up. In addition to this requirement, the short circuit withstanding capability for at least 200ms to 300ms time period is part of most the power converter specification for almost all the applications, to improve the system reliability and reliable short circuit detection. The semiconductor losses during the prolonged surge load or short circuit duration will govern the semiconductor size and thus the system volume.

US6970339 discloses an embedded over current protection circuit within the PWM feedback controller of a power converter having an novel current limit detection function that minimizes the effects of the turn-on period of the power device. The document describes a buck converter for steady state and current limit modes of operation using PMOS, NMOS and diode. During current limit operation, NMOS is used to sense the current and find out the next instance of resuming normal operation. However, the power converter of the cited document requires additional NMOS device for current sense and it does not describe any aspect of loss reduction during current limit operation. The additional NMOS requires additional space, thus cannot address the problem of the power density. Further, the document is specific to buck converter only and not suitable for other modern power converters like Totem pole converter.

US5317499 discloses direct-current converter that has an electronic switch which can be made conductive by switch-on pulses and has current limiting by suppression of switch-on pulses. The converter uses a capacitor to quickly charge and hold the equivalent current information. When the capacitor voltage crosses a set threshold, the converter pulses are stopped and the capacitor voltage is made to discharge slowly using an additional disconnect MOSFET. Thus, switching is paused for several switching cycles. The converter requires additional MOSFET to realize current sense. The method can be used for relatively lower powers where shunt resistors easily serve the purpose of current sensing. The method performs only the current limiting action in the converter. However, the document does not describe any aspect of high losses and high thermal stress in secondary/freewheeling diodes during current limit operation, which is bound to occur at high power, surge loads and short circuit operating conditions.

US20090072805 discloses switching regulator switches according to an input signal and performs PWM control with a PWM pulse signal that can adjust its internal reference current according to measurement of output current so that variations of pulse widths of a pulse signal can be reduced to reduce the decrease in efficiency with light load and variations in output voltage ripple. Methods like, turn OFF of synchronous rectifier when current flow starts from drain to source are implemented to improve converter performance at light loads. However, the methods do not describe protection of the converter during surge loads or short circuit conditions.

CN101911457 discloses power regulator system and its control method with the current limit independent of duty cycle. However, the document does not provide any solution for loss reduction during current limit operation. The method is suitable for low power converters but at high power and high frequency operation, such current limiting methods will result in severe power loss and high thermal stress on semiconductor device.

Most of the solutions available do not focus on power loss reduction during the operation of current limit. The higher power loss dissipation in semiconductor with existing methods is unavoidable and thus semiconductor devices need to be sized to dissipate this short-term high power loss. The short-term higher power loss may not be important from heat sink sizing point of view but this result in larger semiconductor volume, considering the dynamic thermal impedances of the semiconductor devices. Thus, it increases the size and cost of the semiconductor along with the associated heat sink area and thus in turn size and cost of the overall system.

The higher power loss during the current limit operation is mainly result of OFF state reverse conduction (source to drain) of semiconductor devices. For some wide band gap devices like GaN, the reverse conduction voltage drop and thus power losses are much higher compared to Silicon devices, where intrinsic body diode with lower forward voltage drop comes in action during reverse conduction. It is also a fact that wide band gap device adoption is more popular in applications where power density is imperative, thus reducing power semiconductor size and volume can significantly benefit such systems.

The existing methods describes about limiting the current to a desired value during current limit operation and tripping the system there after, to prevent the system to be in high power loss state for a prolonged period. However, the existing methods do not make any attempt to reduce the power loss, due to reveres conduction of semiconductor devices during current limit operation. And the existing methods results in over sizing of the semiconductor device to withstand the current limit operation.

Further the solutions available are part of PWM controller itself and not suitable to be used in conjunction with digital control method.

The need of higher power density and higher efficiency is important for application like electric vehicles, solar, aviation and other application where space constraints are high. In most of the power converters design, these surge current rating during short circuit or overloads governs the semiconductor size and volume and not the steady state operation.
Further, digital control system suffers with limited bandwidth and hence it is difficult for such systems to reliably operate with a fast rise of current and take appropriate protective actions.

Accordingly, there exists a need for dual action current limit operation apparatus for PWM converters. Also, there exist a need for apparatus and method for reducing the semiconductor size and volume in power converters which supplies large surge currents and withstands prolonged short circuits.

OBJECTS OF INVENTION
One or more of the problems of the conventional prior art may be overcome by various embodiments of the present invention.

It is the primary object of the present invention to provide a dual action current limit operation apparatus for PWM converters.

It is another object of the present invention to provide an apparatus for reducing power loss during current limit operation and during reverse conduction of semiconductor devices.

It is another object of the present invention to provide an apparatus to limit the current to desired value.

It is another object of the present invention to provide an apparatus for reducing the semiconductor size and volume in power converters which supplies large surge currents and withstand prolonged short circuits.

It is another object of the present invention, wherein the apparatus is configured for devices which has got higher off state reverse conduction (source to drain) voltage drop and thus power loss.

It is another object of the present invention, wherein the apparatus is configured to perform dual action namely it limits the current and reduces the reverse conduction losses of the semiconductor devices by turning ON a main device channel.

It is another object of the present invention, wherein the apparatus achieves the dual action seamlessly even with systems which are controlled digitally and makes the digital control more viable.

It is another object of the present invention, wherein the apparatus is configured to be adopted for PWM based power converters which has half bridge leg.

It is another object of the present invention to provide a method for reducing power loss during current limit operation.

It is another object of the present invention, wherein the method enables improvement in power density as a result in reduction of the losses in semiconductor during current limit operation.

It is another object of the present invention, wherein the method works in conjunction with digital control system seamlessly and ensures reliable current limit operation even with very fast increase in current rate without consuming digital controller bandwidth.

SUMMARY OF INVENTION
Thus the basic aspect of the present invention is to provide a dual action current limit operation apparatus for pulse-width modulation (PWM) converters, comprising of:
a digital PWM controller;
a dual action current limit controller;
two gate drivers; and
a PWM based half bridge power converter with a current sensing circuit,
wherein the PWM controller generates pre-conditioned gate driver signals Gate_1_Pre and Gate_2_Pre as outputs, said outputs enters the dual action current limit controller,
wherein the gate drivers are buffer circuit which increases current sourcing capability of Gate_1 and Gate_2 signals coming out of the dual action current limit controller,
wherein the gate drive signals Gate_1 and Gate_2 are buffered by the gate drivers and are used to drive the PWM based half bridge power converter by driving semiconductor devices (Q1 and Q2),
wherein the dual action current limit controller enables current limit operation and optimizes power loss by reducing loss during reverse conduction of the semiconductor devices (Q1 and Q2) by turning ON a main device channel over-ruling the digital PWM controller command and thereby enables the apparatus to withstand current limit operation for longer duration, said main device channel is a semiconductor device,
wherein the apparatus enables low power loss during current limit operation by allowing inductor freewheeling current to flow through the main device channel, and
wherein when the main device channel starts conducting during reverse conduction mode of operation for the semiconductor device(Q2), the voltage drop reduces significantly and thus power loss also reduces in the same proportion.

It is another aspect of the present invention, wherein the semiconductor devices (Q1 and Q2) include MOSFET and wide band gap devices, said wide band gap devices include silicon carbide (SiC) and gallium nitride (GaN).

It is another aspect of the present invention, wherein during normal operation, when current through the PWM based half bridge power converter is within normal limit,
the gate drive signals generated by the digital PWM controller passes by the dual action current limit controller via the gate drivers,
the digital PWM controller provides a fixed or modulated duty cycle with fixed switching period Tsw to the semiconductor devices (Q1 and Q2),
wherein when the semiconductor device Q1 is turned ON, the current in inductor ramps up and when the semiconductor device Q1 is turned OFF and the semiconductor device Q2 is turned ON with an appropriate dead time, current in the inductor ramps down.

It is another aspect of the present invention, wherein during overcurrent, the inductor current increases to a pre-set value,
the current sensor detects the increase in current to said pre-set value and provides data to the dual action current limit controller,
the dual action current limit controller conditions the gate drive signals to limit the current and reduce the power loss by controlling the semiconductor devices (Q1 and Q2).

Another aspect of the present invention is directed to a method for reducing power loss during current limit operation, comprising steps of:
detecting increase in inductor current when semiconductor device Q1 turns ON during short circuit;
limiting the inductor current to a pre-set value, I_Set by terminating the pulse coming from digital PWM controller by dual action current limit controller; and
performing turning ON semiconductor device Q2, with a fixed dead time for current to freewheel through the semiconductor device Q2by the dual action current limit controller,
wherein since the semiconductor device Q2 is turned ON, the current flows through device main channel and reverse conduction would not result in substantial power loss, and
wherein the operation repeats if the inductor current threshold crosses pre-set value I_Set.

It is another aspect of the present invention, wherein in the dual action current limit controller, current sense [CS] is compared with a fixed reference (Vref) in a comparator, wherein when the current sense [CS] crosses the pre-set threshold of current value, I_Set, output of the comparator (OC) goes low and said output of the comparator (OC) is processed through logic gates, and
wherein when the inductor current and current sense [CS] falls below a pre-set threshold of current value, I_Reset, the output of the comparator (OC) goes high and is processed through logic gates by letting the digital PWM controller to resume control and drive the semiconductor devices Q1 and Q2.

It is another aspect of the present invention, wherein the power loss during the reverse conduction of the semiconductor device Q2 is reduced by turning ON the main channel which offers Rds (on) of 22 mohms and thus device drop is reduced to 1.32Vfor a period of 200 microseconds.
BRIEF DESCRIPTION OF DRAWINGS
Figure 1: illustrates apparatus according to present invention.
Figure 2: illustrates dual action current limiting operation in buck converter according to present invention.
Figure 3: illustrates operation of the apparatus according to present invention.
Figure 4: illustrates experimental results with buck converter output short circuit according to present invention.

DETAILED DESCRIPTION OF THE INVENTION WITH REFERENCE TO THE ACCOMPANYING FIGURES
The present invention as herein described relates to a dual action current limit operation apparatus for reducing power loss during current limit operation and to reduce loss during reverse conduction of the semiconductor devices. The present invention further relates to apparatus and method for reducing the semiconductor size and volume in power converters which supplies large surge currents and withstands prolonged short circuits.

Referring to Figures 1 and 2, the dual action current limit operation apparatus [100] for pulse-width modulation (PWM) converters, comprising of a PWM controller [1]; a dual action current limit controller [2]; two gate drivers [3 and 4]; and a PWM based half bridge power converter [6]. The PWM controller [1] is responsible for closed loop or open loop operation in the PWM based half bridge power converters [6] and for steady state operation of the apparatus. Said PWM controller [1] could be realized either by Analog control, Digital control (micro-controller) or by other similar method. The digital PWM controller [1] generates output namely as pre-conditioned gate driver signals Gate_1_Pre [1a] and Gate_2_Pre [1b]. In an aspect, the digital PWM controller [1] generates plurality of outputs. Said pre-conditioned gate driver signals Gate_1_Pre [1a] and Gate_2_Pre [1b] from the digital PWM controller [1] enter the dual action current limit controller [2] which enables current limit operation and optimizes power loss by reducing loss during reverse conduction of semiconductor devices (Q1 and Q2) by turning ON a main device channel over-ruling the digital PWM controller command and thereby enables the apparatus [100] to withstand current limit operation for longer duration, said main device channel is a semiconductor device. The gate drivers [3 and 4] are buffer circuit which increases the current sourcing capability of signals Gate_1 [2a] and Gate_2 [2b] coming out of the dual action current limit controller [2]. The gate drivers [3 and 4] could be realized either by discrete components like totem pole transistor configuration or by using standard gate driver ICs. The gate drive signals Gate_1 [2a] and Gate_2 [2b] which are generated by the dual action current limit controller [2] and buffered by the gate drivers [3 and 4] are used to drive the PWM based half bridge power converter [6] by driving the semiconductor devices (Q1 and Q2). The semiconductor devices (Q1 and Q2) include but not limited to MOSFET, Wide band gap devices like GaN or SiC. The PWM based half bridge power converter [6] includes a current sensing circuit [5], which could be realized using Hall Effect current sensor, current transformers, shunts or other current sensing methods.

Normal operation:
During normal operation, when current through the PWM based half bridge power converter [6] is within normal limits, the gate drive signals or pulses generated by digital PWM controller [1] passes by the dual action current limit controller [2] without any conditioning, via the gate drivers [3 and 4]. Referring to Figure 3, during normal operation, the digital PWM controller [1] provides a fixed or modulated duty cycle with fixed switching period Tsw to Buck converter (Q1 and Q2). During this steady state operation, when switch Q1 is turned ON, the current in inductor ramps up and when Q1 is turned OFF and Q2 is turned ON with an appropriate dead time, current in the inductor ramps down.
Current limit operation:
In the event of the over current due to short circuit, voltage sag, the current increases to a pre-set value, and the current sensor [5] detects the increase in current to a pre-set value and provides data/information to the dual action current limit controller [2]. The dual action current limit controller [2] conditions the gate drive signals or pulses to limit the current and reduce the power loss through or by controlling the semiconductor devices (Q1 and Q2).

Referring to Figure 3, during abnormal operation like short circuit, when the semiconductor device Q1 turns ON, the inductor current increases rapidly. The dual action current limit controller [2] limits the current to below a pre-set value, I_Set by terminating the pulse coming from the digital PWM controller [1]. The dual action current limit controller [2] also turns ON the semiconductor device Q2, with a fixed dead time for current to freewheel or fall down through Q2. Now, since the semiconductor device Q2 is turned ON by the dual action current limit controller [2], the current flows through device main channel and reverse conduction will not have substantial power loss. Conventional current limit circuits/methods just terminate the pulse Q1 from PWM controller but do not turn ON Q2 and thus Q2 device conducts in reverse direction with device main channel being OFF and thus it results in substantial power loss. The power loss without present invention is significantly higher than with present invention. When current reaches a pre-set value I_Reset, again the dual action current limit controller [2] releases the pulses coming from the digital PWM controller [1]. In case if again inductor current threshold crosses pre-set value I_Set same sequence of operation repeats.

Referring to Figure 2, the steps involved in achieving the above functionality are as follows:
In the dual action current limit controller [2], the current sense [CS] is compared with a fixed reference (Vref) in a comparator. When the current sense [CS] crosses the pre-set threshold of current value, I_Set, output of the comparator (OC) goes low and said output of the comparator (OC) is processed through logic gates (AND and OR).

Following Boolean equation governs the logic gate circuit.
Gate_1 = OC & Gate_1-Pre
Gate_2 = OC & Gate_2_Pre || OCCOMP (COMP = complementary)

When the inductor current and thus current sense [CS] falls below a pre-set threshold I_Reset, the output of the comparator (OC) is again pulled high and (is processed through logic gates) the Boolean equation lets the PWM controller [1] to drive the semiconductor devices Q1 and Q2. Table 1 shows the truth table for the Boolean equation.
Table 1:
OC Gate_1-Pre Gate_2-Pre Gate_1 Gate_2
1 1 0 1 0
1 0 1 0 1
0 1 0 0 1
0 0 1 0 1

Figure 4 illustrates experimental results with buck converter output short circuit. During output short circuit when the dual action current limit controller [2] is functional, it keeps the semiconductor device Q1 OFF and Q2 ON while current is freewheeling through it and thus reduces loss in Q2 during reverse conduction mode. In one aspect, the semiconductor devices Q1 and Q2 are GaN devices. Without the apparatus of the present invention the power loss during freewheeling period when current flows in reverse direction the power loss is with 60A current and high reverse conduction drop which is larger in WBG devices (in range of 4V to 8V). The loss is pulsating with a period of 200 microseconds. With the proposed invention the power loss during the reverse conduction of Q2 is reduced by turning ON the main channel which offers Rds (on) of 22 mohms equivalent to 1.32V drop for a period of 200 microseconds. Thus the apparatus enables extremely low power loss during current limit operation by allowing the inductor freewheeling current to flow through main device channel. The experimental result demonstrates the power loss is reduced by ~6 times by the apparatus of the present invention and no semiconductor failure occurs in an event of short circuit. Without the apparatus of present invention, the device fails when output is shorted.

The reduction is power loss during current limit operation directly impacts the semiconductor sizing. According to present invention, the device failure could be prevented by paralleling of semiconductor devices which adds to system size. The power loss during the current limit is short term but reparative and thus the sizing is governed by the dynamic thermal impedance. Thus, the present invention reduces the semiconductor size resulting in lower product cost. The power density is also affected significantly by semiconductor devices, directly by volume of additional device (to distribute the thermal stress during short circuit) and indirectly by its heat sinking requirement and thus the size of heat sink required to accommodate it. The reduction in semiconductor size thus also improves the power density.

Although the present invention has focused mainly on buck converter, the invention is not limited to any particular application. The present invention could also be used for any converter with half bridge leg. For example, it could be used for Totem pole converter (Bridgeless PFC and Inverter), interleaved dc-dc converters, Inverters which includes Full Bridge and NPC inverter topologies known to those skilled in the art. The topologies mentioned here are only for example. Any other topology which has half bridge leg could be covered under this invention.

Advantages of the apparatus and method of the present invention are as follows:
• Is very generic for adoption and could be used for power converters with half bridge leg.
• Is more imperative for devices which has got higher OFF state reverse conduction (source to drain) voltage drop and thus the power loss.
• Works in conjunction with digital control seamlessly and ensure reliable current limit operation even with very fast current rise.
• The reduction is power loss during current limit operation directly impacts the semiconductor sizing.
• Reduction in semiconductor size results in lower product cost.
• Enables improvement in power density due to reduction in semiconductor size and associated component count and heatsink area.
• Augments digital control and works with it reliably without interfering with it and makes the digital control more viable.
• Easy to implement and can be adopted without any special components.