Claims:1. An electronic package, comprising:
a first package substrate;
a second package substrate attached to the first package substrate;
a die attached to the second package substrate; and
a plurality of photonics engines attached to a first surface and a second surface of the first package substrate, wherein the plurality of photonics engines are communicatively coupled to the die through the first package substrate and the second package substrate.
, Description:TECHNICAL FIELD
[0002] Embodiments of the present disclosure relate to electronic packaging, and more particularly to optics packaging for high bandwidth networking applications.

BACKGROUND
[0003] As data center traffic continues to scale, it is generally accepted that next generation networks will need tight integration of networking integrated circuits (ICs) (e.g., Ethernet switch silicon dies) and high bandwidth density photonic engines. Currently, the high bandwidth density optics are packaged on the same surface of an interposer that the IC is packaged. Since the area around the perimeter of the IC is limited, future scaling by adding additional photonic engines is limited. Some architectures have proposed implementing additional photonic engines on the system board in order to increase bandwidth. However, such architectures are limited, because the distance between the IC and the photonic engine is increased. As such, there are power penalties due to losses along the interconnect between the IC and the photonic engine.

BRIEF DESCRIPTION OF THE DRAWINGS
[0004] Figure 1A is a cross-sectional illustration of an electronic package that comprises a switch die and a plurality of photonic engines connected to two surfaces of an interposer, in accordance with an embodiment.
[0005] Figure 1B is a cross-sectional illustration of an electronic package that comprises a switch die, a plurality of photonic engines, and thermal and mechanical components used to cool and secure the electronic package.
[0006] Figure 2A is a plan view illustration of a top surface of an electronic package that comprises eight photonic engines around a perimeter of the switch die, in accordance with an embodiment.
[0007] Figure 2B is a plan view illustration of a bottom surface of an electronic package that comprises eight photonic engines, in accordance with an embodiment.
[0008] Figure 2C is a plan view illustration of a top surface of an electronic package that comprises four photonic engines around a perimeter of the switch die, in accordance with an embodiment.
[0009] Figure 2D is a plan view illustration of a top surface of an electronic package that comprises six photonic engines around a perimeter of the switch die, in accordance with an embodiment.
[0010] Figure 3 is a perspective view illustration of an electronic package that depicts the positioning of photonic engines above and below the interposer, in accordance with an embodiment.
[0011] Figure 4A is a cross-sectional illustration of an electronic system that comprises a switching package with photonic engines on two sides of the interposer with the interposer attached to the board by a socket, in accordance with an embodiment.
[0012] Figure 4B is a cross-sectional illustration of the electronic system of Figure 4A along line B-B’, in accordance with an embodiment.
[0013] Figure 5A is a plan view illustrations of the bottom surface of the interposer that shows the layout of sockets and the bottom surface photonic engines, in accordance with an embodiment.
[0014] Figure 5B is a plan view illustration of the bottom surface of the interposer that shows the layout of sockets and the bottom surface photonic engines, where the sockets are connected as a monolithic structure, in accordance with an embodiment.
[0015] Figure 5C is a cross-sectional illustration of the interposer in Figure 5B along line 5-5’, in accordance with an embodiment.
[0016] Figure 5D is a cross-sectional illustration of the interposer in Figure 5B along line 5-5’, in accordance with an additional embodiment.
[0017] Figure 6 is an exploded view of an electronic system with photonic engines on two surfaces of the interposer, in accordance with an embodiment.
[0018] Figure 7 is a schematic of a computing device built in accordance with an embodiment.

EMBODIMENTS OF THE PRESENT DISCLOSURE
[0019] Described herein are network switching packages for high bandwidth networking applications, in accordance with various embodiments. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
[0020] Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.