WO 2005/056675 PCT/US2004/017749 Dual-Stage Wafer Applied Underfills Field Of The Invention [001] The invention is directed to, microelectronic chip assemblies and in particular, methods and materials for applying an underfill to integrated circuit wafers. Background of the Invention [002] Surface mounting of electronic components is well developed in automated package assembly systems. Integrated circuits are made up of devices such as transistors and diodes and elements such as resistors and capacitors linked together by conductive connections to form one or more functional circuits. The devices are built on wafers, or sheets of silicon with a surface that is subject to a series of fabrication steps to form a pattern of identical integrated circuits separated from each other by a repeating rectangular pattern of scribe lines or saw streets in the surface of the wafer that serve as boundaries between the dice, chip or die., At a late stage in a fabrication process the singulated dice from the wafer is bonded to a (Substrate to form an IC package. [003] Conventional flip chip technology generally refers to any assembly where the active side of the integrated circuit die is attached toa package substrate or printed circuit board (collectively referred to as a PCB) Flip chip assemblies can