The invention relates in general to a serial peripheral interface and a data transmitting method thereof, and more particularly to a serial peripheral interface having a better overall behavior and a data transmitting method thereof.

Background
Serial Peripheral Interface (SPI) is a synchronous serial communication interface specification used for short-distance communication, primarily in embedded systems. SPI devices communicate in full duplex mode using a master-slave architecture with a single master. The master device originates the frame for reading and writing. Multiple slave-devices are supported through selection with individual slave select (SS), sometimes called chip select (CS), lines.
FIG. 1 refers a block diagram showing a conventional data transmission system. The data transmission system 100 includes an integrated circuit 110 and a serial peripheral interface 120. The serial peripheral interface 120 has many pins, for example, including an input pin 122, an output pin 124, a chip select pin 126 and a clock pin 128. The input pin 122 receives a piece of serial data, including instructions and addresses, and transmits the piece of serial data to the integrated circuit 110. The output pin 124 reads a piece of serial data, including dummy cycles and multiple read out data, from the integrated circuit 110 and outputs the piece of serial data. The chip select pin 126 provides a chip select signal CS, and the clock pin 128 provides a clock signal SCLK.

Fig. 2 illustrates conventional SPI-mechanism in another representation. As it is known, the Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between microcontrollers and small peripherals such as shift register. To achieve this communication, one node is defined as a Master and another as a Slave. Only Master device can initiate data transfer. If both nodes are active and want to play a role of Master, then a plurality of SPI interfaces are utilized as shown in Fig. 2.

Accordingly, for a particular SPI interface, one of the two SPI nodes has to be permanently designated as a master and other as a slave to initiate data-transfer, thereby imparting a constraint to the system. Moreover, both the SPI interfaces have to act in parallel to contribute towards data transfer and thereby pose additional constraint.

To put it differently, the conventional systems mandate two SPI interfaces between two nodes, thereby always posing a requirement of plurality of SPI interfaces and cause inefficient use of SPI channel

Summary of the invention
This summary is provided to introduce a selection of concepts in a simplified format that are further described in the detailed description of the present disclosure. This summary is not intended to identify key or essential inventive concepts of the claimed subject matter, nor is it intended for determining the scope of the claimed subject matter.

The present subject matter refers a serial to parallel interface (SPI) communication system between two nodes. The system comprises at least one SPI interface, and a plurality of input/output I/O terminals connected through the SPI interface. A processor is configured for maintaining a recipient status and a transmitter status of the I/O terminals. A transfer of data is allowed from a first I/O terminal as a master to a second I/O terminal based on checking a current recipient-status of the first terminal as LOW. The transmitter-status of the first I/O terminal is set as HIGH based on said allowance. Data from the first I/O terminal is transferred to the second I/O terminal. The transmitter-status of the first I/O terminal is reset as LOW based on completion of said transfer.

This present subject matter refers a mechanism to handle SPI communication between two nodes and executed at both ends. To achieve efficient dynamic-role based SPI communication between the nodes, the present subject matter requires a single SPI interface and 2 GPIOs (general-purpose input/output) terminals. GPIO are used for dynamic role configuration and it’s indication to another node.

The mechanism involves a Library that by default initializes both nodes as a slave (ready to receive). Both GPIOs are pulled down by default. Accordingly, the two SPI nodes play a role of Master interchangeably with respect to a single SPI interface and initiate bidirectional data transfer. The same efficiently use SPI protocol constructs and optimizes SPI interface usage. The other SPI interface can be used for some other important functionality ex. Flash access etc.

To further clarify advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof, which is illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. The invention will be described and explained with additional specificity and detail with the accompanying drawings.
Brief description of the drawings
These and other features, aspects, and advantages of the present invention will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:

Fig. 1 illustrates a conventional data transmission system;
Fig. 2 illustrates another representation of the state of the art SPI (Serial Peripheral Interface) mechanism;
Fig. 3 illustrates a dynamic role based data transfer over SPI between two nodes, in accordance with an embodiment of the present subject matter;
Fig. 4 illustrates method steps according to an embodiment of the present subject matter;
Fig. 5 illustrates the SPI (Serial Peripheral Interface) mechanism according to an embodiment of the present subject matter; and
Fig. 6 illustrates an implementation of the present subject matter in a computing system, according to an embodiment of the present subject matter.

Further, skilled artisans will appreciate that elements in the drawings are illustrated for simplicity and may not have been necessarily been drawn to scale. For example, the flow charts illustrate the method in terms of the most prominent steps involved to help to improve understanding of aspects of the present invention. Furthermore, in terms of the construction of the device, one or more components of the device may have been represented in the drawings by conventional symbols, and the drawings may show only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the drawings with details that will be readily apparent to those of ordinary skill in the art having benefit of the description herein.

Detailed Description
For the purposes of promoting understanding of the principles of the invention, reference will now be made to the embodiment illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended, such alterations and further modifications in the illustrated system, and such further applications of the principles of the invention as illustrated therein being contemplated as would normally occur to one skilled in the art to which the invention relates.

It will be understood by those skilled in the art that the foregoing general description and the following detailed description are explanatory of the invention and are not intended to be restrictive thereof.

Reference throughout this specification to “an aspect”, “another aspect” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrase “in an embodiment”, “in another embodiment” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

The terms "comprises", "comprising", or any other variations thereof, are intended to cover a nonexclusive inclusion, such that a process or method that comprises a list of steps does not include only those steps but may include other steps not expressly listed or inherent to such process or method. Similarly, one or more devices or subsystems or elements or structures or components proceeded by "comprises... a" does not, without more constraints, preclude the existence of other devices or other sub-systems or other elements or other structures or other components or additional devices or additional sub-systems or additional elements or additional structures or additional components.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The system, methods, and examples provided herein are illustrative only and not intended to be limiting.

Figure. 3 illustrates a dynamic role based data transfer over SPI between two nodes, in accordance with an embodiment of the present subject matter;

The present subject matter refers a serial to parallel interface (SPI) communication system (300) between two nodes (302, 304). The system comprises at-least one SPI interface (306) and a plurality of input/output I/O terminals (302, 304) connected through the SPI interface (306). The I/O terminals correspond to GPIOs (input/output) terminals.

Further, a processor (602) or microcontroller is provided for :
a) maintaining a recipient status and a transmitter status of the I/O terminals;
b) allowing transfer of data from a first I/O terminal (302) as a master to a second I/O terminal (304) based on checking a current recipient-status of the first terminal (304) as LOW;
c) setting the transmitter-status of the first I/O terminal (302) as HIGH based on said allowance;
d) transferring data from the first I/O terminal (302) to the second I/O terminal (304); and
e) resetting the transmitter-status of the first I/O terminal (302) as LOW based on completion of said transfer.

The maintaining of the recipient status and the transmitter status comprises initializing by a library the plurality of I/O terminals as slave while setting of the recipient status of the plurality of I/O terminals as LOW. Setting the transmitter-status of the first I/O terminal (302) as HIGH further comprises setting the recipient status of the second I/O terminal (304) as HIGH.

The processor (602) is further configured for rejecting a request for transfer of data from the first I/O terminal (302) as the master to the second I/O terminal (304) based on checking the current recipient-status of the first terminal as HIGH. Moreover, the allowing of the transfer of data from the first I/O terminal (302) as the master to the second I/O terminal (304) is further based on a priority associated with first I/O terminal (302).

Based on completion of transfer of data from the first I/O terminal (302) to the second I/O terminal, the transmitter-status of the first I/O terminal (302) is reset as LOW: In addition, upon said transfer, the recipient-status of the second I/O terminal (304) is reset as LOW based on completion of said transfer.

In an embodiment, the present subject matter refers a mechanism to handle SPI communication between two nodes (302, 304) and executed at both ends. To achieve efficient dynamic role based SPI communication between the nodes (302, 304), the present subject matter requires the single SPI interface (306) and 2 GPIOs (general-purpose input/output) terminals 302, 304. GPIOs are used for dynamic role configuration and indication to another node

In operation, a Library by default initializes both nodes 302, 304 as a slave (ready to receive). Both GPIOs are pulled down. If Node A (or the node 302) has data to be transferred to Node B (i.e. node 304), then Node A first checks, if Rx control GPIO is set to High by node Node B. If yes, then it has to wait till node B transfers its data completely.

However, if Rx control is Low, then Node A asserts it’s Tx control GPIO to high. Node A configures itself as SPI Master and initiates data transfer. Once data transfer is complete, Node A reconfigures itself as a Slave.

Thereafter, Node A relinquishes the Tx Control pin to low, once transfer is complete. Similar course of action is adopted by Node B, if it has to transfer data to Node A (302). As the same SPI interface (306) involves Node A and Node B interchangeably and/or intermittently assuming roles of transmission and receiving, there lies a substantial probability of collision of asserting a Tx Control pin for Node A (302) and Node B (304) at same instant of time. The same in turn poses a probability of causing malfunction. To address this, a prior assignment of node-priroity may be done.

In an implementation, for addressing the constraint posed by collision, either of the node (302, 304) is configured at HIGH priority and another node at LOW priority as a part of one time executed initialization. Accordingly, every time during collision, a node with priority set as HIGH will operate as a Master and will transfer the data. In other words, at every occurance of such situation, a designated node having HIGH priority will proceed with Transmission. For example, Node A may be initialized at priority HIGH and Node B initialized with priority LOW. If at given time instant, both nodes attempt to assert respective Tx Control pin and a collision is all set to occur, then Node A will be prioritized to assert Tx Control pin over Node B and Node B will receive data as a Slave.

Further, the other vacant SPI interface (if any) may be used for another purpose, say flash access.

Figure. 4 illustrates method steps according to an embodiment of the present subject matter;. The steps 402 corresponds to connecting a plurality of input/output I/O terminals (302, 304) through an SPI interface 406. The steps 404 to 412 correspond to executing steps a) to e) as depicted in Fig. 3, respectively.

Figure. 5 illustrates the SPI (Serial Peripheral Interface) mechanism according to an embodiment of the present subject matter.

Figure 6 shows an example implementation in accordance with the embodiment of the invention, and yet another typical hardware configuration in preceding figures in the form of a computer-system and architecture 600. The computer system 600 can include a set of instructions that can be executed to cause the computer system 600 to perform any one or more of the methods disclosed. The computer system 600 may operate as a standalone-device or may be connected, e.g., using a network, to other computer systems or peripheral devices.

In a networked deployment, the computer system 600 may operate in the capacity of a server or as a client user computer in a server-client user network environment, or as a peer computer system in a peer-to-peer (or distributed) network environment. The computer system 600 can also be implemented as or incorporated across various devices, such as a personal computer (PC), a tablet PC, a personal digital assistant (PDA), a mobile device, a palmtop computer, a laptop computer, a desktop computer, a communications device, a wireless telephone, a land-line telephone, a web appliance, a network router, switch or bridge, or any other machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single computer system 600 is illustrated, the term "system" shall also be taken to include any collection of systems or sub-systems that individually or jointly execute a set, or multiple sets, of instructions to perform one or more computer functions.

The computer system 600 may include a processor 602 e.g., a central processing unit (CPU), a graphics processing unit (GPU), or both. The processor 602 may be a component in a variety of systems. For example, the processor 602 may be part of a standard personal computer or a workstation. The processor 602 may be one or more general processors, digital signal processors, application specific integrated circuits, field programmable gate arrays, servers, networks, digital circuits, analog circuits, combinations thereof, or other now known or later developed devices for analysing and processing data. The processor 602 may implement a software program, such as code generated manually (i.e., programmed).

The computer system 600 may include a memory 604, such as a memory 604 that can communicate via a bus 608. The memory 604 may include, but is not limited to computer readable storage media such as various types of volatile and non-volatile storage media, including but not limited to random access memory, read-only memory, programmable read-only memory, electrically programmable read-only memory, electrically erasable read-only memory, flash memory, magnetic tape or disk, optical media and the like. In one example, the memory 604 includes a cache or random access memory for the processor 602. In alternative examples, the memory 604 is separate from the processor 602, such as a cache memory of a processor, the system memory, or other memory. The memory 604 may be an external storage device or database for storing data. The memory 604 is operable to store instructions executable by the processor 602. The functions, acts or tasks illustrated in the figures or described may be performed by the programmed processor 602 for executing the instructions stored in the memory 604. The functions, acts or tasks are independent of the particular type of instructions set, storage media, processor or processing strategy and may be performed by software, hardware, integrated circuits, firm-ware, micro-code and the like, operating alone or in combination. Likewise, processing strategies may include multiprocessing, multitasking, parallel processing and the like.

As shown, the computer system 600 may or may not further include a display unit 610, such as a liquid crystal display (LCD), an organic light emitting diode (OLED), a flat panel display, a solid state display, a cathode ray tube (CRT), a projector, a printer or other now known or later developed display device for outputting determined information. The display 610 may act as an interface for the user to see the functioning of the processor 602, or specifically as an interface with the software stored in the memory 604 or in the drive unit 616.

Additionally, the computer system 600 may include an input device 612 configured to allow a user to interact with any of the components of system 600. The computer system 600 may also include a disk or optical drive unit 616. The disk drive unit 616 may include a computer-readable medium 622 in which one or more sets of instructions 624, e.g. software, can be embedded. Further, the instructions 624 may embody one or more of the methods or logic as described. In a particular example, the instructions 624 may reside completely, or at least partially, within the memory 604 or within the processor 602 during execution by the computer system 600.

The present invention contemplates a computer-readable medium that includes instructions 624 or receives and executes instructions 624 responsive to a propagated signal so that a device connected to a network 626 can communicate voice, video, audio, images or any other data over the network 626. Further, the instructions 624 may be transmitted or received over the network 626 via a communication port or interface 620 or using a bus 608. The communication port or interface 620 may be a part of the processor 602 or may be a separate component. The communication port 620 may be created in software or may be a physical connection in hardware. The communication port 620 may be configured to connect with a network 626, external media, the display 610, or any other components in system 600, or combinations thereof. The connection with the network 626 may be a physical connection, such as a wired Ethernet connection or may be established wirelessly as discussed later. Likewise, the additional connections with other components of the system 600 may be physical connections or may be established wirelessly. The network 626 may alternatively be directly connected to the bus 608.

The network 626 may include wired networks, wireless networks, Ethernet AVB networks, or combinations thereof. The wireless network may be a cellular telephone network, an 802.11, 802.16, 802.20, 802.1Q or WiMax network. Further, the network 626 may be a public network, such as the Internet, a private network, such as an intranet, or combinations thereof, and may utilize a variety of networking protocols now available or later developed including, but not limited to TCP/IP based networking protocols. The system is not limited to operation with any particular standards and protocols. For example, standards for Internet and other packet switched network transmission (e.g., TCP/IP, UDP/IP, HTML, HTTP) may be used.

At least by virtue of aforesaid, only one SPI interface required with two GPIOs for Role arbitration, thereby enabling efficient use of peripherals. Moreover, there is achieved cost saving by efficient use of peripherals, since the unused other SPI can be used for another interface.

This present subject matter refers a mechanism to handle SPI communication between two nodes and executed at both ends. To achieve efficient dynamic-role based SPI communication between the nodes, the present subject matter requires a single SPI interface and 2 GPIOs (general-purpose input/output) terminals. GPIO are used for dynamic role configuration and for indication to another node.

The drawings and the forgoing description give examples of embodiments. Those skilled in the art will appreciate that one or more of the described elements may well be combined into a single functional element. Alternatively, certain elements may be split into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, orders of processes described herein may be changed and are not limited to the manner described herein.

Moreover, the actions of any flow diagram need not be implemented in the order shown; nor do all of the acts necessarily need to be performed. Also, those acts that are not dependent on other acts may be performed in parallel with the other acts. The scope of embodiments is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of embodiments is at least as broad as given by the following claims.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any component(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or component of any or all the claims.

WE CLAIM

A serial to parallel interface (SPI) communication system (300) between two nodes comprising:
at least one SPI interface (306):
a plurality of input/output I/O terminals connected through the SPI interface ;
a processor (602) configured for:
maintaining a recipient status and a transmitter status of the I/O terminals;
allowing transfer of data from a first I/O terminal (302) as a master to a second I/O terminal (304) based on checking a current recipient-status of the first terminal (304) as LOW;
setting the transmitter-status of the first I/O terminal (302) as HIGH based on said allowance;
transferring data from the first I/O terminal (302) to the second I/O terminal (304); and
resetting the transmitter-status of the first I/O terminal (302) as LOW based on completion of said transfer.

2. The communication system (300) as claimed in claim 1, wherein the I/O terminals correspond to GPIOs (input/output) terminals.

3. The communication system (300) as claimed in claim 2, wherein the maintaining comprises initializing by a library the plurality of I/O terminals as slave while setting of the recipient status of the plurality of I/O terminals as LOW.

4. The communication system (300) as claimed in claim 1, wherein setting the transmitter-status of the first I/O terminal (302) as HIGH further comprises:

setting the recipient status of the second I/O terminal (304) as HIGH.

5. The communication system (300) as claimed in claim 1, wherein the processor (602) is further configured for:

rejecting a request for transfer of data from the first I/O terminal (302) as the master to the second I/O terminal (304) based on checking the current recipient-status of the first terminal as HIGH.

6. The communication system (300) as claimed in claim 1, wherein the resetting the transmitter-status of the first I/O terminal (302) as LOW based on completion of said transfer further comprises:
resetting the recipient-status of the second I/O terminal (304) as LOW based on completion of said transfer.

7. The communication system (300) as claimed in claim 1, wherein the allowing of the transfer of data from the first I/O terminal (302) as the master to the second I/O terminal (304) is further based on a priority associated with first I/O terminal (302).

8. A method implemented in a serial to parallel interface (SPI) communication system between two nodes comprising:

connecting (step 102) a plurality of input/output I/O terminals (302, 304) connected through a SPI interface (306);
maintaining (step 104) a recipient status and a transmitter status of the plurality of the I/O terminals;
allowing (step 106) transfer of data from a first I/O terminal (302) as a master to a second I/O terminal (304) based on checking a current recipient-status of the first I/O terminal (302) as LOW;
setting (step 108) the transmitter-status of the first I/O terminal (302) as HIGH based on said allowance;
transferring (step 110) data from the first I/O terminal (302) to the second I/O terminal (304); and
resetting (step 112) the transmitter-status of the first I/O terminal (302) as LOW based on completion of said transfer.

9. The method as claimed in claim 8, wherein the initialization comprises:

initializing by a library the plurality of I/O terminals (302, 304) as slave as a part of setting of the recipient status as LOW.

10. The method as claimed in claim 8, wherein setting the transmitter-status of the first I/O terminal (302) as HIGH further comprises:

setting the recipient status of the second I/O terminal (304) as HIGH; and

resetting the transmitter-status of the first I/O terminal (302) as LOW based on completion of said transfer.