CLIAMS:We claim:
1. A startup circuit for use with a switched-capacitor voltage regulator circuit, the startup circuit comprising:
a comparator operative to generate a first control signal as a function of a comparison between an output voltage generated by the switched-capacitor voltage regulator circuit and a reference voltage, the first control signal being used to disable the startup circuit;
a reference generator coupled with the comparator and operative to generate at least first, second and third voltages, the second voltage being greater than the first voltage and the third voltage being greater than the second voltage; and
a controller coupled with the reference generator and operative to dynamically select a given one of the first and third voltages as the reference voltage supplied to the comparator as a function of the first control signal.
2. The startup circuit of claim 1, further comprising a bias circuit adapted for connection with an output of the switched-capacitor voltage regulator circuit, the bias circuit being operative to increase the output voltage generated by the switched-capacitor voltage regulator circuit during a first mode of operation of the startup circuit, the bias circuit being disabled during a second mode of operation of the startup circuit, the mode of operation of the startup circuit being controlled as a function of the first control signal.
3. The startup circuit of claim 2, wherein the bias circuit comprises:
at least a first PMOS transistor having a first source/drain adapted for connection with a voltage supply of the startup circuit, a gate adapted to receive a bias signal which is a function of the first control signal, and a second source/drain adapted for connection with the output of the switched-capacitor voltage regulator circuit;
at least first and second NMOS transistors, a gate and first source/drain of the first NMOS transistor being adapted for connection with the output of the switched-capacitor voltage regulator circuit, a second source/drain of the first NMOS transistor being connected with a gate and first source/drain of the second NMOS transistor, and a second source/drain of the second NMOS transistor being adapted for connection with a voltage return of the startup circuit.
4. The startup circuit of claim 3, wherein the bias circuit further comprises a powerdown circuit coupled with the gate of the first PMOS transistor, the power-down circuit being adapted to receive a power-down signal and to disable the bias circuit as a function of the powerdown signal.
5. The startup circuit of claim 1, wherein the controller comprises a multiplexer adapted to receive the first and third voltages generated by the reference circuit and to generate the reference voltage supplied to the comparator as a function of the first control signal.
6. The startup circuit of claim 1, further comprising reset circuitry operative to generate a reset control signal as a function of a level-shifted version of the first control signal, the reset control signal being operative to initialize at least one circuit element in the switched-capacitor voltage regulator circuit.
7. The startup circuit of claim 6, wherein the reset circuitry comprises a delay element having a prescribed delay associated therewith, the delay element being adapted to receive the first control signal and being operative to generate a delayed version of the first control signal, the reset circuitry being operative to generate the reset control signal as a function of the first control signal and the delayed version of the first control signal.
8. The startup circuit of claim 1, further comprising a power-down circuit coupled with an output of the comparator, the power-down circuit being adapted to receive a power-down signal and to disable the startup circuit as a function of the power-down signal.
9. The startup circuit of claim 1, wherein a magnitude of a difference between the first and third voltages is configured to be greater than or equal to an amplitude of a ripple component in the output voltage generated by the switched-capacitor voltage regulator circuit.
10. The startup circuit of claim 1, wherein at least a portion of the startup circuit is fabricated in at least one integrated circuit.
11. A switched-capacitor voltage regulator circuit, comprising:
at least a first comparator operative to receive a first input signal indicative of a regulated output signal of the voltage regulator circuit and a second input signal indicative of a first reference signal and to generate an output signal indicative of a comparison result between the first and second input signals;
a clock generator operative to receive the output signal generated by the first comparator and to generate a plurality of clock signals;
a switched-capacitor circuit operative to receive the plurality of clock signals and to generate, at an output of the switched-capacitor voltage regulator circuit, the regulated output signal as a function of the plurality of clock signals; and
a startup circuit coupled with at least one node in the voltage regulator circuit and operative to maintain a flow of current in the voltage regulator circuit, the startup circuit comprising:
a second comparator operative to generate a first control signal as a function of a comparison between the regulated output signal and a second reference signal, the first control signal being used to disable the startup circuit;
a reference generator coupled with the second comparator and operative to generate at least first, second and third voltages, the second voltage being greater than the first voltage and the third voltage being greater than the second voltage; and
a controller coupled with the reference generator and operative to dynamically select a given one of the first and third voltages as the second reference signal supplied to the second comparator as a function of the first control signal.
12. The switched-capacitor voltage regulator circuit of claim 11, further comprising a latch circuit coupled the first comparator and operative to hold the output signal indicative of the comparison result between the first and second input signals for a prescribed period of time.
13. The switched-capacitor voltage regulator circuit of claim 11, wherein the startup circuit further comprises a bias circuit adapted for connection with the output of the switchedcapacitor voltage regulator circuit, the bias circuit being operative to increase the output voltage generated by the switched-capacitor voltage regulator circuit during a first mode of operation of the startup circuit, the bias circuit being disabled during a second mode of operation of the startup circuit, the mode of operation of the startup circuit being controlled as a function of the first control signal.
14. The switched-capacitor voltage regulator circuit of claim 13, wherein the bias circuit comprises:
at least a first PMOS transistor having a first source/drain adapted for connection with a voltage supply of the startup circuit, a gate adapted to receive a bias signal which is a function of the first control signal, and a second source/drain adapted for connection with the output of the switched-capacitor voltage regulator circuit;
at least first and second NMOS transistors, a gate and first source/drain of the first NMOS transistor being adapted for connection with the output of the switched-capacitor voltage regulator circuit, a second source/drain of the first NMOS transistor being connected with a gate and first source/drain of the second NMOS transistor, and a second source/drain of the second NMOS transistor being adapted for connection with a voltage return of the switchedcapacitor voltage regulator circuit.
15. The switched-capacitor voltage regulator circuit of claim 14, wherein the bias circuit further comprises a power-down circuit coupled with the gate of the first PMOS transistor, the power-down circuit being adapted to receive a power-down signal and to disable the bias circuit as a function of the power-down signal.
16. The switched-capacitor voltage regulator circuit of claim 11, wherein the controller comprises a multiplexer adapted to receive the first and third voltages generated by the reference circuit and to generate the second reference voltage supplied to the second comparator as a function of the first control signal.
17. The switched-capacitor voltage regulator circuit of claim 11, further comprising reset circuitry operative to generate a reset control signal as a function of a level-shifted version of the first control signal, the reset control signal being operative to initialize at least one circuit element in the switched-capacitor voltage regulator circuit.
18. The switched-capacitor voltage regulator circuit of claim 17, wherein the reset circuitry comprises a delay element having a prescribed delay associated therewith, the delay element being adapted to receive the first control signal and being operative to generate a delayed version of the first control signal, the reset circuitry being operative to generate the reset control signal as a function of the first control signal and the delayed version of the first control signal.
19. The switched-capacitor voltage regulator circuit of claim 11, further comprising a power-down circuit coupled with an output of the second comparator, the power-down circuit being adapted to receive a power-down signal and to disable the startup circuit as a function of the power-down signal.
20. An electronic system, comprising:
at least one integrated circuit including at least one switched-capacitor voltage regulator circuit, the at least one switched-capacitor voltage regulator circuit comprising:
at least a first comparator operative to receive a first input signal indicative of a regulated output signal of the voltage regulator circuit and a second input signal indicative of a first reference signal and to generate an output signal indicative of a comparison result between the first and second input signals;
a clock generator operative to receive the output signal generated by the first comparator and to generate a plurality of clock signals;
a switched-capacitor circuit operative to receive the plurality of clock signals and to generate, at an output of the switched-capacitor voltage regulator circuit, the regulated output signal as a function of the plurality of clock signals; and
a startup circuit coupled with at least one node in the voltage regulator circuit and operative to maintain a flow of current in the voltage regulator circuit, the startup circuit comprising:
a second comparator operative to generate a first control signal as a function of a comparison between the regulated output signal and a second reference signal, the first control signal being used to disable the startup circuit;
a reference generator coupled with the second comparator and operative to generate at least first, second and third voltages, the second voltage being greater than the first voltage and the third voltage being greater than the second voltage; and
a controller coupled with the reference generator and operative to dynamically select a given one of the first and third voltages as the second reference signal supplied to the second comparator as a function of the first control signal. ,TagSPECI:As attached