FORM 2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
[See section 10, Rule 13]
MOTOR CONTROL APPARATUS AND ELECTRIC POWER STEERING APPARATUS;
MITSUBISHI ELECTRIC CORPORATION, A CORPORATION ORGANISED AND EXISTING
UNDER THE LAWS OF JAPAN, WHOSE ADDRESS IS 7-3, MARUNOUCHI 2-CHOME,
CHIYODA-KU, TOKYO 1008310, JAPAN
THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND
THE MANNER IN WHICH IT IS TO BE PERFORMED
2
DESCRIPTION
Technical Field
[0001]
The present disclosure relates to a motor control apparatus and
5 an electric power steering apparatus.
Background Art
[0002]
In a conventional electric-power-steering motor control
10 apparatus, a motor control circuit of a motor control unit transmits
a control signal to a motor driving unit; in according with the control
signal, the motor control unit supplies a motor with a current. In
this case, there is provided an interlock circuit for cutting off
the connection between the motor control circuit and the motor driving
15 unit in the case where an abnormal state in each of the motor driving
unit and the motor control circuit is monitored and any abnormality
is detected. The motor control unit includes the motor control
circuit and the interlock circuit. The motor control apparatus
includes the motor control unit and the motor driving unit. The
20 interlock circuit is provided independently from the motor control
circuit. The motor control circuit receives a signal from the
interlock circuit and then cuts off the connection between the motor
control circuit and the motor driving unit (e.g., refer to Patent
Document 1).
25
3
Citation List
Patent Literature
[0003]
[Patent Document 1] Japanese Patent Application Laid-Open No.
5 H1-257675
Summary of Invention
Technical Problem
[0004]
10 In a conventional motor control apparatus, there is provided
an interlock circuit for cutting off the connection between the motor
control circuit and the motor driving unit in the case where an
abnormal state in each of the motor driving unit and the motor control
circuit is monitored and any abnormality is determined. There has
15 been a problem that because in order to provide such an interlock
circuit independently from the motor control circuit, a monitoring
circuit and a cutoff circuit are provided, the respective circuits
of the motor control unit and the motor driving unit become complicated
and large-scaled, which results in upsizing of the motor control
20 apparatus and increase in the weight and the cost thereof.
[0005]
The objective of a technology according to the present
disclosure is to obtain a motor control apparatus that requires no
complicated and large-scaled circuit, that determines whether or not
25 any one of the motor driving unit and the motor control circuit is
4
abnormal, based on the output of the motor control unit, and that
can cut off the connection between the motor control circuit and the
motor driving unit, when an abnormality is determined.
[0006]
5 In addition, the objective thereof is to obtain an electric power
steering apparatus that requires no complicated and large-scaled
circuit, that determines whether or not any one of the motor driving
unit and the motor control circuit is abnormal, and that can cut off
the motor driving unit, when an abnormality is determined.
10
Solution to Problem
[0007]
A motor control apparatus according to the present disclosure
includes
15 a motor,
a motor driving unit that supplies a current to the motor,
a motor control unit that transmits a control signal for
controlling a current to be supplied by the motor driving unit, and
a cutoff apparatus that is disposed between the motor
20 control unit and the motor driving unit and that cuts off the control
signal transmitted from the motor control unit to the motor driving
unit, when the control signal deviates from a predetermined range.
[0008]
An electric power steering apparatus according to the present
25 disclosure includes the foregoing motor control apparatus.
5
Advantage of Invention
[0009]
Neither a motor control apparatus nor an electric power steering
5 apparatus according to the present disclosure requires a large-scaled
circuit such as an interlock circuit and can determine an abnormality
from an output of a motor control unit and can cut off the connection
between the motor control unit and a motor driving unit, when an
abnormality is determined. As a result, it is made possible to obtain
10 an apparatus having an effective cutoff circuit, while suppressing
the motor control apparatus from being upsized, increasing its weight,
and increasing its cost.
Brief Description of Drawings
15 [0010]
FIG. 1 is a configuration diagram of a motor control apparatus
according to Embodiment 1;
FIG. 2 is a hardware configuration diagram of the motor control
apparatus according to Embodiment 1;
20 FIG. 3 is a flowchart of main processing by a cutoff apparatus
in the motor control apparatus according to Embodiment 1;
FIG. 4 is a flowchart of initialization processing by the cutoff
apparatus in the motor control apparatus according to Embodiment 1;
FIG. 5 is a flowchart of short-circuit determination processing
25 and wrong-output determination processing by the cutoff apparatus
6
in the motor control apparatus according to Embodiment 1;
FIG. 6 is a flowchart of excess-current determination processing
by the cutoff apparatus in the motor control apparatus according to
Embodiment 1;
5 FIG. 7 is a flowchart of cutoff processing by the cutoff
apparatus in the motor control apparatus according to Embodiment 1;
FIG. 8 is a configuration diagram of a motor control apparatus
according to Embodiment 2;
FIG. 9 is a flowchart of main processing by a cutoff apparatus
10 in the motor control apparatus according to Embodiment 2;
FIG. 10 is a flowchart of short-circuit determination processing
and wrong-output determination processing by the cutoff apparatus
in the motor control apparatus according to Embodiment 2;
FIG. 11 is a hardware configuration diagram of a motor control
15 apparatus according to Embodiment 3;
FIG. 12 is a configuration diagram of an electric power steering
apparatus according to Embodiment 4; and
FIG. 13 is a hardware configuration diagram of a motor control
apparatus according to a conventional example.
20
Description of Embodiments
[0011]
Hereinafter, a motor control apparatus and an electric power
steering apparatus according to the present disclosure will be
25 explained with reference to the drawings.
7
[0012]
1. Embodiment 1
Hereinafter, a motor control apparatus 10 according to
Embodiment 1 will be explained with reference to the drawings. FIG.
5 1 is a configuration diagram of the motor control apparatus 10
according to Embodiment 1. FIG. 2 is a hardware configuration diagram
of the motor control apparatus 10 according to Embodiment 1. FIG.
3 is a flowchart of main processing by a cutoff apparatus 7 in the
motor control apparatus 10 according to Embodiment 1. FIG. 4 is a
10 flowchart of initialization processing by the cutoff apparatus 7 in
the motor control apparatus 10 according to Embodiment 1. FIG. 5 is
a flowchart of short-circuit determination processing and
wrong-output determination processing by the cutoff apparatus 7 in
the motor control apparatus 10 according to Embodiment 1. FIG. 6 is
15 a flowchart of excess-current determination processing by the cutoff
apparatus 7 in the motor control apparatus 10 according to Embodiment
1. FIG. 7 is a flowchart of cutoff processing by the cutoff apparatus
7 in the motor control apparatus 10 according to Embodiment 1. FIG.
13 is a configuration diagram of a motor control apparatus 13 according
20 to a conventional example.
[0013]

The motor control apparatus 13 according to a conventional
example includes a motor driving unit 3 and a motor control unit 17
25 having a computing processing unit 1, a motor control circuit 22,
8
and an interlock circuit 4. An input signal from the outside is
inputted to the computing processing unit 1 (unillustrated). Based
on the input signal, the computing processing unit 1 calculates a
current to be supplied to a motor 6, outputs a command to a motor
5 control circuit 22, and then outputs a control signal to the motor
driving unit 3 by way of the motor control circuit 22. In accordance
with the control signal received from the motor control circuit 22,
the motor driving unit 3 supplied a current to the motor 6 through
motor connection terminals 41 and 42.
10 [0014]
The motor driving unit 3 in FIG. 13 incorporates
positive-polarity field-effect transistors 31 and 33 (hereinafter,
referred to as positive-polarity FETs 31 and 33) and negative-polarity
FETs 32 and 34. The positive-polarity FET 31 and the
15 negative-polarity FET 32 are connected in series with each other
between a positive-polarity power source and a negative-polarity
power source; the connection point is connected with the motor
connection terminal 41. The positive-polarity FET 33 and the
negative-polarity FET 34 are connected in series with each other
20 between the positive-polarity power source and the negative-polarity
power source; the connection point is connected with the motor
connection terminal 42. The motor connection terminals 41 and 42 are
connected with the motor 6. The motor driving unit 3 is connected
with the positive-polarity power source and the negative-polarity
25 power source; however, the negative-polarity power source is
9
connected with the motor driving unit 3 through a resistor of a current
detection circuit.
[0015]
When supplying a current so as to drive the motor 6, the motor
5 driving unit 3 turns on the positive-polarity FET 31, turns off the
negative-polarity FET 32, turns off the positive-polarity FET 33,
and turns on the negative-polarity FET 34 so as to pour the current
into the motor 6 through the motor connection terminal 41 and to suck
the current out of the motor through the motor connection terminal
10 42. Alternatively, the motor driving unit 3 turns off the
positive-polarity FET 31, turns on the negative-polarity FET 32, turns
on the positive-polarity FET 33, and turns off the negative-polarity
FET 34 so as to pour the current into the motor 6 through the motor
connection terminal 42 and to suck the current out of the motor through
15 the motor connection terminal 41. Accordingly, there exists neither
the case where both the positive-polarity FET 31 and the
positive-polarity FET 33 are regularly and concurrently turned on
nor the case where both the negative-polarity FET 32 and the
negative-polarity FET 34 are regularly and concurrently turned on.
20 It can be determined that such an output is wrong and abnormal.
[0016]
In parallel with the motor control circuit 22, the interlock
circuit 4 receives the contents of a command that is issued to the
motor control circuit 22 by the computing processing unit 1. In the
25 case where the contents of the command are wrong, the interlock circuit
10
4 determines an abnormality and then outputs a cutoff signal to the
motor control circuit 22. For example, in the case where the computing
processing unit 1 outputs a command for concurrently turning on the
positive-polarity FET 31 and the positive-polarity FET 33 of the motor
5 driving unit 3 or in the case where the computing processing unit
1 outputs a command for concurrently turning on the negative-polarity
FET 32 and the negative-polarity FET 34 of the motor driving unit
3, the interlock circuit 4 determines that the command of the computing
processing unit 1 is wrong. In this case, the interlock circuit 4
10 outputs the cutoff signal to the motor control circuit 22 so as to
disconnect the motor control unit 17 from the motor driving unit 3.
[0017]
In addition, even when the computing processing unit 1 outputs
a correct signal for driving the motor 6, the interlock circuit 4
15 determines whether or not the current flowing in the motor driving
unit 3 corresponds to an excessive current, based on an output voltage
of a current detection circuit 5. In the case where the output voltage
of the current detection circuit 5 exceeds an excessive-current
determination voltage, the interlock circuit 4 determines that an
20 excessive current is flowing in the motor driving unit 3 and then
outputs the cutoff signal to the motor control circuit 22.
[0018]
In such a manner as described above, the interlock circuit 4
can determine an abnormality in the motor control apparatus 13
25 independently from the motor control circuit 22, can output the cutoff
11
signal to the motor control circuit 22, and can disconnect the motor
control unit 17 from the motor driving unit 3. As a result, the motor
driving unit 3 and the motor 6 can be prevented from failing and
deteriorating.
5 [0019]
However, in order to monitor whether or not the command outputted
to the motor control circuit 22 by the computing processing unit 1
is wrong, the interlock circuit 4 requires a circuit configuration
for separately receiving a command value from the computing processing
10 unit 1. Moreover, in order to monitor an excessive current in the
motor driving unit 3, it is required to provide the current detection
circuit 5, a wiring lead from the current detection circuit 5, and
a comparison circuit for a detection value. Furthermore, it is
required to provide a cutoff circuit for transfer the cutoff signal
15 from the interlock circuit 4 to the motor control circuit 22 and for
cutting off the connection between the motor control circuit 22 and
the motor driving unit 3.
[0020]
Therefore, providing the interlock circuit 4 poses a problem
20 that because in order to provide the interlock circuit 4 independently
from the motor control circuit 22, a monitoring circuit and a cutoff
circuit are provided, the respective circuits of the motor control
unit 17 and the motor driving unit 3 become complicated and
large-scaled, which results in upsizing of the motor control apparatus
25 13 and increase in the weight and the cost thereof.
12
[0021]

FIG. 1 is a configuration diagram of the motor control apparatus
10 according to Embodiment 1. The motor control apparatus 10 in FIG.
5 1 includes a motor control unit 15 having the computing processing
unit 1 and a motor control circuit 20, the cutoff apparatus 7, and
the motor driving unit 3. The motor control apparatus 10 in FIG. 1
is different from the conventional example in FIG. 12 in that there
exists no interlock circuit 4 and in that the cutoff apparatus 7 is
10 inserted between the motor control circuit 20 and the motor driving
unit 3.
[0022]
An input signal from the outside is inputted to the computing
processing unit 1 (unillustrated). Based on the input signal, the
15 computing processing unit 1 calculates a current to be supplied to
the motor 6, outputs a command to the motor control circuit 20, and
then outputs a control signal to the motor driving unit 3 by way of
the motor control circuit 20. The motor control circuit 20 transfers
a control signal to the motor driving unit 3 by way of the cutoff
20 apparatus 7. In accordance with the control signal received from the
motor control circuit 20, the motor driving unit 3 supplied a current
to the motor 6 through the motor connection terminals 41 and 42.
[0023]
The motor driving unit 3 in FIG. 1 is the same as the motor driving
25 unit 3 according to the conventional example in FIG. 13. The cutoff
13
apparatus 7 receives the output of the motor control circuit 20; in
the case where no abnormality exists, the output is directly
transferred to the motor driving unit 3. In the case where any
abnormality exists in the output of the motor control circuit 20,
5 the cutoff apparatus 7 cuts off the output of the motor control circuit
20 and does not transfer the output to the motor driving unit 3. In
addition, it may be allowed that the input and the output of the cutoff
apparatus 7 are connected with each other through an electronic
component, such as an FET, a bipolar transistor, a thyristor, or an
10 IC (Integrated Circuit), included in a semiconductor switch and that
in the case where the cutoff is required, the connection between the
motor control unit 15 and the motor driving unit 3 is cut off. It
may be allowed that the input and the output of the cutoff apparatus
7 are connected with each other through a mechanical component such
15 as a relay and that in the case where the cutoff is required, the
connection between the motor control unit 15 and the motor driving
unit 3 is cut off by turning off the relay.
[0024]
The motor driving unit 3 in FIG. 1 incorporates the
20 positive-polarity FETs 31 and 33 and the negative-polarity FETs 32
and 34. The positive-polarity FET 31 and the negative-polarity FET
32 are connected in series with each other between the
positive-polarity power source and the negative-polarity power
source; the connection point is connected with the motor connection
25 terminal 41. The positive-polarity FET 33 and the negative-polarity
14
FET 34 are connected in series with each other between the
positive-polarity power source and the negative-polarity power
source; the connection point is connected with the motor connection
terminal 42. The motor connection terminals 41 and 42 are connected
5 with the motor 6.
[0025]

There exists neither the case where both the positive-polarity
FET 31 and the positive-polarity FET 33 of the motor driving unit
10 3 are concurrently turned on nor the case where both the
negative-polarity FET 32 and the negative-polarity FET 34 thereof
are concurrently turned on. It can be determined that such an output
is wrong and abnormal. The cutoff apparatus 7 monitors the control
signal received from the motor control circuit 20; in the case where
15 the control signal is wrong, the cutoff apparatus 7 determines an
abnormality and cuts off the output of the motor control circuit 20,
but does not transfer the control signal to the motor driving unit
3.
[0026]
20
In addition, both the positive-polarity FET 31 and the
negative-polarity FET 32 that are connected in series with each other
are turned off; alternatively, only one of thereof is turned on and
the other thereof is turned off. When both the positive-polarity FET
25 31 and the negative-polarity FET 32 are concurrently turned on, the
15
motor 6 is not driven, and a large current flows in the
positive-polarity FET 31 and the negative-polarity FET 32 that are
directly connected with each other between the positive-polarity
power source and the negative-polarity power source; thus, the motor
5 driving unit 3 is caused to fail. Similarly, both the
positive-polarity FET 33 and the negative-polarity FET 34 that are
connected in series with each other are turned off; alternatively,
only one of thereof is turned on and the other thereof is turned off.
When both the positive-polarity FET 33 and the negative-polarity FET
10 34 are concurrently turned on, the motor 6 is not driven, and a large
current flows in the positive-polarity FET 33 and the
negative-polarity FET 34 that are directly connected with each other
between the positive-polarity power source and the negative-polarity
power source; thus, the motor driving unit 3 is caused to fail.
15 [0027]
When the motor control unit 15 is normal, there exists neither
the case where both the positive-polarity FET 31 and the
negative-polarity FET 32 of the motor driving unit 3 are regularly
and concurrently turned on nor the case where both the
20 positive-polarity FET 33 and the negative-polarity FET 34 thereof
are concurrently turned on. In such a case, an excessive current
caused by the direct connection flows in the motor driving unit; thus,
in the case where the motor control unit 15 outputs such a control
signal, it is made possible that the cutoff apparatus 7 determines
25 an abnormality caused by a direct-connection excessive current, cuts
16
off the output of the motor control circuit 20, and prevents the motor
driving unit 3 from failing.
[0028]
As described above, by monitoring the control signal outputted
5 by the motor control unit 15, the cutoff apparatus 7 can determine
a wrong-output abnormality and a direct-connection excessive-current
abnormality that causes a large current to flow, and can cut off the
output of the motor control circuit 20 so as to prevent the motor
driving unit 3 from failing. In this situation, there are not required
10 a large-scaled circuit such as the interlock circuit 4 in the
conventional technology, wiring of a signal line from the computing
processing unit 1, wiring of a signal line from the current detection
circuit 5 of the motor driving unit 3, the cutoff circuit for the
motor control circuit 22, and wiring of a signal line to the cutoff
15 circuit for the motor control circuit 22. The adoption of the cutoff
apparatus 7 makes it possible to obtain a motor control apparatus
having a cutoff circuit that is effective while suppressing upsizing,
weight increase, and cost increase.
[0029]
20 Although in FIG. 1, there has been described an example where
as the switching device of the motor driving unit, an FET is utilized,
it may be allowed that the motor driving unit is configured by use
of a bipolar transistor, a thyristor, or a relay.
[0030]
25
17
With regard to driving of the motor 6, the driving current is
often controlled by duty-driving the FETs 31 through 34 of the motor
driving unit 3. In this situation, although each of the FETs 31
through 34 repeats on/off-control, the cutoff apparatus 7 can
5 calculate a motor energization current Im from the ON-time of a
duty-control period. In the case where the calculated motor
energization current Im exceeds a preliminarily determined
excessive-current determination value Iov, the cutoff apparatus 7
considers that an excessive current has flowed and then makes an
10 abnormality determination. In the case where the cutoff apparatus
7 makes an excessive-current abnormality determination, the output
of the motor control circuit 20 is cut off, so that the motor driving
unit 3 and the motor 6 can be prevented from failing.
[0031]
15
Moreover, by accumulating the respective ON-times of the FETs
31 through 34 of the motor driving unit 3 for an average-value
calculation time Tav and then dividing the accumulated ON-time by
the average-value calculation time Tav, the cutoff apparatus 7 can
20 calculate an average motor energization current Ima for the
average-value calculation time Tav. In the case where the average
motor energization current Ima exceeds a predetermined
average-current excess determination value Iova, the cutoff apparatus
7 considers that an excessive current has continued flowing for the
25 average-value calculation time Tav, determines an abnormality, cuts
18
off the output of the motor control circuit 20, so that the motor
driving unit 3 can be prevented from failing. By specifying a
determination value satisfying the equation “Iova  Iov”, a value
smaller than the excessive-current determination value Iov that
5 should not be instantaneously exceeded can be designated as the
average-current excess determination value Iova that should not be
continuously exceeded. As a result, the motor driving unit 3 and the
motor 6 can be prevented from failing and deteriorating due to an
overheating state. Each of Iova and Iov may be obtained through a
10 calculation based on the performance of a FET device to be utilized
and the impedance and reactance of the motor 6 or can be obtained
through an experiment.
[0032]
As described above, by monitoring the control signal outputted
15 by the motor control unit 15, the cutoff apparatus 7 can calculate
the motor energization current Im to be supplied by the motor driving
unit 3. In the case where the motor energization current Im exceeds
the excessive-current determination value Iov, the cutoff apparatus
7 considers that an excessive current has flowed and then makes an
20 abnormality determination, so that the output of the motor control
circuit 20 can be cut off. Moreover, the cutoff apparatus 7 calculates
the average motor energization current Ima for the average-value
calculation time Tav; in the case where the average motor energization
current Ima exceeds the average-current excess determination value
25 Iova, the cutoff apparatus 7 considers that an excessive current has
19
continued flowing for the average-value calculation time Tav and then
determines an abnormality, so that the output of the motor control
circuit 20 can be cut off. The adoption of the cutoff apparatus 7
makes it possible to obtain a motor control apparatus having a cutoff
5 circuit that requires none of a large-scaled circuit such as the
interlock circuit 4, provision of the current detection circuit 5,
and wiring of a connection line and that is effective, while
suppressing upsizing, weight increase, and cost increase.
[0033]
10
FIG. 2 is a hardware configuration diagram of a control apparatus
100 according to Embodiment 1. In the present embodiment, the
hardware configuration of the control apparatus 100 is applied to
the motor control unit 15 and the cutoff apparatus 7 of the motor
15 control apparatus 10. Respective functions of the control apparatus
100 are realized by processing circuits provided in the control
apparatus 100. Specifically, as illustrated in FIG. 2, the control
apparatus 100 includes, as the processing circuits, a computing
processing unit (computer) 90 such as a CPU (Central Processing Unit),
20 storage apparatuses 91 that exchange data with the computing
processing unit 90, an input circuit 92 that inputs external signals
to the computing processing unit 90, an output circuit 93 that outputs
signals from the computing processing unit 90 to the outside, and
the like.
25 [0034]
20
It may be allowed that as the computing processing unit 90, an
ASIC (Application Specific Integrated Circuit), an IC, a DSP (Digital
Signal Processor), an FPGA (Field Programmable Gate Array), each of
various kinds of logic circuits, each of various kinds of signal
5 processing circuits, or the like is provided. In addition, it may
be allowed that as the computing processing unit 90, two or more
computing processing units of the same type or different types are
provided and respective processing items are executed in a sharing
manner. As the storage apparatuses 91, there are provided a RAM
10 (Random Access Memory) that can read data from and write data in the
computing processing unit 90, a ROM (Read Only Memory) that can read
data from the computing processing unit 90, a flash memory, and the
like. The input circuit 92 is connected with various kinds of sensors
and switches and is provided with an A/D converter and the like for
15 inputting output signals from the sensors and the switches to the
computing processing unit 90. The output circuit 93 is connected with
electric loads and is provided with a driving circuit and the like
for converting and outputting a control signal from the computing
processing unit 90 to the electric loads.
20 [0035]
The computing processing unit 90 runs software items (programs)
stored in the storage apparatus 91 such as a ROM and collaborates
with other hardware devices in the control apparatus 100, such as
the storage apparatus 91, the input circuit 92, and the output circuit
25 93, so that the respective functions provided in the control apparatus
21
100 are realized. Setting data items such as a threshold value and
a determination value to be utilized in the control apparatus 100
are stored, as part of software items (programs), in the storage
apparatus 91 such as a ROM.
5 [0036]
It may be allowed that the respective functions included in the
control apparatus 100 in FIG. 2 are configured with either software
modules or combinations of software and hardware.
[0037]
10 It may be allowed that each of the motor control unit 15 and
the cutoff apparatus 7 is configured with a separate control apparatus
100. It may be allowed that the motor control unit 15 and the cutoff
apparatus 7 are configured as separate modules in one and the same
control apparatus. It may be allowed that the cutoff apparatus 7 is
15 not provided with the computing processing unit 90 and the storage
apparatus 91 but is configured with only hardware items such as a
logic circuit, an amplifier, an integrator, a sampling/hold device,
and a comparator.
[0038]
20 Hereinafter, there will be explained software processing to be
executed in the case where as the hardware configuration of the cutoff
apparatus 7 in the motor control apparatus 10 according to Embodiment
1, the configuration of the control apparatus 100 is utilized.
[0039]
25
22
FIG. 3 is a flowchart of main processing executed by the
computing processing unit 90 of the cutoff apparatus 7 in the motor
control apparatus 10 according to Embodiment 1. The main processing
of the control is executed every predetermined time (for example,
5 every 1 ms). In the present embodiment, there has been explained an
example where the main processing is executed every predetermined
time; however, it may be allowed that the main processing is executed
by utilizing, as a trigger, a specific signal such as a rotation-angle
signal of the motor.
10 [0040]
The computing processing unit 90 starts the processing in the
step S301, and executes initialization processing in the step S400.
The processing contents of the step S400 are represented in the steps
S401 through S419 in FIG. 4.
15 [0041]
Next, in the step S500, the computing processing unit 90 executes
direct-connection abnormality determination processing and
wrong-output abnormality determination processing. The processing
contents of the step S500 are represented in the steps S501 through
20 S519 in FIG. 5.
[0042]
Next, in the step S600, the computing processing unit 90 executes
excess-current determination processing. The processing contents of
the step S600 are represented in the steps S601 through S619 in FIG.
25 6.
23
[0043]
Next, the computing processing unit 90 executes cutoff
processing in the step S700 and ends the processing in the step S309.
The processing contents of the step S700 are represented in the steps
5 S701 through S719 in FIG. 7.
[0044]

FIG. 4 is a flowchart representing the contents of the
initialization processing. The steps S401 through S419 in FIG. 4 are
10 details of the step S400 of the flowchart in FIG. 3.
[0045]
The computing processing unit 90 starts the processing in the
step S401 and then determines in the step S402 whether or not the
present timing is immediately after the power source of the cutoff
15 apparatus 7 has been turned on. In the case where the present timing
is immediately after the power source of the cutoff apparatus 7 has
been turned on, the computing processing unit 90 executes the steps
S403 through S410 and then initializes counters and flags. In the
step S403, the computing processing unit 90 clears a direct-connection
20 abnormality counter C_shrt (“0” is set). In the step S404, the
computing processing unit 90 clears a wrong-output abnormality
counter C_ng. In the step S405, the computing processing unit 90
clears an excessive-current counter C_Iov. In the step S406, the
computing processing unit 90 clears an average-current excess counter.
25 In the step S407, the computing processing unit 90 clears a
24
direct-connection abnormality flag f_shrt. In the step S408, the
computing processing unit 90 clears a wrong-output abnormality flag
f_ng. In the step S409, the computing processing unit 90 clears an
excessive-current flag f_Iov. Then, in the step S410, the computing
5 processing unit 90 clears an average-current excess flag f_Iova and
ends the processing in the step S419.
[0046]
In the case where in the step S402, the present timing is not
immediately after the power source of the cutoff apparatus 7 has been
10 turned on, the computing processing unit 90 initializes neither the
counters nor the flags, and then ends the processing in the step S419.
[0047]

15 FIG. 5 is a flowchart representing the contents of the
direct-connection abnormality determination processing and the
wrong-output abnormality determination processing. The flowchart
for the steps S501 through S519 represents the details of the step
S500 of the flowchart in FIG. 3.
20 [0048]
The computing processing unit 90 starts the processing in the
step S501 and determines in the step S502 whether or not the control
signal outputted by the motor control unit 15 is a signal for
concurrently turning on the FET 31 and the FET 32. In the case where
25 the control signal outputted by the motor control unit 15 is a signal
25
for concurrently turning on the FET 31 and the FET 32, the signal
is an abnormal signal for making the FET 31 and the FET 32 directly
connect the positive-polarity power source and the negative-polarity
power source of the motor driving unit 3 and causes a direct-connection
5 excessive current, the step S502 is followed by the step S510, where
the direct-connection abnormality counter C_shrt is incremented; then,
in the step S519, the processing is ended.
[0049]
In the case where in the step S502, the control signal is not
10 a signal for concurrently turning on the FET 31 and the FET 32, the
step S502 is followed by the step S503. In the step S503, it is
determined whether or not the control signal outputted by the motor
control unit 15 is a signal for concurrently turning on the FET 33
and the FET 34. In the case where the control signal outputted by
15 the motor control unit 15 is a signal for concurrently turning on
the FET 33 and the FET 34, it is determined that there exists a
direct-connection abnormality; then, the step S503 is followed by
the step S510. In the case where the control signal outputted by the
motor control unit 15 is not a signal for concurrently turning on
20 the FET 33 and the FET 34, the step S503 is followed by the step S505.
[0050]
In the step S505, it is determined whether or not the control
signal outputted by the motor control unit 15 is a signal for turning
on any one of the FET 31 and the FET 33. In the case where the control
25 signal outputted by the motor control unit 15 is a signal for turning
26
on any one of the FET 31 and the FET 33, the step S505 is followed
by the step S506. In the case where both the FET 31 and the FET 33
are off, the step S505 is followed by the step S507.
[0051]
5 In the step S506, it is determined whether or not the control
signal is a signal for turning on any one of the FET 32 and the FET
34. In the case where the control signal outputted by the motor
control unit 15 is a signal for turning on any one of the FET 32 and
the FET 34, it is determined that no abnormality exists; then, the
10 step S506 is followed by the step S508. In the case where the control
signal is a signal for turning off all of the FET 32 and the FET 34,
it is determined that a wrong-output abnormality exists, because
although a current is poured into the motor 6, no current is sucked
out of the motor; in the step S511, the wrong-output abnormality
15 counter C_ng is incremented; then, in the step S519, the processing
is ended.
[0052]
In the step S507, it is determined whether or not the control
signal is a signal for turning on any one of the FET 32 and the FET
20 34. In the case where the control signal is a signal for turning on
any one of the FET 32 and the FET 34, it is determined that a
wrong-output abnormality exists, because the signal is for the state
where although no current is poured into the motor 6, a current is
sucked out of the motor; then, the step S507 is followed by the step
25 S511. In the case where the control signal is a signal for turning
27
off all of the FET 32 and the FET 34, it is determined that no
abnormality exists; then, the step S507 is followed by the step S508.
[0053]
In the step S508, the direct-connection abnormality counter
5 C_shrt is cleared. In the step S509, the wrong-output abnormality
counter C_ng is cleared. Then, the processing is ended in the step
S519.
[0054]

10 FIG. 6 is a flowchart representing the contents of the
excess-current determination processing. The flowchart for the
steps S601 through S619 represents the details of the step S600 of
the flowchart in FIG. 3.
[0055]
15 In the step S601, the processing is started; in the step S602,
the motor energization current Im to be supplied by the motor driving
unit 3 is calculated from the control signal outputted by the motor
control unit 15. With regard to driving of the motor 6, the driving
current is often controlled by duty-driving the FETs 31 through 34
20 of the motor driving unit 3. In this situation, although each of the
FETs 31 through 34 repeats on/off-control, the cutoff apparatus 7
can calculate the motor energization current Im from the ON-time of
a duty-control period. In the step S603, the newest calculated motor
energization current Im(n) is stored in the storage apparatus 91.
25 The main processing is executed every millisecond; thus, by
28
sequentially storing the motor energization currents obtained every
millisecond Im(1), Im(2), Im(3), ---, Im(n), an average motor
energization current Ima, which is the average value of the motor
energization current Im per average-value calculation time Tav can
5 be obtained. The storage areas can circulatively be utilized by use
of a ring buffer as the storage apparatus 91; thus, the averaging
processing can be implemented within a limited storage area. With
regard to the averaging, the moving average in the immediately
previous average-value calculation time Tav is obtained each time
10 the processing is executed (every millisecond). Alternatively, an
interval average value may be obtained every average-value
calculation time Tav.
[0056]
Next, in the step S 604, it is determined whether or not the
15 motor energization current Im is larger than the excessive-current
determination value Iov. In the case where the motor energization
current Im is larger than the excessive-current determination value
Iov, the step S 604 is followed by the step S608, where the
excessive-current counter C_Iov is incremented; then, the processing
20 is ended in the step S619.
[0057]
In the case where the motor energization current Im is not larger
than the excessive-current determination value Iov, the step S 604
is followed by the step S605. In the step S605, the motor energization
25 current Im in the immediately previous average-value calculation time
29
Tav is accumulated and then is divided by the average-value
calculation time Tav, so that the average motor energization current
Ima is calculated. In this example, the average motor energization
current Ima is calculated through moving averaging or through interval
5 averaging during the average-value calculation time Tav. However,
the average motor energization current Ima may be calculated every
average-value calculation time Tav through a first-order lag
calculation utilizing the equation “Ima(n)  K  Im  (1K)  Ima(n1)”.
Here, K is a constant (0  K  1); the present average motor energization
10 current Ima(n) is obtained every average-value calculation time Tav,
by use of the immediately previous average motor energization current
Ima(n1) and the newest motor energization current Im. The necessary
memory usage amount in the storage apparatus 91 can be reduced by
utilizing the first-order lag calculation.
15 [0058]
Next, in the step S 606, it is determined whether or not the
average motor energization current Ima is larger than the
average-current excess determination value Iova. In the case where
the average motor energization current Ima is larger than the
20 average-current excess determination value Iova, the step S 606 is
followed by the step S609, where the average-current excess counter
C_Iova is incremented; then, the processing is ended in the step S619.
[0059]
In the case where in the step S606, the average motor
25 energization current Ima is not larger than the average-current excess
30
determination value Iova, the motor energization current Im is not
an excessive current and the average motor energization current Ima
does not exceed the average current; therefore, the excessive-current
counter C_Iov is cleared in the step S607 and the average-current
5 excess counter C_Iova is cleared in the step S608; then, the processing
is ended in the step S619.
[0060]

FIG. 7 is a flowchart representing the contents of the cutoff
10 processing. The flowchart for the steps S701 through S719 represents
the details of the step S700 of the flowchart in FIG. 3.
[0061]
The processing is started in the step S701; in the step S702,
it is determined whether or not the value of the direct-connection
15 abnormality counter C_shrt is larger than a direct-connection
abnormality determination time T_shrt. In the case where the value
of the direct-connection abnormality counter C_shrt is larger than
the direct-connection abnormality determination time T_shrt, a
direct-connection abnormality is determined, and the step S702 is
20 followed by the step S706, where the direct-connection abnormality
flag f_shrt is set (“1” is inputted). Then, there is set a
direct-connection abnormality storage flag f_shrtM, which is not
cleared in the initialization processing, provided in a nonvolatile
storage apparatus. After that, in the step S710, the motor driving
25 unit 3 is cut off from the motor control unit 15; then, the processing
31
is ended in the step S719.
[0062]
In the case where in the step S702, the value of the
direct-connection abnormality counter C_shrt is not larger than the
5 direct-connection abnormality determination time T_shrt, the step
S702 is followed by the step S703. In the step S703, it is determined
whether or not the value of the wrong-output abnormality counter C_ng
is larger than a wrong-output abnormality determination time T_ng.
In the case where the value of the wrong-output abnormality counter
10 C_ng is larger than a wrong-output abnormality determination time
T_ng, a wrong-output abnormality is determined, and the step S703
is followed by the step S707. In the step S707, the wrong-output
abnormality flag f_ng is set. Then, there is set a wrong-output
abnormality storage flag f_ngM, which is not cleared in the
15 initialization processing, provided in a nonvolatile storage
apparatus; then, the step S707 is followed by the step S710.
[0063]
In the case where in the step S703, the value of the wrong-output
abnormality counter C_ng is not larger than the wrong-output
20 abnormality determination time T_ng, the step S703 is followed by
the step S704. In the step S704, it is determined whether or not the
value of the excessive-current counter C_Iov is larger than an
excessive-current determination time T_Iov. In the case where the
value of the excessive-current counter C_Iov is larger than the
25 excessive-current determination time T_Iov, an excessive-current
32
determination is settled, and the step S704 is followed by the step
S708. In the step S708, the excessive-current flag f_Iov is set.
Then, there is set an excessive-current storage flag f_IovM, which
is not cleared in the initialization processing, provided in an
5 nonvolatile storage apparatus; then, the step S708 is followed by
the step S710.
[0064]
In the case where in the step S704, the value of the
excessive-current counter C_Iov is not larger than the
10 excessive-current determination time T_Iov, the step S704 is followed
by the step S705. In the step S705, it is determined whether or not
the value of the average-current excess counter C_Iova is larger than
an average-current excess time T_Iova. In the case where the value
of the average-current excess counter C_Iova is larger than the
15 average-current excess time T_Iova, an average-current excess
determination is settled, and the step S705 is followed by the step
S709. In the step S709, the average-current excess flag f_Iova is
set. Then, there is set an average-current excess storage flag
f_IovaM, which is not cleared in the initialization processing,
20 provided in a nonvolatile storage apparatus; then, the step S709 is
followed by the step S710.
[0065]
In the case where in the step S705, the value of the
average-current excess counter C_Iova is not larger than the
25 average-current excess time T_Iova, the step S705 is followed by the
33
step S719, where the processing is ended. As far as the respective
values of the direct-connection abnormality determination time T_shrt,
the wrong-output abnormality determination time T_ng, the
excessive-current determination time T_Iov, and the average-current
5 excess time T_Iova are concerned, a time suitable for determining
each of the respective abnormalities can be set through an experiment
or a desktop calculation.
[0066]
Such a configuration makes it possible to realize the function
10 of the cutoff apparatus 7 by means of software. As a result, it is
made possible to obtain the effective cutoff apparatus 7, while
suppressing the motor control apparatus 10 from being upsized,
increasing its weight, and increasing its cost. In addition, in the
case where when the cutoff processing is executed, flags indicating
15 the causes of the cutoffs are stored in a nonvolatile storage apparatus,
the postliminary investigation is facilitated.
[0067]
2. Embodiment 2
A motor control apparatus 11 according to Embodiment 2 will be
20 explained with reference to the drawings. FIG. 8 is a configuration
diagram of the motor control apparatus 11 according to Embodiment
2. FIG. 9 is a flowchart of main processing by a cutoff apparatus
71 in the motor control apparatus 11 according to Embodiment 2. FIG.
10 is a flowchart of short-circuit determination processing and
25 wrong-output determination processing by the cutoff apparatus 71 in
34
the motor control apparatus 11 according to Embodiment 2.
[0068]

In Embodiment 1, the motor 6 connected with the two connection
5 terminals 41 and 42 has been exemplarily represented; however, the
number of the connection terminals to be connected with the motor
is not limited to two. In Embodiment 2, as shown in FIG. 8, there
is represented an example where the motor control apparatus 11 is
applied to the three-phase AC motor 61 connected with three connection
10 terminals 41, 42, and 43. In contrast to the configuration diagram
in FIG. 1, in FIG. 8, a motor driving unit 39 has six FETs 31 through
36 and currents are supplied to the three-phase AC motor 61 through
the three connection terminals 41, 42, and 43. In response to a
command from the computing processing unit 101, a motor control
15 circuit 21 outputs a control signal to the six FETs 31 through 36.
[0069]
The cutoff apparatus 71 is provided between a motor control unit
16 and the motor driving unit 39 and outputs the control signal,
received from the motor control unit 16, to the motor driving unit
20 39. The cutoff apparatus 71 detects various kinds of abnormalities
from the control signal and cuts off the motor driving unit 39 from
the motor control unit 16 at a time when an abnormality exists.
[0070]
There will be explained software processing to be executed at
25 a time when the configuration of the control apparatus 100 is applied
35
to the configuration of the cutoff apparatus 71.
[0071]

FIG. 9 is a flowchart of main processing executed by the
5 computing processing unit 90 of the cutoff apparatus 71 in the motor
control apparatus 11 according to Embodiment 2. The main processing
of the control is executed every predetermined time (for example,
every 1 ms). In the present embodiment, there has been explained an
example where the main processing is executed every predetermined
10 time; however, it may be allowed that the main processing is executed
by utilizing, as a trigger, a specific signal such as a rotation-angle
signal of the motor.
[0072]
The computing processing unit 90 starts the processing in the
15 step S901, and executes initialization processing in the step S400.
The processing contents of the step S400 are the same as those in
Embodiment 1 and are represented in the steps S401 through S419 in
FIG. 4.
[0073]
20 Next, in the step S1000, the computing processing unit 90
executes direct-connection abnormality determination processing and
wrong-output abnormality determination processing. The processing
contents of the step S1000 are represented in the steps S1001 through
S1019 in FIG. 10.
25 [0074]
36
Next, in the step S600, the computing processing unit 90 executes
excess-current determination processing. The processing contents of
the step S600 are the same as those in Embodiment 1 and are represented
in the steps S601 through S619 in FIG. 6.
5 [0075]
Next, the computing processing unit 90 executes cutoff
processing in the step S700 and ends the processing in the step S909.
The processing contents of the step S700 are the same as those in
Embodiment 1 and are represented in the steps S701 through S719 in
10 FIG. 7.
[0076]

FIG. 10 is a flowchart representing the contents of the
15 direct-connection abnormality determination processing and the
wrong-output abnormality determination processing. The flowchart
for the steps S1001 through S1019 represents the details of the step
S1000 of the flowchart in FIG. 9.
[0077]
20 The flowchart in FIG. 10 is different from the flowchart in FIG.5
according to Embodiment 1 in that the step S1004 is added to the steps
S501 through S519 because the number of the FETs has increased from
4 to 6 and in that the number of the FETs in each of the steps S1005,
S1006, and S1007 has increased by 1 from the number of the FETs in
25 each of the steps S505, S506, and S507.
37
[0078]
The computing processing unit 90 starts the processing in the
step S1001 and determines in the step S1002 whether or not the control
signal outputted by the motor control unit 16 is a signal for
5 concurrently turning on the FET 31 and the FET 32. In the case where
the control signal outputted by the motor control unit 15 is a signal
for concurrently turning on the FET 31 and the FET 32, the signal
is an abnormal signal for making the FET 31 and the FET 32 directly
connect the positive-polarity power source and the negative-polarity
10 power source of the motor driving unit 3 and causes a direct-connection
excessive current, the step S1002 is followed by the step S1010, where
the direct-connection abnormality counter C_shrt is incremented; then,
in the step S1019, the processing is ended.
[0079]
15 In the case where in the step S1002, the control signal is not
a signal for concurrently turning on the FET 31 and the FET 32, the
step S1002 is followed by the step S1003. In the step S1003, it is
determined whether or not the control signal outputted by the motor
control unit 16 is a signal for concurrently turning on the FET 33
20 and the FET 34. In the case where the control signal outputted by
the motor control unit 16 is a signal for concurrently turning on
the FET 33 and the FET 34, it is determined that there exists a
direct-connection abnormality; then, the step S1003 is followed by
the step S1010. In the case where the control signal outputted by
25 the motor control unit 16 is not a signal for concurrently turning
38
on the FET 33 and the FET 34, the step S1003 is followed by the step
S1004.
[0080]
In the case where in the step S1003, the control signal is not
5 a signal for concurrently turning on the FET 33 and the FET 34, the
step S1003 is followed by the step S1004. In the step S1004, it is
determined whether or not the control signal outputted by the motor
control unit 16 is a signal for concurrently turning on the FET 35
and the FET 36. In the case where the control signal outputted by
10 the motor control unit 16 is a signal for concurrently turning on
the FET 35 and the FET 36, it is determined that there exists a
direct-connection abnormality; then, the step S1004 is followed by
the step S1010. In the case where the control signal outputted by
the motor control unit 16 is not a signal for concurrently turning
15 on the FET 35 and the FET 36, the step S1004 is followed by the step
S1005.
[0081]
In the step S1005, it is determined whether or not the control
signal outputted by the motor control unit 16 is a signal for turning
20 on any one of the positive-polarity FETs 31, 33 and 35. In the case
where the control signal outputted by the motor control unit 16 is
a signal for turning on any one of the FETs 31, 33, and 35, the step
S1005 is followed by the step S1006. In the case where all of the
FETs 31, 33, and 35 are off, the step S1005 is followed by the step
25 S1007.
39
[0082]
In the step S1006, it is determined whether or not the control
signal is a signal for turning on any one of the FETs 32, 34, and
36. In the case where the control signal outputted by the motor
5 control unit 16 is a signal for turning on any one of the FETs 32,
34, and 36, it is determined that no abnormality exists; then, the
step S1006 is followed by the step S1008. In the case where the control
signal is a signal for turning off all of the FETs 32, 34, and 36,
it is determined that a wrong-output abnormality exists; then, in
10 the step S1011, the wrong-output abnormality counter C_ng is
incremented; after that, the processing is ended in the step S1019.
[0083]
In the step S1007, it is determined whether or not the control
signal is a signal for turning on any one of the FETs 32, 34, and
15 36. In the case where the control signal is a signal for turning on
any one of the FETs 32, 34, and 36, it is determined that a wrong-output
abnormality exists; then, the step S1007 is followed by the step S1011.
In the case where the control signal is a signal for turning off all
of the FETs 32, 34, and 36, it is determined that no abnormality exists;
20 then, the step S1007 is followed by the step S1008.
[0084]
In the step S1008, the direct-connection abnormality counter
C_shrt is cleared. In the step S1009, the wrong-output abnormality
counter C_ng is cleared. Then, the processing is ended in the step
25 S1019.
40
[0085]
As described above, the case where the motor 61 is a three-phase
AC motor has been explained. Even when the motor is connected with
terminals, the number of which is other than two or three, of the
5 motor driving unit, even when the motor has phases, the number of
which is other than two or three, or even when the motor is not an
AC motor but a DC motor, the control-signal abnormality determination
and the cutoff processing by the cutoff apparatus according to the
present disclosure can be utilized.
10 [0086]
3. Embodiment 3
A motor control apparatus 12 according to Embodiment 3 will be
explained with reference to the drawings. FIG. 11 is a hardware
configuration diagram of the motor control apparatus 12 according
15 to Embodiment 3.
[0087]
FIG. 11 represents a configuration where the cutoff apparatus
7 is added to the motor control apparatus 13 in FIG. 13 according
to the conventional example. The hardware configuration in FIG. 11
20 is different from the conventional example in that the cutoff
apparatus 7 is provided between the motor driving unit 3 and the motor
control unit 17 having the interlock circuit 4.
[0088]
The configuration of the conventional example is not changed
25 but only the cutoff apparatus 7 is added thereto, so that the
41
redundancy of the cutoff function is expanded for an abnormality in
the motor control apparatus. Such a configuration makes it possible
to perform double monitoring with regard to detection of an
abnormality in the motor control apparatus 12 and cutoff of the motor
5 control apparatus 12. As described above, the cutoff apparatus 7 can
additionally be provided without changing the existing motor control
apparatus; thus, this method is very significant because the
redundancy can readily be expanded in a small-scale, lightweight,
and low-cost manner.
10 [0089]
4. Embodiment 4
FIG. 12 is a configuration diagram of an electric power steering
apparatus 150 according to Embodiment 4. In FIG. 12, there will be
explained an example in which the motor control apparatus 10 and the
15 motor 6 are applied to the electric power steering apparatus 150 to
be mounted in a vehicle. The electric power steering apparatus 150
in FIG. 12 is an example of a rack-type electric power steering
apparatus. Even when instead of the motor control apparatus 10, the
motor control apparatus 11 or 12 is utilized in the electric power
20 steering apparatus 150 according to Embodiment 4, the same effect
is provided.
[0090]
When a driver makes the steering mechanism of a vehicle generate
steering torque by means of a steering wheel 151, a torque sensor
25 152 detects the steering torque and then outputs it to the motor
42
control apparatus 10. In addition, a speed sensor 153 detects the
traveling speed of the vehicle and then outputs it to the motor control
apparatus 10. Based on the inputs from the torque sensor 152 and the
speed sensor 153, the motor control apparatus 10 drives the motor
5 6 so as to generate auxiliary torque for supplementing the steering
torque and then supplies it to the steering mechanism of front wheels
154 of the vehicle. In FIG. 1, illustration of the torque sensor 152
and the speed sensor 153 is omitted. It may be allowed that the motor
control apparatus 10 generates auxiliary torque based on inputs other
10 than the inputs from the torque sensor 152 and the speed sensor 153.
[0091]
The motor control apparatus 10 to be applied to an electric power
steering apparatus can suppress itself from being upsized, increasing
its weight, and increasing its cost, while performing effective cutoff
15 processing at a time when an abnormality exists; thus, the motor
control apparatus 10 can contribute to downsizing, weight saving,
and cost reduction of the whole electric power steering apparatus.
[0092]
Although the present application is described above in terms
20 of various exemplary embodiments and implementations, it should be
understood that the various features, aspects and functions described
in one or more of the individual embodiments are not limited in their
applicability to the particular embodiment with which they are
described, but instead can be applied, alone or in various
25 combinations to one or more of the embodiments. Therefore, an
43
infinite number of unexemplified variant examples are conceivable
within the range of the technology disclosed in the specification
of the present disclosure. For example, there are included the case
where at least one constituent element is modified, added, or omitted
5 and the case where at least one constituent element is extracted and
then combined with constituent elements of other embodiments.
Description of Reference Numerals
[0093]
10 3, 39: motor driving unit
4: interlock circuit
5: current detection circuit
6, 61: motor
7, 71: cutoff apparatus
15 10, 11, 12, 13: motor control apparatus
15, 16, 17: motor control unit
31, 32, 33, 34, 35, 36: FET
150: electric power steering apparatus
44
We Claim:
1. A motor control apparatus comprising:
a motor;
a motor driving unit that supplies a current to a motor;
5 a motor control unit that transmits a control signal for
controlling a current to be supplied by the motor driving unit; and
a cutoff apparatus that is disposed between the motor control
unit and the motor driving unit and that cuts off the control signal
transmitted from the motor control unit to the motor driving unit,
10 when the control signal deviates from a predetermined range.
2. The motor control apparatus according to claim 1, wherein the cutoff
apparatus estimates a value of a current that flows in the motor
driving unit, based on the control signal from the motor control unit,
15 and cuts off the control signal, when an estimated current value
exceeds an excessive-current determination value.
3. The motor control apparatus according to any one of claims 1 and
2, wherein the cutoff apparatus estimates a value of a current that
20 flows in the motor driving unit, based on the control signal from
the motor control unit, and cuts off the control signal, when an
average value of estimated current values exceeds an average
excessive-current determination value.
25 4. The motor control apparatus according to any one of claims 1 through
45
3,
wherein the motor driving unit has
two or more positive-polarity switching devices connected
with a positive-polarity side of a DC power source,
5 two or more negative-polarity switching devices connected
with a negative-polarity side of the DC power source, and
an output terminal provided for each connection point at
which one of the positive-polarity switching devices and one of the
negative-polarity switching devices are connected in series with each
10 other, and supplies a current to the motor through the output terminals,
and
wherein when a state where the control signal concurrently turns
on one of the positive-polarity switching devices and one of the
negative-polarity switching devices that are connected in series with
15 each other continues for a time exceeding a determination time, the
cutoff apparatus cuts off the control signal.
5. The motor control apparatus according to any one of claims 1 through
4, wherein the motor control unit further includes an interlock
20 circuit that cuts off the control signal transmitted from the motor
control unit to the motor driving unit, when the control signal
deviates from a predetermined range.
6. The motor control apparatus according to claim 5,
25 wherein the motor driving unit has a current detection circuit
46
for detecting a value of a current flowing in the motor driving unit,
and
wherein the interlock circuit cuts off the control signal, when
the value of the current detected by the current detection circuit
5 exceeds an excessive-current interlock determination value.
7. The motor control apparatus according to any one of claims 1 through
6, wherein the cutoff apparatus cuts off the control signal by use
of a semiconductor switch.
10
8. The motor control apparatus according to any one of claims 1 through
6, wherein the cutoff apparatus cuts off the control signal by use
of a mechanical relay.
15 9. An electric power steering apparatus having the motor control
apparatus according to any one of claims 1 through 8.