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Embedded Die Architecture And Method Of Making

Abstract: Various examples provide a semiconductor package. The semiconductor package includes a substrate having first and second opposed substantially planar major surfaces extending in an x-y direction. The package further includes a bridge die having third and fourth opposed substantially planar major surfaces extending in the x-y direction. The third substantially planar major surface of the bridge die is in direct contact with the second substantially planar major surface of the substrate. The semiconductor package further includes a through silicon via extending in a z-direction through the first substantially planar major surface of the substrate and the fourth substantially planar major surface of the bridge die. The semiconductor package further includes a power source coupled to the through silicon via, a first electronic component electronically coupled to the bridge die, and a second electronic component electronically coupled to the bridge die. The semiconductor package further includes an overmold at least partially encasing the first electronic component, second electronic component, and the bridge die.

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Notices, Deadlines & Correspondence

Patent Information

Application #
Filing Date
25 September 2020
Publication Number
26/2021
Publication Type
INA
Invention Field
ELECTRONICS
Status
Email
ipo@iphorizons.com
Parent Application
Patent Number
Legal Status
Grant Date
2024-12-23
Renewal Date

Applicants

INTEL CORPORATION
2200 Mission College Boulevard, Santa Clara, California 95054, USA

Inventors

1. Sanka Ganesan
11W Canyon Way, Chandler, AZ 85248 (USA)
2. Robert L. Sankman
13202 S 34th Way, Phoenix, AZ 85044 (USA)
3. Sri Chaitra Jyotsna Chavali
4820 West Commonwealth Place, Chandler, AZ 85226 (USA)

Specification

Claims:1. A semiconductor package comprising:
a substrate having first and second opposed substantially planar major surfaces extending in an x-y direction;
a bridge die having third and fourth opposed substantially planar major surfaces extending in the x-y direction, wherein the third substantially planar major surface of the bridge die is in direct contact with the second substantially planar major surface of the substrate;
a through silicon via extending in a z-direction through the first substantially planar major surface of the substrate and the fourth substantially planar major surface of the bridge die;
a power source coupled to the through silicon via;
a first electronic component electronically and a second electronic component at least one of which electronically coupled to the bridge die; and
an overmold at least partially encasing the first electronic component, second electronic component, and the bridge die.
, Description:BACKGROUND
[0001] Microelectronics typically include a central processing unit (CPU). To enhance performance, CPU products are increasingly integrating multi-die into CPU packages in the form of side-by-side or other multi-chip modules (MCMs). Embedded Multi-die Interconnect Bridging (EMIB) is the way to electrically connect multiple dies within a microelectronic package.

BRIEF DESCRIPTION OF THE FIGURES
[0002] The drawings illustrate generally, by way of example, but not by way of limitation, various examples of the present invention.
[0003] FIG. 1 is sectional view of a semiconductor package assembly, in accordance with various examples.
[0004] FIG. 2 is a system level diagram of a system that can include a semiconductor package assembly, in accordance with various examples.

DETAILED DESCRIPTION OF THE INVENTION
[0005] Reference will now be made in detail to certain examples of the disclosed subject matter, examples of which are illustrated in part in the accompanying drawings. While the disclosed subject matter will be described in conjunction with the enumerated claims, it will be understood that the exemplified subject matter is not intended to limit the claims to the disclosed subject matter.
[0006] Throughout this document, values expressed in a range format should be interpreted in a flexible manner to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. For example, a range of “about 0.1% to about 5%” or “about 0.1% to 5%” should be interpreted to include not just about 0.1% to about 5%, but also the individual values (e.g., 1%, 2%, 3%, and 4%) and the sub-ranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the indicated range. The statement “about X to Y” has the same meaning as “about X to about Y,” unless indicated otherwise. Likewise, the statement “about X, Y, or about Z” has the same meaning as “about X, about Y, or about Z,” unless indicated otherwise.

Documents

Application Documents

# Name Date
1 202044041703-US 16724907-DASCODE-9319 [25-09-2020].pdf 2020-09-25
2 202044041703-FORM 1 [25-09-2020(online)].pdf 2020-09-25
3 202044041703-DRAWINGS [25-09-2020(online)].pdf 2020-09-25
4 202044041703-DECLARATION OF INVENTORSHIP (FORM 5) [25-09-2020(online)].pdf 2020-09-25
5 202044041703-COMPLETE SPECIFICATION [25-09-2020(online)].pdf 2020-09-25
6 202044041703-FORM-26 [30-11-2020(online)].pdf 2020-11-30
7 202044041703-FORM 3 [25-03-2021(online)].pdf 2021-03-25
8 202044041703-FORM 18 [27-05-2021(online)].pdf 2021-05-27
9 202044041703-FORM 3 [25-09-2021(online)].pdf 2021-09-25
10 202044041703-FER.pdf 2022-05-18
11 202044041703-OTHERS [19-10-2022(online)].pdf 2022-10-19
12 202044041703-FER_SER_REPLY [19-10-2022(online)].pdf 2022-10-19
13 202044041703-CLAIMS [19-10-2022(online)].pdf 2022-10-19
14 202044041703-ABSTRACT [19-10-2022(online)].pdf 2022-10-19
15 202044041703-US(14)-HearingNotice-(HearingDate-03-12-2024).pdf 2024-11-18
16 202044041703-Correspondence to notify the Controller [19-11-2024(online)].pdf 2024-11-19
17 202044041703-FORM-26 [03-12-2024(online)].pdf 2024-12-03
18 202044041703-Proof of Right [16-12-2024(online)].pdf 2024-12-16
19 202044041703-PETITION UNDER RULE 137 [17-12-2024(online)].pdf 2024-12-17
20 202044041703-Written submissions and relevant documents [18-12-2024(online)].pdf 2024-12-18
21 202044041703-Annexure [18-12-2024(online)].pdf 2024-12-18
22 202044041703-PatentCertificate23-12-2024.pdf 2024-12-23
23 202044041703-IntimationOfGrant23-12-2024.pdf 2024-12-23

Search Strategy

1 202044041703E_17-05-2022.pdf

ERegister / Renewals

3rd: 14 Mar 2025

From 25/09/2022 - To 25/09/2023

4th: 14 Mar 2025

From 25/09/2023 - To 25/09/2024

5th: 14 Mar 2025

From 25/09/2024 - To 25/09/2025

6th: 22 Aug 2025

From 25/09/2025 - To 25/09/2026