Sign In to Follow Application
View All Documents & Correspondence

Embedded Graphics Coding: Reordered Bitstream For Parallel Decoding

Abstract: Reordering of a bitstream is able to be used to speed up the decoding in embedded graphics coding. In the reordering  the signaling bits of all of the groups are sent and then the refinement bits of each group follow. With this reordering  the decoder can decode the header  identify the number of refinement bits for each group and locate the starting point of each group within the bitstream  therefore parallel processing of each group is able to be implemented at the decoder side.

Get Free WhatsApp Updates!
Notices, Deadlines & Correspondence

Patent Information

Application #
Filing Date
03 May 2012
Publication Number
35/2013
Publication Type
INA
Invention Field
COMMUNICATION
Status
Email
Parent Application
Patent Number
Legal Status
Grant Date
2020-03-11
Renewal Date

Applicants

SONY CORPORATION
1-7-1 Konan  Minato-ku Tokyo  Tokyo 108-0075  Japan

Inventors

1. LIU  Wei
1365 Meadow Ridge Cir.  San Jose  California 95131  United States of America
2. GHARAVI-ALKHANSARI  Mohammad
3602 Flora Vista Ave.  #306  Santa Clara  California 95015  United States of America

Specification

What is claimed is:
1. A method of encoding programmed in a controller in a device comprising:
a. generating signaling bits for groups of a bit-plane of an image block;
b. generating refinement bits for each of the groups; and
c. combining the signaling bits to form a header of a bitstream.
2. The method of claim 1 further comprising dividing the image into blocks and
partitioning the blocks into the groups.
3. The method of claim 1 wherein a signaling bit is set to 1 when a group of the groups
contains any disparate pixels.
4. The method of claim 1 wherein the signaling bits are transmitted before the refinement
bits.
5. The method of claim 4 wherein the refinement bits each of the groups is decoded
utilizing parallel processing.
6. The method of claim 1 wherein the device is selected from the group consisting of a
personal computer, a laptop computer, a computer workstation, a server, a mainframe
computer, a handheld computer, a personal digital assistant, a cellular/mobile
telephone, a smart appliance, a gaming console, a digital camera, a digital camcorder, a
camera phone, an iPod®/iPhone, a video player, a DVD writer/player, a Blu-ray®
writer/player, a television and a home entertainment system.
7. A method of decoding programmed in a controller in a device comprising:
a. receiving an encoded bit-plane including signaling bits and refinement bits;
b. determining a quantity of the refinement bits for each group within the
bit-plane; and
c. utilizing the number of the refinement bits to perform parallel decoding of the
bit-plane.
8. The method of claim 7 wherein a maximum number of allowable groups is set to a total
number of groups.
9. The method of claim 7 wherein header bits are utilized for determining the quantity of
the refinement bits for each group.
10. The method of claim 7 further comprising determining if a number of groups reaches a
limit of the groups before decoding the bit-plane, wherein if the number of groups
reaches the limit of the groups, then all of the groups are indicated as having raw
refinement bits and the signaling bit is not sent.
11. The method of claim 7 wherein the device is selected from the group consisting of a
personal computer, a laptop computer, a computer workstation, a server, a mainframe
computer, a handheld computer, a personal digital assistant, a cellular/mobile
telephone, a smart appliance, a gaming console, a digital camera, a digital camcorder, a
camera phone, an iPod®/iPhone, a video player, a DVD writer/player, a Blu-ray®
writer/player, a television and a home entertainment system.
12. An encoder device comprising:
a. a memory for storing an application, the application for:
i. generating signaling bits for groups within a bit-plane;
ii. generating refinement bits for each of the groups; and
iii. combining the signaling bits to form a header of a bit-plane; and
b. a processing component coupled to the memory, the processing component
configured for processing the application.
13. The encoder device of claim 12 wherein the signaling bits are set to 1 when a group of
the groups contains any disparate pixels.
14. The encoder device of claim 12 wherein the application is further for transmitting the
signaling bits before the refinement bits.
15. The encoder device of claim 12 wherein each of the groups is encoded and decoded
utilizing parallel processing
16. A decoder device comprising:
a. a memory for storing an application, the application for:
i. receiving an encoded bit-plane including signaling bits and refinement
bits;
ii. determining a quantity of refinement bits for each group within the
bit-plane; and
iii. utilizing the quantity of the refinement bits for each group to decode the
groups within the bit-plane in parallel; and
b. a processing component coupled to the memory, the processing component
configured for processing the application.
17. The decoder device of claim 16 wherein a maximum number of allowable groups is set
to a total number of groups.
18. The decoder device of claim 16 wherein header bits are utilized for determining the
quantity of the refinement bits for each group.
19. The decoder device of claim 16 the application is further for determining if a number of
groups reaches a limit of the groups before decoding the bit-plane, wherein if the
number of groups reaches the limit of the groups, then all of the groups are indicated as
having raw refinement bits and the signaling bit is not sent.
20. The decoder device of claim 16 the application is further for determining if a number of
groups reaches a limit of the groups, wherein if the number of groups does not reach the
limit of the groups, and the signaling bit equals one, the group is split into two; if the
number of groups does reach the limit of the groups, no group is further split.
21. A system programmed in a controller in a device comprising:
a. a partitioning module for partitioning a block of an image into a plurality of
groups;
b. an encoding module for encoding the groups including generating a signaling
bit and a set of refinement bits for each group, wherein a set of signaling bits is
transmitted before the refinement bits; and
c. a transmitting module for transmitting the encoded bitstream.
22. The system of claim 21 wherein the signaling bit is 1 when a group of the groups
contains any disparate pixels.
23. The system of claim 21 wherein each of the groups is encoded and decoded utilizing
parallel processing.
24. The system of claim 21 wherein the device is selected from the group consisting of a
personal computer, a laptop computer, a computer workstation, a server, a mainframe
computer, a handheld computer, a personal digital assistant, a cellular/mobile
telephone, a smart appliance, a gaming console, a digital camera, a digital camcorder, a
camera phone, an iPod®/iPhone, a video player, a DVD writer/player, a Blu-ray®
writer/player, a television and a home entertainment system.

Documents

Application Documents

# Name Date
1 Translation-Search Report.pdf 2012-05-14
2 Priority Document.pdf 2012-05-14
3 Power of Authority.pdf 2012-05-14
4 Form-5.pdf 2012-05-14
5 Form-3.pdf 2012-05-14
6 Form-1.pdf 2012-05-14
7 Drawings.pdf 2012-05-14
8 3952-CHENP-2012 POWER OF ATTORNEY 15-05-2012.pdf 2012-05-15
9 3952-CHENP-2012 FORM-18 15-05-2012.pdf 2012-05-15
10 3952-CHENP-2012 CORRESPONDENCE OTHERS.. 15-05-2012.pdf 2012-05-15
11 3952-CHENP-2012 FORM-13 24-05-2012.pdf 2012-05-24
12 3952-CHENP-2012 FORM-1 24-05-2012.pdf 2012-05-24
13 3952-CHENP-2012 CORRESPONDENCE OTHERS 24-05-2012.pdf 2012-05-24
14 3952-CHENP-2012 CORRESPONDENCE OTHERS 29-05-2012.pdf 2012-05-29
15 3952-CHENP-2012 ASSIGNMENT 29-05-2012.pdf 2012-05-29
16 3952-CHENP-2012 CORRESPONDENCE OTHERS 25-10-2012.pdf 2012-10-25
17 3952-CHENP-2012 FORM-3 25-10-2012.pdf 2012-10-25
18 3952-CHENP-2012-FER.pdf 2017-05-31
19 3952-CHENP-2012-FORM 3 [16-08-2017(online)].pdf 2017-08-16
20 3952-CHENP-2012-Information under section 8(2) (MANDATORY) [06-11-2017(online)]_2.pdf 2017-11-06
21 3952-CHENP-2012-Information under section 8(2) (MANDATORY) [06-11-2017(online)].pdf 2017-11-06
22 3952-CHENP-2012-OTHERS [27-11-2017(online)].pdf 2017-11-27
23 3952-CHENP-2012-FER_SER_REPLY [27-11-2017(online)].pdf 2017-11-27
24 3952-CHENP-2012-DRAWING [27-11-2017(online)].pdf 2017-11-27
25 3952-CHENP-2012-CLAIMS [27-11-2017(online)].pdf 2017-11-27
26 3952-CHENP-2012-ABSTRACT [27-11-2017(online)].pdf 2017-11-27
27 3952-CHENP-2012-HearingNoticeLetter-(DateOfHearing-14-02-2020).pdf 2020-01-29
28 3952-CHENP-2012-FORM-26 [12-02-2020(online)].pdf 2020-02-12
29 3952-CHENP-2012-Correspondence to notify the Controller [12-02-2020(online)].pdf 2020-02-12
30 3952-CHENP-2012-Form26_General Power of Attorney_24-02-2020.pdf 2020-02-24
31 3952-CHENP-2012-Correspondence_24-02-2020.pdf 2020-02-24
32 3952-CHENP-2012-Written submissions and relevant documents [27-02-2020(online)].pdf 2020-02-27
33 3952-CHENP-2012-PatentCertificate11-03-2020.pdf 2020-03-11
34 3952-CHENP-2012-Marked up Claims_Granted 334310_11-03-2020.pdf 2020-03-11
35 3952-CHENP-2012-IntimationOfGrant11-03-2020.pdf 2020-03-11
36 3952-CHENP-2012-Drawings_Granted 334310_11-03-2020.pdf 2020-03-11
37 3952-CHENP-2012-Description_Granted 334310_11-03-2020.pdf 2020-03-11
38 3952-CHENP-2012-Claims_Granted 334310_11-03-2020.pdf 2020-03-11
39 3952-CHENP-2012-Abstract_Granted 334310_11-03-2020.pdf 2020-03-11
40 3952-CHENP-2012-RELEVANT DOCUMENTS [06-09-2021(online)].pdf 2021-09-06
41 3952-CHENP-2012-RELEVANT DOCUMENTS [14-04-2022(online)].pdf 2022-04-14
42 3952-CHENP-2012-POA [14-04-2022(online)].pdf 2022-04-14
43 3952-CHENP-2012-FORM 13 [14-04-2022(online)].pdf 2022-04-14
44 3952-CHENP-2012-PROOF OF ALTERATION [20-04-2022(online)].pdf 2022-04-20
45 3952-CHENP-2012-PROOF OF ALTERATION [21-09-2022(online)].pdf 2022-09-21
46 3952-CHENP-2012-RELEVANT DOCUMENTS [26-09-2022(online)].pdf 2022-09-26
47 3952-CHENP-2012-RELEVANT DOCUMENTS [11-09-2023(online)].pdf 2023-09-11

Search Strategy

1 search11_31-03-2017.pdf

ERegister / Renewals

3rd: 22 Apr 2020

From 22/11/2012 - To 22/11/2013

4th: 22 Apr 2020

From 22/11/2013 - To 22/11/2014

5th: 22 Apr 2020

From 22/11/2014 - To 22/11/2015

6th: 22 Apr 2020

From 22/11/2015 - To 22/11/2016

7th: 22 Apr 2020

From 22/11/2016 - To 22/11/2017

8th: 22 Apr 2020

From 22/11/2017 - To 22/11/2018

9th: 22 Apr 2020

From 22/11/2018 - To 22/11/2019

10th: 22 Apr 2020

From 22/11/2019 - To 22/11/2020

11th: 16 Nov 2020

From 22/11/2020 - To 22/11/2021

12th: 17 Nov 2021

From 22/11/2021 - To 22/11/2022

13th: 16 Nov 2022

From 22/11/2022 - To 22/11/2023

14th: 20 Nov 2023

From 22/11/2023 - To 22/11/2024

15th: 19 Nov 2024

From 22/11/2024 - To 22/11/2025