FORM 2 THE PATENTS ACT, 1970 (39 of 1970) & THE PATENTS RULES, 2003 COMPLETE SPECIFICATION [See section 10, Rule 13] ERROR CORRECTING DECODING DEVICE AND ERROR CORRECTING DECODING METHOD; PANASONIC CORPORATION, A CORPORATION ORGANIZED AND EXISTING UNDER THE LAWS OF JAPAN, WHOSE ADDRESS IS 1006, OAZA KADOMA, KADOMA-SHI, OSAKA 5718501, JAPAN THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED. DESCRIPTION Technical Field The present invention relates to an error correcting decoding apparatus and an error correcting decoding method using low-density parity check (LDPC) code. Background Art In recent years, LDPC code is becoming a focus of attention as error correcting code that yields high error correcting performance. LDPC code is error correction code defined by a low-density parity check matrix. Since the LDPC code has high error correcting performance and can be easily mounted, the LDPC code is being considered as an error correcting coding scheme for an IEEE802.11n high speed wireless LAN (Local Area Network) system, digital broadcasting system or large-capacity storage apparatus or the like. One example of a conventional LDPC code decoding apparatus is disclosed in Patent Literature 1. The decoding apparatus described in Patent Literature 1 is a decoding apparatus adaptable to a plurality of check matrices and classifies check matrices so that edges are included in a unit region. Here, the "edge" refers to element "1" of a check matrix. In the case of LDPC code in binary notation, elements of a check matrix are "0" or "1." The "elements of a matrix" represent components of the matrix. The decoding apparatus described in Patent Literature 1 stores edge arrangement information of edges located in a classified group and thereby reduces the memory capacity. Furthermore, Patent Literature 1 describes a method of simplifying connections between memory and calculation processors using the edge arrangement information. Citation List Patent Literature PTL 1 Japanese Patent Application Laid-Open No.2007-21 5089 Non-Patent Literature NPL 1 "Low-Density Parity Check Code and Decoding Method" Tadashi Wadayama, Triceps Publishing, June 5, 2002 (PP.92-99) Summary of Invention Technical Problem However, the conventional configuration requires as many calculation processors mounted for a decoding process as row weight x the number of simultaneously processed rows. For this reason, a decoding apparatus adaptable to a plurality of check matrices requires a number of calculation processors that can support a check matrix having the largest row weight, resulting in a problem of increasing the circuit scale. The present invention has been implemented in view of such a problem, and it is an object of the present invention to provide an error correcting decoding apparatus and an error correcting decoding method capable of performing LDPC decoding adaptable to a plurality of code rates while sharing circuits to suppress an increase in the circuit scale. Solution to Problem An aspect of an error correcting decoding apparatus of the present invention is an error correcting decoding apparatus that decodes a coded bit which is subjected to low-density parity check code of a code rate selected from among a plurality of code rates by using a check matrix adaptable to the selected code rate, the apparatus including a storage section that stores a likelihood obtained by receiving the coded bit, a calculation section that calculates a soft decision value by repeating column processing and row processing using the likelihood and a partial matrix corresponding to the check matrix adaptable to the selected code rate, and a decision section that decides the decoded bit using the soft decision value, in which the calculation section uses, when the selected code rate is a first Code rate, a first partial matrix obtained by selecting and combining arbitrary columns from a first check matrix adaptable to the first code rate in accordance with the number of columns to be decoded in the column processing as the partial matrix, and uses, when the selected code rate is a second code rate greater than the first code rate, a distributed partial matrix obtained by selecting and combining arbitrary columns from a distributed check matrix in accordance with a second check matrix adaptable to the second code rate as the partial matrix in accordance with the number of columns making up the first partial matrix, and the distributed check matrix is a matrix in which the number of rows of the second check matrix is expanded so that elements of a row with a great row weight of the second check matrix are arranged to be distributed across the original row and the expanded row. An aspect of an error correcting decoding method of the present invention is an error correcting decoding method for decoding a coded bit which is subjected to low-density parity check code of a code rate selected from among a plurality of code rates by using a check matrix adaptable to the selected code rate, the method including storing a likelihood obtained by receiving the coded bit, calculating a soft decision value by repeating column processing and row processing using the likelihood and a partial matrix corresponding to the check matrix adaptable to the selected code rate, and deciding a decoded bit using the soft decision value, in which when the selected code rate is a first code rate, a first partial matrix selected and combined from a first check matrix adaptable to the first code rate in accordance with the number of columns to be decoded in the column processing is used as the partial matrix, and when the selected code rate is a second code rate greater than the first code rate, a distributed partial matrix selected and combined from a distributed check matrix in accordance with a second check matrix adaptable to the second code rate in accordance with the number of columns making up the first partial matrix is used as the partial matrix, and the distributed check matrix is a matrix in which the number of rows of the second check matrix is expanded so that elements of a row with a large number of row weight of the second check matrix are arranged to be distributed across the original row and the expanded row. According to these aspects of the present invention, it is possible to perform LDPC decoding adaptable to a plurality of code rates while sharing circuits to suppress an increase in the circuit scale. Advantageous Effects of Invention According to the present invention, it is possible to perform LDPC decoding adaptable to a plurality of code rates while sharing circuits to suppress an increase in the circuit scale. Brief Description of Drawings FIG.l is a diagram illustrating an example of a check matrix as a sharing source according to an embodiment of the present invention; FIG.2 is a diagram illustrating an example of a partial matrix as a sharing source in the above embodiment; FIG.3 is a flowchart of a decoding process in the above embodiment; FIG.4 is a diagram illustrating a configuration of main parts of a decoder as a sharing source according to the above embodiment; FIG.5 is a diagram illustrating an example of a check matrix as a sharing target in the above embodiment; FIG.6 is a diagram illustrating an example of a partial matrix as a sharing target in the above embodiment; FIG. 7 is a diagram illustrating an example of a distributed check matrix in the above embodiment; FIG. 8 is a diagram illustrating an example of a distributed partial matrix in the above embodiment; FIG.9 is a flowchart of the decoding process in the above embodiment; FIG.10 is a diagram illustrating a configuration of main parts of a shared decoder according to the above embodiment; FIG.ll is a diagram illustrating another configuration of main parts of a shared decoder according to the above embodiment; FIG.12 is a diagram illustrating a time chart of a decoding process in the decoder shown in FIG.10; FIG. 13 is a diagram illustrating a time chart of a decoding process in the decoder shown in FIG.ll; FIG. 14 is a diagram illustrating a configuration of an LDPC decoding apparatus adaptable to a code rate arbitrarily selected from among a plurality of code rates; and FIG.15 is a diagram illustrating a configuration of an LDPC decoding apparatus adaptable to a first code rate and a second code rate. Description of Embodiments Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. (Embodiment) The present embodiment will describe an error correcting decoding apparatus (hereinafter abbreviated as "decoder") and an error correcting decoding method (hereinafter referred to as "LDPC decoding method or decoding algorithm") capable of performing LDPC decoding adaptable to a plurality of code rates while sharing circuits to suppress an increase in the circuit scale. First, an LDPC decoding method adaptable to a code rate arbitrarily selected from among a plurality of code rates will be described. Decoder 100C shown in FIG. 14 represents a configuration of an LDPC decoding apparatus adaptable to a code rate arbitrarily selected from among a plurality of code rates. Information called "likelihood" obtained from a received signal is inputted to decoder 100C. The likelihood inputted is temporarily stored in likelihood storage section 110. Column processing/row processing calculation section 120 reads the likelihood stored in likelihood storage section 110 and performs a decoding process. Column processing/row processing calculation section 120 outputs extrinsic value 200 which is information obtained in the decoding process. Column processing/row processing calculation section 120 reuses outputted extrinsic value 200 as an input signal. In FIG.14, extrinsic value 200 is once outputted from column processing/row processing calculation section 120, but extrinsic value 200 need not always be outputted, and column processing/row processing calculation section 120 may also internally process extrinsic value 200. Column processing/row processing calculation section 120 repeatedly performs the decoding process (iterative decoding process) using extrinsic value 200 and the read likelihood. After repeating the decoding process a predetermined number of iteration times, column processing/row processing calculation section 120 output a prior value to hard decision section 180. Hard decision section 180 makes a hard decision on the inputted prior value and outputs a decoded bit. Details of the likelihood, extrinsic value 200 and prior value are described in Non-Patent Literature 1. Details of the LDPC decoding method in column processing/row processing calculation section 120 will be described below. FIG.l is a diagram illustrating a check matrix of LDPC code adaptable to a code rate arbitrarily selected from among a plurality of code rates. In FIG. 1, a portion enclosed by a rectangular frame corresponds to a submatrix, and a first check matrix is configured by combining a plurality of submatrices. This submatrix is a matrix resulting from cyclically shifting a unit matrix, and a numerical value enclosed by the rectangular frame in FIG.l represents the amount of cyclic shift of the unit matrix. For example, the amount of cyclic shift "0" at row 0 and column 0 represents the unit matrix itself, and the amount of cyclic shift "9" at row 1 and column 2 represents a matrix resulting from cyclically shifting the unit matrix by 9. On the other hand, "-" represents a zero matrix and is not a matrix resulting from cyclically shifting the unit matrix. A submatrix whose unit matrix has a size of 4x4 and whose amount of cyclic shift is 2 is expressed as shown in equation 1. As is clear from equation 1, a submatrix whose amount of cyclic shift is 2 is a matrix resulting from shifting element "1" of the unit matrix to the right by 2. [1] Hereinafter, a case will be described as an example where the submatrix in the check matrix in FIG.l has a size of 64x64. At this time, for example, a submatrix at row 0 and column 2 is a matrix resulting from cyclically shifting a 64x64 unit matrix to the right by 8, and a submatrix at 2 rows and 3 columns is a matrix resulting from cyclically shifting the 64x64 unit matrix to the right by 12. Since the number of columns of the check matrix in FIG.l is 16, its code length is 16x64=1024 and since the number of rows is 8, its parity length is 8x64 = 512. Thus, its information bit length is 512 bits and the check matrix in FIG.l is a check matrix having a code rate of 1/2 (R=l/2). Although the code rate and the check matrix in the present embodiment are not particularly limited, the present embodiment will be described using the check matrix having the code rate of 1/2 shown in FIG.l as an example. In the present embodiment, LDPC decoding corresponding to a check matrix is not performed on all columns of the check matrix all at once, but performed by dividing all the columns into blocks of a certain number of columns. To be more specific, in the present embodiment, a check matrix is divided into a plurality of submatrices, and a decoding process is performed for each partial matrix. As an example, a case will be considered below where LDPC decoding corresponding to the check matrix in FIG.l composed of 16 columns is performed on four columns at a time. FIG.2 is a diagram illustrating submatrices used when performing a decoding process on four columns at a time. FIG.2 is an example where columns numbered as shown in FIG.l are selected and combined as {0,1,2,3}, {4,5,6,7}, {8,9,10,12} and {11,13,14,15} to form submatrices. In the example shown in FIG.l, a check matrix composed of 16 columns is divided into submatrices each composed of 4 columns. Column number 12 is selected for partial matrix #1-2, and column number 11 is selected for partial matrix #1-3. A criteria for column selection in order to form submatrices from a check matrix is as follows. In the present embodiment, columns are selected from a check matrix to generate submatrices so that row weights of the submatrices is minimized. In FIG. 2, every row weight corresponding to each row of each partial matrix is set to 2 or below. Here, the "row weight" represents the number of elements "1" in each row of a matrix. That is, when the row weight is 2, this represents that two elements "1" exist when the number of elements "1" of the matrix is counted in the row direction. In FIG. 2 is represented that the number of submatrices in which the amount of cyclic shift is described is 2 or below in all rows. When the decoding process is performed on two columns at a time, submatrices are formed by focusing, for example, on column numbers 9, 12 and 13 in the check matrix in FIG.l and by selecting two columns at a time as {0, 1}, (2, 3}, {4, 5}, {6, 7}, {8, 10}, {9, 12}, {11, 14} and {13, 15). It is thereby possible to set the row weights to 1. The setting of the number of columns that make up a partial matrix, that is, the number of columns on which the decoding process is performed collectively will be described later. Thus, in the present embodiment, submatrices are generated from a check matrix by selecting columns so that row weights of the partial matrices is minimized according to the number of columns on which a decoding process is performed, that is, the number of columns making up the submatrix. In the present embodiment, the following decoding process is performed after forming submatrices according to the above-described column selection. A case will be described below where, for example, logarithmic region min-sum decoding is used as the present decoding algorithm. Details of the logarithmic region min-sum decoding can be obtained by referring to Non-Patent Literature 1. In the present embodiment, the logarithmic region min-sum decoding is performed as follows. Table 1 shows definitions of variables used for the present decoding algorithm. [Table 1] Name of variables Notation Details Number-of-times of i Number of times of update update processed in LDPC decoding Row number m (0, 1, .. ., 7 in Row number that FIG.l) identifies submatrix as shown in FIG. 1 Column number n (0, 1, ... ., 15 in Column number that FIG.l) identifies submatrix as shown in FIG. 1 In-submatrix index z (0, 1, .. ., 63 in Number that case of submatrix identifies row or of 64x64) column in submatrix Logarithmic λ(n, z) Logarithmic likelihood ratio likelihood ratio corresponding to LDPC coded bit (logarithmic likelihood ratio corresponding to 1024 ( = 16x64) bits in present embodiment). Corresponds to z-th column of submatrix in n-th column. Output soft decision Λs(n, z) Represented by value defining output soft decision value conesponding to LDPC coded bit, as z-th column of submatrix in n-th column. Output hard decision Λh(n, z) Value resulting from value making hard decision on output soft decision value Logarithmic αmin(i, m, z) Minimum value of extrinsic value ratio absolute value of (extrinsic value logarithmic corresponding to z-th extrinsic value ratio row of submatrix on when extrinsic value m-th row in i-th update processing) is updated a2nd(i, m,z) Absolute value of second smallest logarithmic extrinsic value ratio when extrinsic value is updated aand(i, m, z) Column number of submatrix that provides minimum value of absolute value of logarithmic extrinsic value ratio when extrinsic value is updated α sig(i, m, z) Sign of logarithmic extrinsic value ratio Logarithmic prior β(m, n, z) Logarithmic prior value ratio value ratio corresponding to z-th column of submatrix on m-th row, n-th column βsig(m, n, z) Sign of logarithmic prior value ratio corresponding to z-th column of submatrix on m-th row, n-th column The present decoding algorithm performs column processing based on the unit of the number of columns of a submatrix selected and formed from the check matrix as shown in FIG,2. Furthermore, the present decoding algorithm successively performs row processing using logarithmic prior value ratios obtained as a result of column processing. In the example of FIG.2, the present decoding algorithm performs column processing on every four columns (the number of columns of each partial matrix), four times in total. To be more specific, the present decoding algorithm performs column processing in order of partial matrix #1-0, partial matrix #1-1, partial matrix #1-2, and partial matrix #1-3 shown in FIG.2. Thus, at a time at which the present decoding algorithm has performed column processing on every four columns (the number of columns of each partial matrix), four times in total, column processing using the check matrix shown in FIG. 1 has been updated once. FIG.3 is a diagram illustrating a flowchart of an LDPC decoding process according to the present embodiment. Hereinafter, details of the present decoding algorithm will be described using the flowchart shown in FIG.3. [1] Start After obtaining logarithmic likelihood ratios corresponding to all LDPC coded bits (1024 bits in the present embodiment), the present decoding algorithm starts LDPC decoding. [2] Initial setting (ST101) The present decoding algorithm sets the update processing count as the 0-th time. Furthermore, the present decoding algorithm sets logarithmic extrinsic value ratios corresponding to all m and z in the 0-th update processing as follows. In this algorithm, m indicates the row number when the check matrix is represented by submatrices (subblocks) as shown in FIG.l. Furthermore, z is an index that indicates a row when a submatrix (subblock) selected by m is converted through a cyclic shift on a unit matrix. The logarithmic extrinsic value (extrinsic value) indicates an improvement of decoding reliability of a bit to be decoded in iterative decoding. Referring to min-sum decoding, the logarithmic extrinsic value is an improvement of reliability obtained through row processing performed using a prior value corresponding to any bits other than bits to be decoded. [2] αmin(0, m, z) = 0 ... (Equation 2-1) α2nd(0, m, z) = 0 ... (Equation 2-2) αind(0, m, z) = 0 ... (Equation 2-3) αSig(0, m, z) = 1 ... (Equation 2-4) Furthermore, the present decoding algorithm sets signs of logarithmic prior value ratios for all m, n, z as follows. In this algorithm, n indicates a column number when the check matrix is represented by submatrices (subblocks) as shown in FIG.l. [3] βSin(m,n, z) = 1 ... (Equation 3) [3] i = l (ST102) The present decoding algorithm sets variable i for counting the number of times of update (hereinafter referred to as "update count") to 1. [4] Initialization of extrinsic value (ST103) The present decoding algorithm sets the logarithmic extrinsic value ratio in the i-th update processing for all m and z as follows. [4] αmin(i, m, z) = qtmax-l ... (Equation 4-1) α2nd(i, m, z) = qtmax ..... (Equation 4-2) αind(i, m, z) = 0 ... (Equation 4-3) α sig(i, m, z) = 1 ... (Equation 4-4) where qtmax represents a maximum value in the processing system. [5] j=0 (ST104) The present decoding algorithm sets variable j representing the decoding order to 0. Decoding order j is a number assigned to a partial matrix (set of columns to which the decoding process is applied) as shown in FIG.2. [6] Calculation of prior value (column processing) (ST105) First, the present decoding algorithm obtains input extrinsic value eval (m, n, z1) to column processing corresponding to a partial matrix for all m, n, z0, from the logarithmic extrinsic value ratio obtained in (i-l)-th update processing as follows. [5] esig(m, n, z1) = αsig(i-l, m, z0) x βsig(m, n, z1) ... (Equation 5) where Z is a submatrix size, and S(m, n) is the amount of cyclic shift corresponding to the submatrix on the m-th row, n-th column of the check matrix. Furthermore, Z0 = 0, ..., Z-l and z1 = (S(m, n) + z0) mod Z. Herein, X mod Y represents a remainder of Y divided by X. [6] eabs(m, n, zj) = αmin(i-l, m, z0) (when αind(i-l, m, z0) ≠ n) ... (Equation 6-1) α2nd(i-l, m, z0) (when αind(i-l, m, z0) = n) ... (Equation 6-2) [7] eVa1(m, n, z1) = esig(m, n, zi) x eabs(m, n, z1) ... (Equation 7) However, when S(m, n)= "-," that is, when the submatrix indicated by S(m, n) is a zero matrix, the present decoding algorithm does not calculate the input extrinsic value, where S(m, n) represents the amount of cyclic shift for a submatrix on the m-th row, n-th column of the check matrix. As the in-submatrix index, index zo corresponding to the logarithmic extrinsic value ratio differs from index z\ corresponding to the input extrinsic value because the processing order changes due to the cyclic shift of the submatrix. The present decoding algorithm calculates a logarithmic prior value ratio using the input extrinsic value and the logarithmic likelihood ratio calculated as shown above. The logarithmic prior value ratio is calculated for all m, n, and z as shown in equation 8. [8] where, M represents the number of rows of the submatrix of the check matrix. In equation 8, ∑ is applied to the submatrix except row number m of the submatrix. In equation 8, 0 m indicates a "except row number m." Furthermore, to generate input extrinsic value eval(m, n, z1) in the next update processing, the sign of the logarithmic prior value ratio is updated as shown in equation 9. [9] βsig(m, n, z) = SIGN(β(m, n, z)) ... (Equation 9) where, SIGN(-) is a function that returns a sign. [7] Calculation of extrinsic value (row processing) (ST106) The present decoding algorithm performs successive row processing on a partial matrix made up of a set of submatrices selected as shown in FIG.2. The row processing in min-sum decoding is a calculation that searches for a minimum value. Thus, the present decoding algorithm compares the logarithmic prior value ratio calculated in [6] with the logarithmic extrinsic value ratios calculated so far, searches for a minimum value of the absolute value and updates the logarithmic extrinsic value ratio with the searched minimum value, The present decoding algorithm also calculates a column number that provides a minimum value of the absolute value and a value whose absolute value is the second smallest (hereinafter referred to as "second value") as ones for the aforementioned column processing in the minimum value search. Furthermore, the present decoding algorithm also updates the sign of the logarithmic extrinsic value ratio. The row processing can be expressed by the following equations. [10] where min(.) represents a function that returns a minimum value of the absolute value when the logarithmic prior value ratio corresponding to the column to be decoded is viewed in the row direction. Furthermore, minind(.) represents a function that returns a column number of the submatrix that provides a minimum value of the absolute vaiue, [11] z1 = (S(m, n) + z0) mod Z ... (Equation 11-1) αmin(i, m, z0) = min(αmin(i,m, z0), β min (m, z1)) ... (Equation 11-2) α2nd(i, m, z0) = min2(αmin(i, m, z0), α2nd(i, m, z0), β min(m, z1) ... (Equation 11-3) αind(i, m, z0) = minind(αind(i, m, z0), βind(m, Z1)) ... (Equation 11-4) where min(.) represents a function that returns a minimum value, and min2(.) represents a function that returns a second value. Furthermore, minind(.) is a function that returns βind(m,zi) when min function selects βmin(m, Z1) as the minimum value, and returns αind(i, m, z0) otherwise. [8] j+=l (ST107) The present decoding algorithm increments decoding order j by 1. [9] j<=J (ST108) The present decoding algorithm returns to "[6] Calculation of prior value" to perform column processing when j is equal to or less than last decoding order J or exits the loop when j exceeds J. [10] i+=l (ST109) The present decoding algorithm increments update count i by 1. [11] i