Abstract: In one implementation, the present invention provides a communication of a trip record data from a main controller to a display controller, in case when breaker senses the fault occurrence in the circuit breaker, and thereby saving the same in the display controller’s data flash memory specifically for faults with trip time less than 100ms. In case when the fault is happening at power up (Make ON fault), the present invention takes care of the memory endurance while writing the data in the data flash.
Claims:1. A circuit breaker system for use with electric power lines comprising:
at least one controller adapted to:
generate at least one record on detection of at least one fault, the record comprises at least a tripping protection settings or a timestamp of the occurrence of the fault, or any combination thereof;
transmit the record generated using at least a handshaking line;
at least one display controller adapted to:
receive the record using the handshaking line by simultaneously cancelling the transmission and the reception happening, or clearing the transmit and the receive buffer, or clearing the transmission counters and the reception counters, or any combination thereof at the time of receipt of the record.
2. The circuit breaker system as claimed in claim 1, wherein the display controller is further adapted to validate the record received, preferably, by using a CRC verification technique.
3. The breaker system as claimed in claim 1, wherein the display controller is further adapted to store the record in a memory.
4. The breaker system as claimed in claim 3, wherein the display controller is further adapted to:
check if the memory is free to store the record in the memory; and
erase, if the memory comprises no free space to store the record, at least the pre-existing data in at least one block by:
checking at least the length of the block and/or the length of the record to be stored; and
erasing the memory such that the block will be ready before the next trip record data needs to be written.
5. The breaker system as claimed in claim 4, wherein the display controller comprise a search mechanism to check if the memory is free to store the record in the memory.
6. The breaker system as claimed in claim 4, wherein, before storing the record in the memory, the display controller is further adapted to check endurance of the memory by:
calculating a time gap required between two erase cycles;
calculating a time required between two trip record write;
comparing the timestamp based on the calculated time gap and the time required, wherein
if the time difference between a previous record and present record is less than the time difference required between writing two records in the memory, the record is not stored in the memory; and
if the breaker has tripped because of a new fault then the trip record will be saved irrespective of the timestamp difference.
7. A method of communication between at least one main controller and at least one display controller in a circuit breaker system, the method comprising:
detecting occurrence of at least one fault in the circuit breaker system;
identifying receipt of at least one record from a handshaking line, the record comprises at least a tripping protection settings or a timestamp of the occurrence of the fault, or any combination thereof; thereby
cancelling the transmission and the reception happening, or clearing the transmit and the receive buffer, or clearing the transmission counters and the reception counters, or any combination thereof at the time of receipt of the record.
8. A method of storing at least a record in a memory, during a communication between at least one main controller and at least one display controller in a circuit breaker system, the method comprising:
checking if the memory is free to store the record in the memory; and
erasing, if the memory comprises no free space to store the record, at least the pre-existing data in at least one block by:
checking at least the length of the block and/or the length of the record to be stored; and
erasing the memory such that the block will be ready before the next trip record data needs to be written.
9. The method as claimed in claim 8, further comprises a search mechanism to check if the memory is free to store the record in the memory
10. A method to check endurance of at least one memory before storing the data in the memory, during a communication between at least one controller and at least one display controller in a circuit breaker system, the method comprising:
calculating a time gap required between two erase cycles;
calculating a time required between two write cycles;
comparing the timestamp based on the calculated time gap and the time required, wherein
if the time difference between a previous record and present record is less than the time difference required between writing two records in the memory, the record is not stored in the memory; and
if the breaker has tripped because of a new fault then the trip record will be saved irrespective of the timestamp difference.
, Description:TECHNICAL FIELD
[001] The present subject matter described herein, in general, relates to an apparatus for monitoring an electric power distribution system, and more particularly relates to a power monitoring processor unit which provides circuit protection and which logs overcurrent conditions which may cause the processor to trip the breaker as well as overcurrent conditions existing at the time the breaker is tripped.
BACKGROUND
[002] Protection devices like circuit breakers are used to protect electrical circuitry from damage due to an overcurrent condition, such as an overload, short circuit or instantaneous condition. This functionality is achieved using the trip unit in these protection devices. Trip units are broadly classified as thermo-magnetic and electronic trip unit. Thermo-magnetic includes a bimetal, which heats and bends in response to a persistent overcurrent condition. The bimetal, in turn, unlatches a spring powered operating mechanism, to open the contacts of circuit breaker and break the flow of current.
[003] Electronic trip unit typically makes use of microprocessor to achieve the protection functionality. The long delay trip function protects the load from overloads and/or over current’s. The short delay trip function can be classified into low level short circuit current and high level short circuit current. In case of low level short circuit delay, trip is achieved as per the set trip delay which is typically in the range of 20ms to few hundreds of milliseconds. In case of high level short circuit current, the tripping occurs in the matter of few milliseconds as the current passed is higher than breaker short circuit capacity. The instantaneous trip function protects the electrical conductors to which the circuit breaker is connected from damaging overcurrent conditions, such as short circuits and tripping occurs in half or full cycle of the signal passed.
[004] Electronic trip unit design is illustrated in U.S. Pat. Nos. 4,428,022; and 5,525,985, which include microprocessors, to provide improved performance and flexibility. These digital systems sample the current waveforms periodically to generate a digital representation of the current. The microprocessor uses the samples to execute algorithms, which implement one or more current protection curves.
[005] When diagnosing field issues with protection devices, engineers often rely heavily on hearsay reports of the circumstances surrounding each issue. These reports can come from users, service engineers and sales staff. Assessing the quality of information provided from field reports is often as big a challenge as determining what the original problem may have been. When the pattern of available information is confusing or unclear, then engineers are forced to make very broad guesses as to what the field issue may have been. In these cases, it is often required to send an engineer to a field location for diagnosis of the issue. This can be time consuming, costly and even unproductive if the field issue is not repeatable.
[006] Hence, there is a need of trip record storage in the field for precise recording of the current, voltage, frequency, system settings and other required data for diagnosis of the issue. Storage of these data has some practical limitations. Amount of the data required for diagnosis ranges from few tens of bytes to few hundreds of bytes. The computation of the metering data to be saved in non-volatile memory can take few milliseconds to tens of milliseconds. Also, writing in non-volatile memory will consume some more time. If writing operation is done before tripping, the computation time and writing time adds to the trip time and hence, introduces error in the trip time accuracy. Another way to achieve trip record storage is to issue trip and then start computation and writing in non-volatile memory. The breaker opening time is very less as compared to computation time for parameters and writing them in non-volatile memory. Hence, trip record storage operation will not get completed.
SUMMARY OF THE INVENTION
[007] The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the present invention. It is not intended to identify the key/critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concept of the invention in a simplified form as a prelude to a more detailed description of the invention presented later.
[008] An object of the present invention is to provide a mechanism for saving/storing a reliable trip record without compromising on trip time accuracy.
[009] Another object of the present invention is to achieve a reliable communication and an efficient usage of non-volatile memory in the circuit breakers.
[0010] Accordingly, the present invention disclosed a communication of a trip record data from a main controller to a display controller, in case when breaker senses the fault occurrence in the circuit breaker, and thereby saving the same in the display controller’s data flash memory specifically for faults with trip time less than 100ms. In case when the fault is happening at power up (Make ON fault), the present invention takes care of the memory endurance while writing the data in the data flash.
[0011] In contrast to the existing prior-art techniques, the present invention provides a communication between two controllers, such that the fault sensing, issuing trip command as well as event log generation and trip log generation is done in main controller and data thus generated is transferred to the display controller by a communication means. Then the data is saved in the non-volatile memory of the display controller for future reference. Specifically, the present invention discloses communication and saving of trip records from main controller to display controller for protections with trip time less than 100ms and when make ON fault happens. Also, the present invention is applicable for non-volatile memory which has fixed endurance cycles.
[0012] Other aspects, advantages, and salient features of the invention will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, discloses exemplary embodiments of the invention.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
The above and other aspects, features, and advantages of certain exemplary embodiments of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings in which:
[0013] Figure 1 illustrates a block diagram for electronic trip unit, in accordance with an embodiment of the present subject matter.
[0014] Figure 2 illustrates a SPI communication interface between main controller and display controller, in accordance with an embodiment of the present subject matter.
[0015] Figure 3 illustrates a process of sensing the fault and transmitting the trip log data from the main controller, in accordance with an embodiment of the present subject matter.
[0016] Figure 4 illustrates a process of sensing that main controller is transmitting the trip log data by the display controller and getting ready to receive the same in display controller, in accordance with an embodiment of the present subject matter.
[0017] Figure 5 illustrates a process of finding the data flash location for writing the trip record data and erasing the block if required, in accordance with an embodiment of the present subject matter.
[0018] Figure 6 illustrates an endurance check method calculation and checking of the same before saving the trip records in the flash, in accordance with an embodiment of the present subject matter.
[0019] Persons skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and may have not been drawn to scale. For example, the dimensions of some of the elements in the figure may be exaggerated relative to other elements to help to improve understanding of various exemplary embodiments of the present disclosure. Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
[0020] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of exemplary embodiments of the invention. It includes various specific details to assist in that understanding but these are to be regarded as merely exemplary.
[0021] Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the invention. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness.
[0022] The terms and words used in the following description and claims are not limited to the bibliographical meanings, but, are merely used by the inventor to enable a clear and consistent understanding of the invention. Accordingly, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention are provided for illustration purpose only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.
[0023] It is to be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise.
[0024] By the term “substantially” it is meant that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations or variations, including for example, tolerances, measurement error, measurement accuracy limitations and other factors known to those of skill in the art, may occur in amounts that do not preclude the effect the characteristic was intended to provide.
[0025] Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments and/or in combination with or instead of the features of the other embodiments.
[0026] It should be emphasized that the term “comprises/comprising” when used in this specification is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.
[0027] Traditionally circuit breakers were used to break the current passing through it in case the current goes above a particular threshold. The threshold settings for various protections were done by dip switches or by rotary switches. But with the advancement in electronics field, nowadays the microcontrollers/microprocessors are used for the purpose of fault sensing and giving trip command to the breaker when current exceeds the threshold set by the user. As microcontrollers are being used for fault sensing, hence various types of protections such as current, voltage, frequency, power etc. can be offered in circuit breakers. Also these days circuit breakers are capable of giving current, voltage, frequency, energy metering and can store various records such as trip records which can be referred by the user even after the power down. The circuit breakers are also capable of communicating with SCADA using protocols such as CAN bus and MODBUS.
[0028] As the microcontroller based electronic trip unit provides all the above mentioned features, they may use more than one microcontroller for performing the operations listed above. For example, one microcontroller may be used to perform breaker critical operations such as fault sensing, giving trip command to the breaker in case of fault, generating trip records, calculating metering data etc. Whereas another microcontroller may be used for providing user interface such as display navigation. Display navigation can be used to view/change various protection settings, view trip record data, metering data etc. Since, data is generated in main controller; it needs to be communicated to the display controller so that user can view various parameters as and when required. Also, parameters such as protection settings or trip record can be viewed by the user even after power down. Hence, there may be an option of powering up the controllers on battery power.
[0029] The electronic trip unit or ETU is the intelligent part of the circuit breakers which senses the fault and issues the trip command. With many protections being offered, it becomes important to store the trip records in case of breaker tripping so that the user can view the reason of trip and resolve the fault that led to breaker tripping. In general the trip time of various protections may vary from 20ms in case of a short circuit fault to few seconds in case of overload fault. Since these trip records can be viewed by the user even after the power down , hence these records are in general written in the non-volatile memory of the controller such as data flash. The flash memories generally allow the reading and writing of the data according to the user defined size of bytes. However, before undertaking writing operation, data already stored in the flash needs to be erased. This erase operation is generally a block wise operation (512 bytes/1024 bytes). Also the data flash memory in general has fixed endurance that is the number of times data flash memory can be erased is usually fixed. After this, the data flash memory becomes corrupt.
[0030] The present invention provides a mechanism for communicating the trip record data from main controller to display controller in case when breaker senses the fault and saving the same in the display controller’s data flash memory specifically for faults with trip time less than 100ms and in case when the fault is happening at power up (Make ON fault). The present invention also takes care of the memory endurance while writing the data in the data flash.
[0031] Referring now to figure 1, a basic block diagram of electronic trip unit with main controller is illustrated. When current is passed through the circuit breaker, the current output is available at secondary of current transformer 1 and voltage output is available at output of Rogowski coil 2. The current transformer output is given to power supply module 4 and the Rogowski output is given to signal conditioning module 3. The signal conditioning module has certain AC gain and DC gain. The power supply is also made available to flux shift device (FSD) 6 through trip circuit 5. The power supply signal is passed through regulator 7 and used for powering the main controller 8.
[0032] A main controller here senses the fault and issues trip command when current goes above a certain threshold. User interface for changing settings, viewing trip record, viewing metering data is provided by the display controller. Since the data is generated in main controller, this data needs to be communicated to the display controller (as shown in figure 2) as and when the data changes or the data can be queried by the display controller as and when required to be refreshed on the display screen. The communication between main controller and display controller may be based on SPI/I2C protocol.
[0033] It may be understood that, the present invention in general discusses about SPI protocol throughout the description, however, any other protocol may be used for communication purpose. The SPI protocol uses 4 wires (MISO, MOSI, Clock, and Slave select). Also, the SPI protocol is based on master and slave communication. Here, the main controller is the master and display controller is the slave. Since, the main controller is the master, hence clock for communication is controlled by the main controller. The same is shown in figure 2. The frame for communication between main controller and display controller may consist of a fixed format which can have a start of frame, data, CRC for data validation and an end of frame.
[0034] In one implementation, when the main controller detects a fault, it generates the trip record along with the tripping protection settings and timestamp and makes the frame as per the communication frame format. Now, this frame needs to be communicated to the display controller and saved in its data flash memory before power down happens that is less than 10ms. Hence, it is important that slave controller is in ready state to receive the data before master controller starts transmission. To achieve this purpose, the present invention provides / discloses a handshaking line to be used such that when master wants to transmit the trip record data this line is set high, as shown in figure 3. As the slave device that is display controller detects that line is set high by the master, it cancels all the transmission and reception happening at that time. It also clears transmit and receive buffer and the transmission and reception counters used for communication purpose. Then the slave configures itself for reception of trip record data from master. Same process is explained in figure 4. The master simultaneously performs the similar process at its end and also configures itself for transmitting the trip record data. The master resets the handshaking line and starts transmission of the data.
[0035] When the complete trip record frame is received in the display controller, display controller switches to battery power mode for saving the data in the data flash memory. The flash memories generally allow the reading and writing of the data according to the user defined size of bytes. However, before undertaking writing operation, data already stored in the flash needs to be erased. This erase operation is generally block wise (512 bytes/1024 bytes). Thus the data, once written in flash memory, if requiring modification, cannot be simply overwritten on the existing data. The process of erase is usually time taking and may require 10-300ms for erasing entire block depending upon the operating frequency of controller. Then writing the data may further require 5-50ms depending upon data length. If the display controller remains ON for longer time to save the data, faster will be the battery drainage. Hence it is required that at the time of saving the data, the block is already ready for writing.
[0036] In order to address the above issues, the present invention provides a method to take care of the block erase such that the block is always ready for writing the trip record data. The present invention allows calculation of the maximum number of trip records that can be stored in a block according to the length of the block and length of the data to be stored. Also more than one block of data flash are used for storing the data such that when a particular block is full, the data can be written to next block. The present invention also confirms in a block total number of trip records that are written must be greater than the total number of trip records that user can view. Thus the erase of the block, according to the present invention, will be required only when all the blocks are full and also the user will be able to see previous records data.
[0037] The present invention uses a search mechanism in which at power up of the controller the blocks are checked for presence of data. If first block is empty, then new record will be written in the first block. If first block is completely filled, then second block will be checked. If second block is empty then new data can be written in second block. In cases, when two blocks are being used for writing the trip log data and one block is completely filled and in second block also only one more record can be updated, in such case block one will be completely erased at power up. Thus the block will be ready before the next trip record data needs to be written. This process is explained in figure 5.
[0038] As discussed above, the data flash memory in general have a fixed endurance that is the number of times data flash memory can be erased is usually fixed. After this, the data flash memory becomes corrupt. This endurance may also vary from 30,000 erase cycles to 10, 00,000 depending upon the type of non-volatile memory. In some cases, due to faulty conditions such as breaker not opening in case of a fault though trip command is being given, the controller will reset continuously because the fault being persistent. This condition will generate the trip records continuously and if the trip time is of the order of 20ms, then a trip record will be generated every 20ms. This continuous writing and erasing will lead to data flash corruption. Hence in order that the memory endurance of the controller last till the product life of the breaker, it is important to avoid repetitive trip record writing of same fault in turn reducing the number of times the data flash is getting erased.
[0039] In order to address the above issue, the present invention also provides a method to calculate the time gap required between two erase cycles, in turn calculating the time required between two write cycles. In case, the breaker trips in the same fault such that the time difference between previous record and new record is less than the time difference required between writing two records in data flash memory, the new record will not be saved. However, if the breaker has tripped because of a new fault then the trip record will be saved irrespective of the timestamp difference as explained in figure 6. Thus, the method to calculate the time gap required between two erase cycles, will ensure that the data flash memory is intact for the entire product life and is not corrupted because of frequent erasing of data flash.
[0040] Apart from what is discussed above, some other benefits and/or technical advantages of the present invention are as provided below:
i. The present invention stores reliably trip record for trip that occurs in less than 100ms in case of faults that occur at power up as well as run time.
ii. The present invention stores the detailed trip log including metering parameters and system parameters without compromising on trip time accuracy.
iii. The present invention provides a reliable communication of trip record data from main controller to display controller before the power down occurs and saving the record in display controller’s data flash on battery power.
iv. The present invention provides repeated trip record writing of same fault in data flash is avoided by additional check added for memory writing. This ensures data flash endurance remains intact for entire product life.
v. The present invention provides an efficient method of checking the presence of empty block of data flash for writing trip log and erasing the block if the block is already filled to ensure that during tripping, trip log saving time is reduced.
vi. The present invention provides a reliable saving of fault record in electronic trip unit of circuit breakers.
[0041] It may be clearly understood by a person skilled in the art that for the purpose of convenient and brief description, for a detailed working process of the foregoing system, devices, and unit, reference may be made to a corresponding process in the foregoing device/apparatus embodiments, and details are not described herein again.
[0042] In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus, and device may be implemented in other manners. For example, a plurality of units or components or mechanisms may be combined or integrated into another system, or some features may be ignored or not performed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections may be implemented through some interfaces. The indirect couplings or communication connections between the apparatuses or units may be implemented in electronic, mechanical, or other forms.
[0043] The various mechanisms described as separate parts may or may not be physically separate, and the parts displayed as mechanisms may or may not be physical units, may be located in one position, or may be distributed at various location of the device. Some or all of the units may be selected to achieve the objective of the solution of the embodiment according to actual needs.
[0044] In addition, the mechanisms in the embodiments of the present invention may be integrated into one processing unit, or each of the mechanisms may exist alone physically, or two or more mechanisms may be integrated into one mechanism.
[0045] Although an event recording of critical fault in limited time space disclosed, it is to be understood that the embodiments disclosed in the above section are not necessarily limited to the specific features or methods or devices described. Rather, the specific features are disclosed as examples of implementations of the event recording of critical fault in limited time space.
| # | Name | Date |
|---|---|---|
| 1 | Power of Attorney [31-03-2016(online)].pdf | 2016-03-31 |
| 2 | Form 3 [31-03-2016(online)].pdf | 2016-03-31 |
| 3 | Form 18 [31-03-2016(online)].pdf | 2016-03-31 |
| 4 | Drawing [31-03-2016(online)].pdf | 2016-03-31 |
| 5 | Description(Complete) [31-03-2016(online)].pdf | 2016-03-31 |
| 6 | Other Patent Document [20-05-2016(online)].pdf | 2016-05-20 |
| 7 | 201621011236-FORM 1-(24-05-2016).pdf | 2016-05-24 |
| 8 | 201621011236-CORRESPONDENCE-(24-05-2016).pdf | 2016-05-24 |
| 9 | Abstract.jpg | 2018-08-11 |
| 10 | 201621011236-FER.pdf | 2019-10-23 |
| 11 | 201621011236-ABSTRACT [16-04-2020(online)].pdf | 2020-04-16 |
| 11 | 201621011236-OTHERS [16-04-2020(online)].pdf | 2020-04-16 |
| 12 | 201621011236-CLAIMS [16-04-2020(online)].pdf | 2020-04-16 |
| 12 | 201621011236-FER_SER_REPLY [16-04-2020(online)].pdf | 2020-04-16 |
| 13 | 201621011236-CLAIMS [16-04-2020(online)].pdf | 2020-04-16 |
| 13 | 201621011236-FER_SER_REPLY [16-04-2020(online)].pdf | 2020-04-16 |
| 14 | 201621011236-ABSTRACT [16-04-2020(online)].pdf | 2020-04-16 |
| 14 | 201621011236-OTHERS [16-04-2020(online)].pdf | 2020-04-16 |
| 15 | 201621011236-FER.pdf | 2019-10-23 |
| 15 | 201621011236-PA [18-01-2021(online)].pdf | 2021-01-18 |
| 16 | 201621011236-ASSIGNMENT DOCUMENTS [18-01-2021(online)].pdf | 2021-01-18 |
| 16 | Abstract.jpg | 2018-08-11 |
| 17 | 201621011236-8(i)-Substitution-Change Of Applicant - Form 6 [18-01-2021(online)].pdf | 2021-01-18 |
| 17 | 201621011236-CORRESPONDENCE-(24-05-2016).pdf | 2016-05-24 |
| 18 | 201621011236-FORM 1-(24-05-2016).pdf | 2016-05-24 |
| 18 | 201621011236-FORM-26 [09-08-2021(online)].pdf | 2021-08-09 |
| 19 | Other Patent Document [20-05-2016(online)].pdf | 2016-05-20 |
| 19 | 201621011236-Response to office action [15-06-2022(online)].pdf | 2022-06-15 |
| 20 | Description(Complete) [31-03-2016(online)].pdf | 2016-03-31 |
| 20 | 201621011236-US(14)-HearingNotice-(HearingDate-26-07-2023).pdf | 2023-07-10 |
| 21 | Drawing [31-03-2016(online)].pdf | 2016-03-31 |
| 21 | 201621011236-Correspondence to notify the Controller [24-07-2023(online)].pdf | 2023-07-24 |
| 22 | 201621011236-Written submissions and relevant documents [10-08-2023(online)].pdf | 2023-08-10 |
| 22 | Form 18 [31-03-2016(online)].pdf | 2016-03-31 |
| 23 | 201621011236-PatentCertificate12-10-2023.pdf | 2023-10-12 |
| 23 | Form 3 [31-03-2016(online)].pdf | 2016-03-31 |
| 24 | 201621011236-IntimationOfGrant12-10-2023.pdf | 2023-10-12 |
| 24 | Power of Attorney [31-03-2016(online)].pdf | 2016-03-31 |
| 1 | TPOSEARCHSTRATEGY13_23-10-2019.pdf |
| 2 | SEARCHSTRATEGYAMD201621011236AE_28-04-2020.pdf |