This invention relates to FDAU Processor Module (FPM) for use in Data
Acquisition System (DAS) of Flight Data Recorders and, more particularly, to fight data
acquisition systems for receiving & processing fight data signals in a variety of signal
forms like Analog, Synchro, Discrete, Frequency & Ratio metric (OAT Signals) and
sending to DRU after Harvard Bi-Phase Conversion.
BACKGROUND OF THE INVENTION
Flight data recorders are monitoring and recording instruments, carried aboard
an aircraft, which systematically monitor and store the instantaneous values of various
aircraft parameters. Early recorders were analog electromechanical devices which
periodically marked, in analog form, the value of a given airplane parameter on a
moving wire or other permanent storage medium. The time of occurrence of the
parameter was also suitably scribed into the medium opposite the mark for the sensed
parameter. Subsequently, digital flight data recorders have been developed which
operate by converting each analog aircraft parameter into a corresponding digital signal,
and storing the digital signals on a permanent storage medium such as magnetic tape.
The numerous mechanical parts employed in the analog and digital type
electromechanical flight data recorders have rendered such units expensive to construct
and bulky in design, requiring periodic maintenance of the mechanical parts. In addition,
extraction of the stored data from these data recorders requires physical removal of the
storage medium.
The development of solid state memory devices, such as electrically erasable
read-only memory, has led to the design of all solid state flight data recorders. The solid
state flight data recorders commonly employ a data acquisition system (DAS) which
receives and processes the various aircraft input signals to be monitored and stored
under the control of a central processing unit (CPU). The analog signals are converted
to digital signals by the DAS and, under CPU control, are passed over a data bus to the
solid state memory devices. Programming within the CPU controls the processing of
input airplane signals to corresponding digital signals through the DAS and the
subsequent transference of these digital signals to controlled locations in the solid state
memory.
Annexure‐II
The signals representative of monitored aircraft parameters are typically either
discrete level signals or analog signals. Discrete signals are typically switch positions
and produce either a high or a low level output depending upon the status of the
particular switch. A typical example in an aircraft is a squat switch, which indicates
whether or not a load is being borne by the landing gear.
SUMMARY OF PRESENT INVENTION
The present invention, therefore, is directed to FDAU Processor Module (FPM) of
data acquisition system for use in a Flight data recorder.
An aspect of the present invention is the ability of the data acquisition system to
process a set of parameter sense signals in response to a single CPU request. In this
way, integrity of multiple signal sensor data is assured and overhead on CPU operation
is reduced.
A further aspect of the invention is the universal application of the present data
acquisition system. All aircraft parameter signals may be assigned to any of the multiple
data acquisition system inputs under CPU control. Further, the FPM is responsive to
CPU control to vary the scaling applied to each input signal. Briefly, according to the
invention, FPM module for an aircraft flight data recorder is responsive to a central
processor unit (CPU) for selectively processing a plurality of input signals.
The FPM is designed around the highly integrated 32-bit Motorola microcontroller.
It supports a memory address space of 16MB. The FDAU Processor Module
is designed to support SRAM and FLASH memory. An operating frequency of 16MHz is
chosen for the micro-controller, which is primarily driven by the choice of cost effective
mini ACE, to provide MIL-STD 1553-B data bus interface. A NVRAM and MIL-STD
1553-B RT’s memory is also mapped on to the micro-controller’s memory space. The
micro-controller’s on-chip BDM interface support is extended on to the front of the PCB
to enable hardware/software development.
Memory devices chosen have an access time of 70 ns or lesser. The card
provides the necessary support for in-situ programming of the Flash memory.
A dedicated Watchdog is used and it has to be triggered periodically by software
to avoid occurring of Watchdog Timeout event.
Annexure‐II
An inter-card interconnect bus called system bus is formed using the address,
control, data & I/O port lines of the micro-controller namely: Address lines, Read/write
lines, Off-Board Latch signal, Data lines and I/O Select lines.
A mini ACE 1553-B RT device is used to support communication over the MILSTD
1553-B data bus interconnects. This device sits directly on to the micro-controller’s
bus. The Channel ‘A’ and Channel ‘B’ signals of the mini ACE device are interfaced to
the MIL-STD 1553-B bus through a pair of pulse transformers. The RT address lines are
accessible externally, so that the address can be easily configured.
The card also supports a serial ARINC-717 interface, which can be programmed
for various pre-determined data rates.
Additionally, an RS-232 serial asynchronous interface is provided to enable
communication with a Host PC. This link may be used for debugging as well as
downloading application software.
The heart of the system is Motorola's 32-bit micro-controller. The main function of
the micro-controller is to acquire sensor data and send the same to DRU.
The major building blocks of the card are:
• Micro-controller
• FLASH Memory to store program and constants
• SRAM Memory to provide data/program storage
• NVRAM Memory to store nonvolatile data
• 1553-B RT Mini ACE to provide MIL-STD 1553-B data bus interface
• CPLD to provide glue logic and Harvard Bi-phase encoding
• RS-232 serial asynchronous interface to HOST
• ARINC-717 Interface to transmit sensor data
• Watchdog timer to overcome forever loops situation
• supervisory circuit to provide highly reliable reset to the system
Annexure‐II
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the present invention will become more apparent
and descriptive in the description when considered together with figures/flow charts
presented:
Figure 1: is a Block Diagram of FDAU Processor Module (FPM)
Figure 2: is a Block Diagram of Micro controller Interface with Flash Memory
Figure 3: is a Block Diagram of Micro Controller Interface with SRAM
Figure 4: is a Block Diagram of Micro Controller Interface to NVRAM
DETAILED DESCRIPTION
The FDAU Processor Card is the core of the FDAU. It acquires Analog,
Frequency, Discrete, and Synchro signals through other I/O Cards in the FDAU. These
I/O cards are interfaced with the processor’s data, address and control bus, which are
brought out on the PCB edge connector. The processor card also exchanges certain
data and configuration parameters through the MIL-STD 1553-B and transmit these
data along with acquired a/c data (Analog, Discrete, Frequency & Synchro) to DRU
through ARINC717 Interface. Detail description of all electronics interfaces used in FPM
is described in succeeding paragraph:
CPU:
The CPU module is designed based on Motorola Micro controller, which operates
at 16 MHz. The Motorola Quad Integrated Communication Controller is a versatile one
chip integrated microprocessor with peripheral combination.
MEMORY:
Memory is provided using single 16-bit devices. FLASH EPROM is provided for
code memory for application program and constants. The device used for Code
memory, which require 5V single supply. The device has access time as fast as 70ns.
The device features top boot and bottom configuration. The device can be in-circuit
programmable.
Static RAM is provided for data memory. Data memory is used for storage of
dynamic data, during the execution of the application program. It is also used for
downloading test and debugging programs during development phase. The memory is
provided with access time as 55 ns.
The Non-volatile memory required for storing the sorties is provided which is
organized with access time 45 ns Speed.
Annexure‐II
SERIAL PORTS:
The Serial ports are provided using the internal communication ports of the
processor, as UART ports. The interfaces are provided using the standard interface
devices for RS-232 interfaces.
MIL-STD-1553 INTERFACE:
The MIL-STD-1553 interface is provided to configure it for RT / BC / MT, as
required. It is highly integrated ACE, in terms of space and power consumption. The
device is operated at 16MHz. This device supports flexible processor/ memory
interface.
INTERRUPTS:
The module provides seven interrupt inputs using the externally connected
interrupts of the CPU. These pins are prioritized interrupt request lines. These interrupts
are synchronized and de-bounced by input circuitry on two consecutive rising edges of
the processor clock.
• One interrupt is from Arinc717,
• One from 1553 device,
• One from Analog & Synchro Board
• One from Frequency & Discrete Board
DECODING LOGIC:
Control logic, Memory decoding, on board I/O decoding are implemented using
Cypress CPLD’s. This controls the bus access cycle and read – write operations for
memory and I/O devices. Glue Logic for Bi Phase data Frame generation &
synchronization for Arinc 717 is also implemented.
BUS EXPANSION:
The module provides 16-bit bus expansion with required control signals for
interfacing with other IO cards using buffer devices.
POWER SUPPLY
The module required +5VDC power supply for operation. On-board bypass
capacitors are provided on each power supply line.

WE CLIAMS:-
Accordingly, the description of the present invention is to be considered as illustrative only and is for the purpose of teaching those skilled in the art of the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and exclusive use of all modifications which are within the scope of the appended claims is reserved. The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. FDAU Processor Module (FPM) for an aircraft flight data recorder responsive to a central processor unit (CPU) for processing a plurality of input signals to provide a digitally encoded signal representative of a selected set of input signals each time the CPU provides a simple command signal, said digitally encoded signal being used by said CPU for generation of recorded flight data information, said data acquisition system comprising:
Multiplexing means for outputting said selected set of said input signals, each selected input signal set being output responsive to a corresponding address command signal;
Logic means responsive to said single command from said CPU for producing each address command signal; and
Processing means for processing each signal in a selected signal set to supply said digitally encoded signal representative of said selected set of input signals.

2. The FPM of claim 1, wherein said processing means comprises: gain controlled amplifier means responsive to gain control command signals from said CPU for amplifying each signal in a selected signal set by a predetermined gain factor; Controller means for pre-determinedly coupling the instantaneous value of each signal in the selected signal set to the input of said analog-to-digital converter means; and means for supplying said corresponding signals at the output of said analog-to-digital converter means as said digitally encoded signal representative of said selected set of input signals.

3. The FPM of claim 2, wherein said controller means produces an interrupt signal to said CPU upon all the signals in a selected signal set being stored in said digital memory means.

4. The FPM of claim 4, wherein said logic means responds to a single CPU command signal to:

(a) produce a predetermined address command signal such that said multiplexing means outputs said set of selected input signals,

(b) produce predetermined gain control command signals such that each signal in a selected signal set is amplified by a predetermined gain factor, and

(c) Activate said controller means such that the analog-to-digital converted instantaneous value of each signal in a selected signal set is loaded into said digital memory means.

5. A FPM for an aircraft flight data recorder of the type that selectively records flight data information, said FPM being responsive to a central processor unit (CPU) for selectively processing multiple input signals and supplying to said CPU for utilization in selective recording of flight data information a digital signal representative of a selected set of said input signals.

6. The FPM of claim 4, further comprising: digital memory means for storing each analog-to-digital converted instantaneous value of a signal in a selected signal set; and wherein said controller means produces an interrupt signal to said CPU upon all of the analog-to-digital converted signals in a selected signal set being stored in said digital memory means.

7. The FPM of claims 7, further comprising: logic means responsive to a single CPU command signal for:
(a) Producing said address command signals applied to said multiplexing means for selection of said selected sets of selected input signals,
(b) producing said applied gain control command signals such that each signal in a selected signal set is amplified by a predetermined gain factor, and
(c) Activating said controller means such that the analog-to-digital converted instantaneous value of each signal in a selected signal set is loaded into said digital memory means.

8. A FPM as claimed in any of the preceding claims wherein a dedicated watchdog is used and it has to be triggered periodically by software to avoid occurring of Watchdog Timeout event.

9. A FPM as claimed in any of the preceding claims wherein an RS-232 serial asynchronous interface is provided to enable communication with a Host PC, wherein a serial ARINC-717 interface, which can be programmed for various pre-determined data rates.

10. A FPM as claimed in any of the preceding claims wherein a CPLD is used to provide glue logic and Harvard Bi-phase encoding, wherein a mini ACE 1553-B RT device is used to support communication over the MIL-STD 1553-B data bus interconnects. The RT address lines are accessible externally, so that the address can be easily configured, A FPM as claimed in any of the preceding claims wherein a supervisory circuit is used to provide highly reliable reset to the system. ,TagSPECI:As per Annexure-II