FIELD OF THE INEVNTION
[001] The present invention is generally related to hardware processing engines. More
particularly, the present invention relates to field programmable gate array based
hardware processors for digital/numerical relays for power and data transmission lines.
BACKGROUND OF INVENTION
[002] Existing power and data transmission relays are based on microcontrollers or
digital signal processors. The relays importantly are used for sensing, processing and
communicating data in modern power and data communication systems. These
microprocessors/ microcontrollers and digital signal processing (DSP) processors are
inherently sequential in nature. While performing these tasks viz, sensing data,
processing the data and communicating result of processing the data are executed one
after the other. Subsequent data set is sensed only after the previous data set has
completed all the three tasks of sensing, then processing and finally communicating the
result. This sequential process effectively reduces sample rate of the parameters being
sensed. Consequently, the sequential process increases time of executing all the three
tasks on a data set, and also affects the performance of the relay.
[003] Further, the present technologies have also provided field programmable gate
array (FPGA) based relays for many protection functions, metering, and self-test
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functions and power and data transmission. But these FPGA based relays reported in the
literature also are designed for sequential operation only.
[004] Therefore, there is a need for an improved hardware processing engine for digital
relays which may reduce the overall computation time of process executed by the relay
and improves the performance of the relay.
SUMMARY OF THE INVENTION
[005] It is an objective of the present invention to provide an improved hardware
processing engine based on FPGA for digital relays which can execute sensing,
processing and communicating of data concurrently, for reducing computational time and
improving performance of the relays.
[006] An objective of the present invention is to provide the hardware processing engine
for multiple relay functionality in a single device, viz., overcurrent IDMT relay, distance
relay, impedance relay, Mho Relay and Reactance relay.
[007] Yet another objective of the present invention is to prevent the tendency of the
relay to trip for transient faults by isolating fundamental component of current and
voltage using IP cores for implementing Fast Fourier Transform and Inverse Fast Fourier
Transform algorithms in digital hardware.
[008] Another objective of the present invention is to provide the hardware processing
engine with data communication facility for implementing special protection schemes.
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BRIEF DESCRIPTION OF DRAWINGS
[009] For a better understanding of the embodiments of the systems and methods
described herein, and to show more clearly how they may be carried into effect,
references will now be made, by way of example, to the accompanying drawings,
wherein like reference numerals represent like elements/components throughout and
wherein:
[0010] Fig. 1 illustrates an exemplary environment of schematic diagram of the relay of
the present invention in a transmission line, in accordance with an embodiment of the
present invention; and
[0011] Fig. 2 illustrates an exemplary embodiment including sensing module, the
processing module and the communicating module based on the FPGA board of the
relay, in accordance with an embodiment of the present invention; and
[0012] Fig. 3 illustrates a flowchart showing a method of implementing a digital relay on
an FPGA board with the hardware processing module including sensing module,
processing, and communicating module concurrently working for the digital relay, in
accordance with an embodiment of the present invention.
DETAILED DESCRIPTION OF INVENTION
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[0013] This patent describes the subject matter for patenting with specificity to meet
statutory requirements. However, the description itself is not intended to limit the scope
of this patent. The principles described herein may be embodied in many different forms.
[0014] Illustrative embodiments of the invention now will be described more fully
hereinafter with reference to the accompanying drawings, in which some, but not all
embodiments of the invention are shown. Indeed, the invention may be embodied in
many different forms and should not be construed as limited to the embodiments set forth
herein; rather, these embodiments are provided so that this disclosure will satisfy
applicable legal requirements. Like numbers refer to like elements throughout.
[0015] The present invention provides an FPGA based hardware processing engine for
digital relays for transmission lines. In an embodiment, the hardware processing engine
or hardware processor engines are implemented in multiple functional relays for electric
transmission lines such as power and data transmission. The hardware processing engine
may comprise a sensing module, a processing module and a communicating module
which perform their respective functions of sensing, processing and communicating data
concurrently, resulting in faster overall relaying process. The sensing module transfers a
data set after sensing, to the processing module, and starts sensing a next data set, while
the processing module concurrently works on the sensed data set received from the
sensing module.
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[0016] In the same way, the processing module transfers a processed data set to the
communicating module, and immediately receives the sensed data set from the sensing
module, which is again transferred after processing to the communicating module, for the
communicating module to communicate the result of the processed data further to an end
device, such as a laptop/PC or the like. After transferring the processed data to the
communicating module, the processing module concurrently performs processing of a
next sensed data set received from the sensing module, while the communicating module
concurrently transfers the result of the processed data to the end device.
[0017] Thus all the three modules of the FPGA based hardware processing engine of the
digital relays in the present invention perform their respective functions concurrently, and
not sequentially. This is because the three modules are arranged in a parallel pipeline
configuration. The present invention also provides multiple relay functionality
concurrently in a single device, viz., for an example overcurrent IDMT relay, Distance
Relay, Impedance relay, Mho Relay and Reactance relay.
[0018] Fig. 1 illustrates an exemplary environment of schematic diagram of the relay of
the present invention in a transmission line, in accordance with an embodiment of the
present invention. The exemplary embodiment 100 includes a hardware simulator for
transmission line, such as 360Km transmission line. The hardware simulator 102 includes
a generator section 104 for generating data signals to be transmitted along sections of
transmission line 106 till a load section 108, via a sampling module 110 that samples the
generated signals for creating rectified samples of voltage and current. The rectified
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samples are then sent to an analog to digital signal converter 112. In an embodiment, the
analog to digital signal converter (ADC) is a 112 PMOD 12 bit Dual Channel ADC.
[0019] From the ADC 112, the converted digital signal is passed to the FPGA board 114,
of the present invention on which a digital relay 116 is provided, to further communicate
it to an end device 118. The end device 118 may be a terminal included in a Personal
Computer, a laptop, a mobile device and the like. The relay 116 implemented on the
FPGA board 114 includes the sensing module, the processing module and the
communicating module concurrently performing their respective functions of sensing the
data signals, processing the data signals and communicating the data signals.
[0020] Fig. 2 illustrates an exemplary embodiment including sensing module, the
processing module and the communicating module based on the FPGA board of the
relay, in accordance with an embodiment of the present invention. The embodiment 200
shows a parallel pipeline control configuration 202 where relay processing functions
including sampling, measurement, processing and communication tasks are executed
concurrently. A sensing module 206, a processing module 208 and a communicating
module 210 are arranged in the parallel pipeline control architecture 202 for developing a
hardware processor engine for an FPGA based relay. The three modules including the
sensing module 204, the processing module 206 and the communicating module 208
function concurrently with each other. The sensing module 204 includes a clock, an
ADC, and zero crossing detector and counter. The processing module 206 implements
fast fourier algorithms isolating the fundamental component of current and voltage, and
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implements functions of a multi-functional relay calculations such as and including and
not limited to overcurrent IDMT measurement, Distance measurement, Impedance
measurement, Mho measurement and Reactance measurement. The communicating
module 208 includes a clock and a communication interface such as an Serial/Ethernet
interface for communication.
[0021] For transmitting data along a transmission line, a first set of sample data is
generated at the generator 104, which is sampled and passed to the relay implemented on
the FPGA board 114. Here, the first set of sample data is sensed by the sensing module
204. After sensing, the sensing module 204 passes the sensed first sample of data set to
the processing module 206 for processing, while sensing a next second sample of data set
concurrently while having passed the sensed first sample of data set to the processing
module 206. While the processing module 206 processes the first sample of data set, the
sensing module 204 senses the second sample of data set concurrently. After processing,
the processing module 206 transfers the processed first sample of data set to the
communicating module 208 for the communicating module 208 to transfer it further.
While the communicating module 208 receives the first sample of data set to be
communicated further, the processing module 206 concurrently receives and processes
the second sample of data set which is received from the sensing module 204 after being
sensed, and the sensing module 204 senses a third sample of data set concurrently.
Hence, this cycle of sensing, processing and communicating continues concurrently.
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[0022] The careful time synchronization is done with the help of synchronizing signals
exchanged between the modules 204, 206 and 208 as the data signals are transferred
among the modules. The pipeline control 202 takes care of the coordination between
concurrent processes. It also generates separate clocks for the three modules.
[0023] In an embodiment, in parallel implementation, after sensing 128 samples window,
the sensing module 204 transfers the samples to concurrently working module and starts
sensing the next window of 128 samples while the processing module 206 and
communicating module 208 are working on the previous window. Thus, there is no break
in sampling. However, in sequential implementation, the sampling of next window
commences only after completion of processing and communicating cycles. Thus, the
parallel implementation reduces the total delay significantly for example, by almost 50%
as compared to sequential implementation.
[0024] Fig. 3 illustrates a flowchart showing a method of implementing a digital relay on
an FPGA board with the hardware processing module including sensing module,
processing, and communicating module concurrently working for the digital relay, in
accordance with an embodiment of the present invention. The method 300 is read in
conjunction with the Figs 1-2 as described above. The method 300 includes a step 302
where the sensing module 204 receives first input sample of data set. The sensing module
204 senses the first input sample of data set and at a step 304, the sensing module 204
transfers the sensed first sample of data set to the processing module 206. In an
embodiment, the sensing module receives and senses a 128 samples window.
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[0025] Further at a step 306, the processing module 206 processes the first sample of data
set sensed and received by the sensing module 204, while the sensing module 204 senses
a next second sample of data set concurrently with the processing module 206 processing
the first sample of data set. Furthermore, at step 308, the processing module 206 transfers
the processed first sample of data set to the communicating module 208 for it
concurrently to communicate result of processing the first sample of data set further to an
end device.
[0026] The continuous and concurrent cycle of sensing module 204, the processing
module 206, and the communicating module 208 continues for performance of the digital
relay.
[0027] Advantageously, the present invention provides a hardware processing engine
based on FPGA for digital relays which executes three functions concurrently namely
sensing, processing and communicating, including sampling and measurement functions.
The present hardware processing engine further provides multiple relay functionality in a
single device, viz., overcurrent IDMT relay, Distance Relay, Impedance relay, Mho
Relay and Reactance relay. Additionally, the hardware processing engine uses IP cores
for implementing Fast Fourier Transform and Inverse Fast Fourier Transform algorithms
in digital hardware for isolating the fundamental component of current and voltage. This
prevents the tendency of the relay to trip for transient faults.
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[0028] While certain embodiments have been described, these embodiments have been
presented by way of example only, and are not intended to limit the scope of the present
disclosure. Indeed, the novel methods, devices, and systems described herein may be
embodied in a variety of other forms. Furthermore, various omissions, substitutions, and
changes in the form of the methods, devices, and systems described herein may be made
without departing from the spirit of the present disclosure.

We claim:
1. A multifunctional digital relay for power and data transmission comprising:
a sensing module for sensing a data set;
a processing module for processing a data set; and
a communicating module for communicating a data set to an end device,
and
wherein the sensing module, the processing module and the
communicating module are arranged in a parallel pipeline configuration
for executing the sensing, the processing and the communicating of the
data set concurrently of each other.
2. The multifunctional digital relay of claim 1, wherein the sensing module, the
processing module and the communicating module function concurrently by:
sensing, by the sensing module, a first data set;
transferring, by the sensing module, the first data set after sensing
to the processing module;
processing, by the processing module, the sensed first data set
received from the sensing module;
sensing, by the sensing module, a second data set concurrently
while the processing module processes the sensed first data set received
from the sensing module;
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transferring, by the processing module, processed first data set to
the communicating module;
receiving, by the communicating module, the processed first data
set for communicating to the end device, while the processing module
processes the second data set concurrently;
receiving, by the processing module, sensed second data set from
the sensing module concurrently while the sensing module receives a third
data set for sensing;
transferring, by the processing module, second data set to the
communicating module after processing the second data set; and
receiving, by the communicating module, the processed second
data set for communicating to the end device, and
wherein a continuous cycle of sensing, processing and
communicating of data sets are performed by the sensing module, the
processing module and the communicating module concurrently.
3. The multifunctional digital relay of claim 1, wherein the sensing module includes
a clock, an ADC, and zero crossing detector and counter.
4. The multifunctional digital relay of claim 1, wherein the communicating module
includes a clock and a communication interface such as Serial/Ethernet interface
for communication.
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5. A method of implementing a digital relay on an FPGA board with the hardware
processing module, the method comprises:
sensing, by a sensing module included in the digital relay, a data set;
processing, by a processing module included in the digital relay, a data set;
and
communicating, by a communicating module included in the digital relay,
a data set to an end device, and
wherein the sensing module, the processing module and the
communicating module are arranged in a parallel pipeline configuration for
executing the sensing, the processing and the communicating of the data set
concurrently of each other.
6. The method of claim 8, wherein the sensing module, the processing module and
the communicating module function concurrently by:
sensing, by the sensing module, a first data set;
transferring, by the sensing module, the first data set after sensing
to the processing module;
processing, , by the processing module, the sensed first data set
received from the sensing module;
sensing, by the sensing module, a second data set concurrently
while the processing module processes the sensed first data set received
from the sensing module;
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transferring, by the processing module, processed first data set to
the communicating module;
receiving, by the communicating module, the processed first data
set for communicating to the end device, while the processing module
processes the second data set concurrently;
receiving, by the processing module, sensed second data set from
the sensing module concurrently while the sensing module receives a third
data set for sensing;
transferring, by the processing module, second data set to the
communicating module after processing the second data set; and
receiving, by the communicating module, the processed second
data set for communicating to the end device, and
wherein a continuous cycle of sensing, processing and
communicating of data sets are performed by the sensing module, the
processing module and the communicating module concurrently.
7. The method of claim 8, wherein the processing module implements fast fourier
algorithms isolating the fundamental component of current and voltage, and
implements functions of a multi-functional relay calculations such as and
including and not limited to overcurrent IDMT measurement, Distance
measurement, Impedance measurement, Mho measurement and Reactance
measurement.
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8. The method of claim 8, wherein the communicating module includes a clock and
a communication interface such as a Serial/Ethernet interface for communication.
9. The method of claim 8 further synchronizes data signals exchanged between the
sensing module, the processing module and the communicating module as the
data signals are transferred among the modules.
10. The method of claim 8, wherein the pipeline configuration further implements a
control to take care of coordination between concurrent processes of sensing,
processing and communication, and also generates separate clocks for the sensing
module, the processing module and the communicating module.