DESC:TECHNICAL FIELD
[001] The present disclosure generally relates to electrostatic discharge protection devices for use in electronic architectures. More specifically, the present disclosure relates to fin-based silicon controlled rectifier (SCR) architectures that has high uniformity in current distribution in addition to affording higher electrostatic discharge protection.

BACKGROUND
[002] Background description includes information that can be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[003] With the advancement of semiconductor technology, system on chip (SoC) are now of great demand in the ULSI industry. A SoC chip consists of various analog, RF and digital functional blocks, each requiring dedicated ESD protection concepts. ESD protection is a desperate need for all the technologies, at each node. However, handling ESD protection in these ultra-scaled technologies is much more challenging as compared to planar counterpart and most of the planar concepts / devices are often not applicable for these technologies. SCRs, for example, are a must for ESD protection in low voltage – high speed I/O, as well as, ESD protection of RF pads, due to least parasitic loading and smallest foot print offered by SCRs.
[004] However, the failure threshold of all the Fin based SCR architecture proposed so far suffers due to high non-uniform current distribution among the fins as the number of anode/ cathode fins is increased more than 4. All the injected current under ESD stress is confined predominantly into few fins closer to the junction. This results in severe degradation of failure current per unit area as the number of fins is increased since the extra added fins do not carry any significant current.
[005] FinFET technology replaced their planar counterparts, by offering an improved short channel performance to scale the conventional transistors. However, the severely lowered ESD robustness of FinFET technology node has been an obstruction to develop advanced SoC using FinFET technology. The severely decreased silicon volume further degrades the ESD robustness of Fin based ESD protection elements. An ESD stress occurs when two bodies at different electrostatic potential come in contact leading to a massive flow of current between the bodies for a few 100’s of nano-seconds. At chip level it can be because a charged human touching a device modelled as Human Body Model (HBM) or a charged device being abruptly grounded modelled as Charged Device Model (CDM) or can be during assembly when a huge machinery which is accidently grounded by a chip categorized as Machine Model (MM). These three models are differentiated based on the ESD stress time and peak amplitude of current reached.
[006] An ESD event can result in catastrophic failure of the device by gate oxide breakdown or meltdown of device active area. They can also lead to time dependent degradation of the device. Hence it is critical to design efficient Fin based ESD protection elements for non-planar technology nodes. Among various ESD protection elements SCRs are a must for low voltage – high speed I/O, as well as, ESD protection of RF pads, due to least parasitic loading and smallest foot print offered by SCRs. The implementation of Fin based SCRs with the fundamental concepts borrowed from conventional planar SCR fails to reproduce SCR characteristics. It was shown that a non-zero silicide blocking or introduction of an ESD implant introduced the SCR characteristic in Conventional Fin based SCR. However, the failure threshold in Conventional Fin based SCR (CFSCR) is severely limited by the non-uniform conduction among the fins. As a result of which, the failure threshold severely degrades once the number of anode/cathode fins is increased more than 4. This problem exists in all the previously demonstrated Fin based SCRs.
[007] In technology scaling beyond 45nm, FinFETs have replaced their planar counterparts due to their superior electrostatic control. FinFETs are found to be promising options for System on Chip (SoC) application, which indeed is the key requirement for reduced system cost, size and power while enjoying improved system performance. Each of the functional blocks in a SoC requires an efficient ESD protection. However due to significantly reduced silicon volume Fin based ESD protection elements are prone to early ESD failure. SCRs are one of the most sought for option among various ESD protection devices, owing to their low holding voltage and low on resistance resulting in high failure currents. While designing a Fin based SCRs, the fundamental device design concepts borrowed from planar SCR needs certain modifications to maximize failure threshold. These modifications if carefully engineered can result in a better ESD performance and a higher failure threshold in Fin based SCR than in planar SCRs.
[008] Efforts have been made in the prior art to realize effective and efficient solutions for fin-based SCR architectures that has high uniformity in current distribution in addition to affording higher electrostatic discharge protection. For example, contemporary device designs pertaining to SCR architectures have not effectively addressed the aspect of fin-based silicon controlled rectifier (SCR) architectures that has high uniformity in current distribution and that which can afford higher electrostatic discharge protection.
[009] Thus, there is a need in the art to provide a reliable and efficient fin-based SCR architectures that has high uniformity in current distribution in addition to affording higher electrostatic discharge protection.
[0010] All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
[0011] In some embodiments, the numbers expressing quantities or dimensions of items, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term “about.” Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that may vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.

OBJECTS OF THE PRESENT DISCLOSURE
[0012] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are as listed herein below.
[0013] It is an object of the present disclosure to provide a fin-based SCR architecture that has distributed current configuration and enhanced ESD protection.
[0014] It is another object of the present disclosure to provide a simple and effective fin-based SCR architecture that has distributed current configuration and enhanced ESD protection.
[0015] It is another object of the present disclosure to provide a reliable and efficient fin-based SCR architecture that has distributed current configuration and enhanced ESD protection.
[0016] It is another object of the present disclosure to provide a robust fin-based SCR architecture that has distributed current configuration and enhanced ESD protection.

SUMMARY
[0017] The present disclosure generally relates to electrostatic discharge protection devices for use in electronic architectures. More specifically, the present disclosure relates to fin-based silicon controlled rectifier (SCR) architectures that has high uniformity in current distribution in addition to affording higher electrostatic discharge protection.
[0018] In an aspect, the present disclosure provides for a silicon-controlled-rectifier (SCR) disposed on a substrate. The SCR may include a set of fins made of a semiconducting material, each of the set of fins may include an active region that may be above shallow trench isolation (STI) surface, an inactive region that may be sandwiched between STI region, extending between an anode and a cathode and including a junction region there between. The SCR may further include one or more first transverse fins that traverse the set of fins at one or more respective tapping points positioned between the anode and a first end of the SCR and between one or more second transverse fins and the anode. The one or more second transverse fins traverse the set of fins at one or more respective tapping points and may be positioned between the one or more first transverse fins and the cathode and between the cathode and a second end of the SCR such that positioning of the one or more first transverse fins and the one or more second transverse fins may facilitate maintaining of uniform current distribution in the set of fins.
[0019] In an embodiment, the SCR may include one or more anodes, cathodes, the one or more first transverse fins and the one or more second transverse fins and one or more unit-cells. The one or more the one or more first transverse fins and the one or more second transverse fins may be positioned at predefined one or more unit-cells.
[0020] In an embodiment, the one or more first transverse fins may be positioned between the anode and the first end of the device. The one or more first transverse fins may be away from a well where the anode may be placed. In an embodiment, the anode and the cathode may be placed close to the junction. The one or more second transverse fins may be positioned between the anode and the cathode close to the junction.
[0021] In an embodiment, the one or more second transverse fins may be positioned between the cathode and the one or more first transverse fins and the one or more first transverse may be placed between the anode and the one or more second transverse fins close to the junction.
[0022] In an embodiment, the set of fins may be scaled in horizontal and vertical direction to increase current handling capability.
[0023] In an aspect, the present disclosure provides for a semiconductor device disposed on a substrate. The device may include a set of fins made of a semiconducting material, each of the set of fins may include an active region that may be above shallow trench isolation (STI) surface, an inactive region that may be sandwiched between STI region, extending between an anode and a cathode and including a junction region there between. The device may further include one or more first transverse fins that traverse the set of fins at one or more respective tapping points positioned between the anode and a first end of the device and between one or more second transverse fins and the anode. The one or more second transverse fins traverse the set of fins at one or more respective tapping points and may be positioned between the one or more first transverse fins and the cathode and between the cathode and a second end of the device such that positioning of the one or more first transverse fins and the one or more second transverse fins may facilitate maintaining of uniform current distribution in the set of fins.
[0024] In an embodiment, depth of junctions of any or a combination of the anode and the cathode may be greater than a predefined depth and where depth of any or a combination of the first transverse fins and the second junction fins may be less than the predefined depth and where the substrate may be any semiconductor, an insulator or a combination thereof.
[0025] In an embodiment, an electrostatic discharge (ESD) protection circuit may be configured between a VDD and a ground, where the one or more first transverse fins may be connected to the VDD, the anode may be connected to a PAD. The one or more second transverse fins and the cathode may be connected with the ground. The SCR may be triggered transiently by the ESD protection circuit between the VDD and the ground to provide protection between the PAD and the ground.
[0026] In an embodiment, a gate contact between any or a combination of the first transverse fins and the anode, and the second transverse fins and the cathode may be connected to any or a combination of trigger circuit and a power bus, and where the device may include a plurality of guard rings.
[0027] In an aspect, the present disclosure provides for an integrated circuit. The integrated circuit may include a set of fins made of a semiconducting material, each of the set of fins may include an active region that may be above shallow trench isolation (STI) surface, an inactive region that may be sandwiched between STI region, extending between an anode and a cathode and including a junction region there between. The device may further include one or more first transverse fins that traverse the set of fins at one or more respective tapping points positioned between the anode and a first end of the device and between one or more second transverse fins and the anode. The one or more second transverse fins traverse the set of fins at one or more respective tapping points and may be positioned between the one or more first transverse fins and the cathode and between the cathode and a second end of the device such that positioning of the one or more first transverse fins and the one or more second transverse fins may facilitate maintaining of uniform current distribution in the set of fins.
[0028] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The diagrams are for illustration only, which thus is not a limitation of the present disclosure, and wherein:
[0030] FIG. 1 shows a cross-sectional view of a first modified fin base SCR, in accordance with an embodiment of the present disclosure.
[0031] FIG. 2 shows a cross-sectional view of a second modified fin base SCR, in accordance with an embodiment of the present disclosure.
[0032] FIG. 3 shows a cross-sectional view of one unit-cell of a distributed-tap Fin SCR, in accordance with an embodiment of the present disclosure.
[0033] FIG. 4 shows a cross-sectional view of one unit-cell of a generalized version of a distributed-tap Fin SCR showing an N number of unit cells, in accordance with an embodiment of the present disclosure.
[0034] FIG. 5 illustrates data showing a comparison between a conventional fin based SCR, a first modified fin based SCR, a second modified fin based SCR, a distributed-tap Fin SCR, in accordance with the present disclosure.
[0035] FIG. 6 illustrates data showing a comparison between various number of unit cells of a distributed-tap Fin SCR, in accordance with the present disclosure.
[0036] FIG. 7 illustrates data associated with conduction current density for a first modified fin based SCR, in accordance with the present disclosure.
[0037] FIG. 8 illustrates data associated with conduction current density for a second modified fin based SCR, in accordance with the present disclosure.
[0038] FIG. 9 illustrates data associated with conduction current density for a distributed-tap Fin SCR having four number of unit cells, in accordance with the present disclosure.
[0039] FIG. 10 illustrates data associated with conduction current density for a distributed-tap Fin SCR having eight number of unit cells, in accordance with the present disclosure.

DETAILED DESCRIPTION
[0040] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0041] In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without some of these specific details.
[0042] Embodiments of the present invention include various steps, which will be described below. The steps may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, steps may be performed by a combination of hardware, software, and firmware and/or by human operators.
[0043] Various methods described herein may be practiced by combining one or more machine-readable storage media containing the code according to the present invention with appropriate standard computer hardware to execute the code contained therein. An apparatus for practicing various embodiments of the present invention may involve one or more computers (or one or more processors within a single computer) and storage systems containing or having network access to computer program(s) coded in accordance with various methods described herein, and the method steps of the invention could be accomplished by modules, routines, subroutines, or subparts of a computer program product.
[0044] Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. These exemplary embodiments are provided only for illustrative purposes and so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those of ordinary skill in the art. The invention disclosed may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Various modifications will be readily apparent to persons skilled in the art. The general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Moreover, all statements herein reciting embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future (i.e., any elements developed that perform the same function, regardless of structure). Also, the terminology and phraseology used is for the purpose of describing exemplary embodiments and should not be considered limiting. Thus, the present invention is to be accorded the widest scope encompassing numerous alternatives, modifications and equivalents consistent with the principles and features disclosed. For purpose of clarity, details relating to technical material that is known in the technical fields related to the invention have not been described in detail so as not to unnecessarily obscure the present invention.
[0045] Thus, for example, it will be appreciated by those of ordinary skill in the art that the diagrams, schematics, illustrations, and the like represent conceptual views or processes illustrating systems and methods embodying this invention. The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing associated software. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the entity implementing this invention. Those of ordinary skill in the art further understand that the exemplary hardware, software, processes, methods, and/or operating systems described herein are for illustrative purposes and, thus, are not intended to be limited to any particular named element.
[0046] Systems depicted in some of the figures may be provided in various configurations. In some embodiments, the systems may be configured as a distributed system where one or more components of the system are distributed across one or more networks in a cloud computing system.
[0047] Each of the appended claims defines a separate invention, which for infringement purposes is recognized as including equivalents to the various elements or limitations specified in the claims. Depending on the context, all references below to the "invention" may in some cases refer to certain specific embodiments only. In other cases, it will be recognized that references to the "invention" will refer to subject matter recited in one or more, but not necessarily all, of the claims.
[0048] All methods described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0049] Various terms as used herein are shown below. To the extent a term used in a claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
[0050] The present disclosure generally relates to electrostatic discharge protection devices for use in electronic architectures. More specifically, the present disclosure relates to fin-based silicon controlled rectifier (SCR) architectures that has high uniformity in current distribution in addition to affording higher electrostatic discharge protection.
[0051] The present disclosure also provides an SCR concept for non-planar technologies with highly uniform current distribution among the fins. This disclosed design also has low holding voltage thus improving the failure current further.
[0052] FIG. 1 shows a cross-sectional view of a first modified fin base SCR 100 while FIG. 2 shows a cross-sectional view of a second modified fin base SCR 200, in accordance with an embodiment of the present disclosure.
[0053] As illustrated, the first modified fin based SCR 100 may be disposed on a substrate 116. The SCR may include a set of fins made of a semiconducting material of a predefined height HFIN 110. Each of the set of fins may include an active region that may be above shallow trench isolation (STI) surface 130, an inactive region that is sandwiched between STI region, extending between one or more anodes 104 and one or more cathodes 108 and including a junction region 134 there between. One or more first transverse fins 102-1, 102-2, 102-3..102-N (collectively referred to as first transverse fins or N-taps 102 and individually referred to as first transverse fin 102 or N-tap 102 hereinafter) traverse the set of fins at one or more respective tapping points positioned between the anode 104 and a first end of the SCR. In an embodiment, one or more second transverse fins traverse (collectively referred to as second transverse fins or P-taps 106 and individually referred to as second transverse fin 106 or P-tap 106 hereinafter) the set of fins at one or more respective tapping points. The P-taps 106 may be positioned between the cathode 108 and the anode 104.
[0054] In an embodiment, the anode 104 may be disposed in an N-well 114 and the cathode 108 in a P-well 112. The junction 134 length is given by LAC. A first set of resistances 126-1, 126-2…126-N may be formed internally due to the arrangement of the cathode 108 and the P-taps 106. In another embodiment, a second set of resistances 128-1, 128-2…128-N may be formed internally due to the arrangement of the anodes 104 and the N-taps 102.
[0055] In an embodiment, the SCR design may lead to the formation of internal npn transistor 118 in the P well 112 and an pnp transistor 120 in the N well 114. The resistances 122 and 124 in the P-well 112 and N well 114 sides respectively lead to the formation of the complete SCR circuit. Such positioning of P-taps 106 and N-taps 102 may facilitate maintaining of uniform current distribution in the set of fins.
[0056] The second modified fin base SCR 200 as illustrated in FIG. 2 may differ to that of the first modified fin base SCR 100 in the positional placement of P-taps 106 and N taps 102. The P-taps 106 may be positioned between the cathode 108 and the P-taps 106, while the N-taps 102 may be placed between the anode 104 and the P-taps 106 fins close to the junction.
[0057] FIG. 3 shows a cross-sectional view of one unit-cell of a distributed-tap Fin SCR 300 in accordance with an embodiment of the present disclosure.
[0058] As illustrated the unit-cell of the distributed-tap FIN SCR 300 may include N-taps 1-2 that traverse the set of fins at one or more respective tapping points positioned between the anode 104 and a first end of the SCR 300 and between P-taps 106 106 and the anode 104. The P-taps 106 may be positioned between the N-taps 102 and the cathode and between the cathode and a second end of the SCR 300.
[0059] FIG. 4 shows a cross-sectional view of one unit-cell of a generalized version of a distributed-tap Fin SCR showing an N number of unit cells, in accordance with an embodiment of the present disclosure. As illustrated, the SCR may include the one or more anodes 104, the one or more cathodes 108, the N-taps 102 and the P-taps 106 and one or more unit-cells. The N-taps 102 and the P-taps 106 may be positioned at predefined the one or more unit-cells.
[0060] In an embodiment, the set of fins may be scaled in horizontal and vertical direction to increase current handling capability.
[0061] In another embodiment, depth of junctions of any or a combination of the anode 104 and the cathode 108 may be greater than a predefined depth and wherein depth of any or a combination of the first transverse fins102 and the second transverse fins 106 may be less than the predefined depth. In yet another embodiment, the substrate may be any semiconductor, an insulator or a combination thereof but not limited to the like.
[0062] In another embodiment, an electrostatic discharge (ESD) circuit may be configured between a VDD and a ground. The one or more first transverse fins 102 may be connected to the VDD, the anode 104 may be connected to a PAD, the one or more second transverse fins 106 and the cathode 108 may be connected with the ground. The SCR may be triggered transiently by the ESD circuit between the VDD and the ground to provide protection between the PAD and the ground.
[0063] In yet another embodiment, a gate contact between any or a combination of the first transverse fins 102 and the anode 104 , and the second transverse fins 106 and the cathode 108 may be connected to any or a combination of trigger circuit and a power bus. In another embodiment, the device may include a plurality of guard rings.
[0064] The proposed Silicon Controlled Rectifier (SCR) device design (as shown respectively in FIGs.1-3) consist of different schemes of tap engineering to improve the current(Turn-on) uniformity among the anode/cathode fins. The taps of the SCR’s are engineered to tune bipolar trigger among the fins. In prior art, the hotspot developed resulting in the failure of SCR was localized in the inactive region of the fin closest to the junction. In the SCR architecture proposed here the hotspot is spread across the fins and is pushed in the bulk silicon improving the heat dissipation and thus the failure threshold. The ESD behavior of the proposed device was simulated using 3D device TCAD, in the configuration where, the anode and n-tap were stressed, and cathode, and p-tap terminals were grounded.
[0065] FIG. 5 illustrates data showing a comparison between a conventional fin based SCR, a first modified fin based SCR, a second modified fin based SCR, a distributed-tap Fin SCR, while FIG. 6 illustrates data showing a comparison between various number of unit cells of a distributed-tap Fin SCR, in accordance with the present disclosure. In particular, the TLP results presented in FIG. 5 show improved failure current in the devices proposed here. It can also be seen in FIG. 6 that the failure current per unit length scales with the number of unit-cell in DTFSCR which is seen as a constant failure current per unit area.
[0066] The principle behind the operation of the device is as follows: the first modified device proposed (FIG. 1, MFSCR-1) has the taps on both the side of the well placed near the junction. This results in degradation of the bipolar efficiency of fins closer to the junction and enhancement of bipolar efficiency of the fins farthest from the junction thus improving the overall current distribution. However, it was found that the failure current was limited only by the cathode fin closest to the junction and not by the anode fins. Therefore, despite power to failure increasing in MFSCR-1 the failure current is slightly decreased due to increased voltage at failure as a result of the N-Tap degrading the bipolar efficiency of the anode fin taking the highest amount of current which isn’t necessary.
[0067] The second modified device proposed (FIG. 2, MFSCR-2) has taps engineered only on the cathode side. Despite power to failure decreasing in this architecture since voltage at failure decreases the failure current increases. The current distribution among fins is more uniform in MFSCR-2 than CFSCR, however less uniform than the in MFSCR-1.
[0068] The third device proposed is Distributed-Tap FinSCR (DTFSCR) shown in FIG’s. 3-4. FIG. 3 shows one unit-cell of Distributed-Tap FinSCR while multiple unit-cells are cascaded in the device in FIG. 4 is formed. In each well respective anode/cathode fins are placed. The number of anode/cathode fins and the number of taps in each well allows to engineer the holding voltage, trigger voltage, trigger current and on-resistance. These parameters can also be engineered using the anode to cathode distance, the tap to anode/cathode distance, well doping profiles and the depth of an ESD implant. In this design the anode/cathode fins are placed in the middle of the junction. The taps are placed on both the sides of the junction to ensure current distribution among the fins in each well. This is to make sure that the failure threshold of this device is less dependent on the fins near the junction. The two junctions provide sufficient carriers for the fins on either sides of the junction to uniformly turned on. This is the only Fin based SCR in prior art which has failure current scaling with number of fins.
[0069] FIG. 7 illustrates data associated with conduction current density for a first modified fin based SCR while FIG. 8 illustrates data associated with conduction current density for a second modified fin based SCR, in accordance with the present disclosure. FIG. 9 illustrates data associated with conduction current density for a distributed-tap Fin SCR having four (4) number of unit cells while FIG. 10 illustrates data associated with conduction current density for a distributed-tap Fin SCR having eight (8) number of unit cells, in accordance with the present disclosure.It is plotted for a cut taken in the inactive region of the fin at 5nm from the base of the active region. In the figures shown (FIG’s. 7-10), the current density is measured as x107 A/cm2.
[0070] An aspect of the present disclosure pertains to a distributed-tap fin SCR device. The SCR device comprising any number of anode or cathode fins, any number of tap members (or taps), and any number of unit cells.
[0071] In an aspect, the distributed-tap fin SCR device can include tap members (or taps) only in a select number of unit cells.
[0072] Another aspect of the present disclosure pertains to a modified fin SCR device. The modified fin SCR device includes tap members (or taps) on both anode and cathode side placed close to the junction and anode/cathode fins placed after taps.
[0073] In an aspect, the modified fin SCR device includes taps on anode side placed closed to the well and taps on cathode side placed away from the well.
[0074] In an aspect, taps on cathode side placed closed to the well and taps on anode side placed away from the well.
[0075] Another aspect of the present disclosure pertains to a semiconductor device having the configurations provided in this disclosure. In an aspect, the semiconductor device with regards and in association with the distributed-tap fin SCR device and the modified fin SCR device are multiplied in X and Y direction to increase current handling capability.
[0076] In an aspect, the semiconductor device can be complementary to the devices enumerated above.
[0077] In an aspect, the semiconductor device can have anode and/or cathode has deeper junctions compared to n- and p- taps.
[0078] In an aspect, the semiconductor device an ESD implant is present.
[0079] Another aspect of the present disclosure pertains to an ESD protection configuration or concept. In one aspect, the configuration is for protection between PAD and ground, based on the 3D semiconductor device.
[0080] In an aspect of the ESD protection configuration or concept, n-tap is connected to VDD, Anode is connected to PAD, p-tap and Cathode are connected with ground and SCR is triggered transiently by clamp between VDD and Ground.
[0081] In an aspect, the 3D device can include guard-rings.
[0082] In an aspect, the substrate associated with any of the devices mentioned herein can be a semiconductor or an insulator or a stack of two or more.
[0083] Another aspect of the present disclosure pertains to an integrated circuit that can accommodate all the components, devices, configurations, or concepts mentioned herein.
[0084] It was found that the reason for non-uniform current distribution among the fins was due to non-uniform bipolar trigger among the fins as a result of their non-uniform distance from the well-junction. In the proposed SCR architecture, to improve uniformity in bipolar trigger among the fins the bipolar efficiency of the fins carrying highest amount of current distribution (cathode/anode fins closer to the junction) needs to be degraded and the bipolar efficiency of the fins carrying the least amount of current distribution (cathode/anode fins farthest from the junction) needs to be enhanced. Bipolar efficiency can be degraded by placing the taps adjacent to them. And to enhance bipolar efficiency either the taps can be moved away from them or increase the impact ionization generated carriers for bipolar turn-on. These design modifications allows to come up with an SCR architecture that has very high uniformity in the current distribution among the fins.
[0085] The present disclosure provides an SCR concept for non-planar technologies with highly uniform turn-on among fins and thus resulting in failure current scaling with the number of fins. The Distributed-Tap Fin SCR demonstrated here has a failure threshold of 24 mA/µm2 (774 mA/µm for a 192 anode/cathode fin device). None of the other previously demonstrated Fin based SCR device has failure current scaling with number of fins.
[0086] Thus, it will be appreciated by those of ordinary skill in the art that the diagrams, schematics, illustrations, and the like represent conceptual views or processes illustrating systems and methods embodying this invention. The functions of the various elements shown in the figures can be provided through the use of dedicated hardware as well as hardware capable of executing associated software. Similarly, any switches shown in the figures are conceptual only. Their function can be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the entity implementing this invention. Those of ordinary skill in the art further understand that the exemplary hardware, software, processes, methods, and/or operating systems described herein are for illustrative purposes and, thus, are not intended to be limited to any particular named.
[0087] While embodiments of the present invention have been illustrated and described, it will be clear that the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the invention, as described in the claim.
[0088] In the foregoing description, numerous details are set forth. It will be apparent, however, to one of ordinary skill in the art having the benefit of this disclosure, that the present invention can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention.
[0089] As used herein, and unless the context dictates otherwise, the term "coupled to" is intended to include both direct coupling (in which two elements that are coupled to each other contact each other)and indirect coupling (in which at least one additional element is located between the two elements). Therefore, the terms "coupled to" and "coupled with" are used synonymously. Within the context of this document terms "coupled to" and "coupled with" are also used euphemistically to mean “communicatively coupled with” over a network, where two or more devices are able to exchange data with each other over the network, possibly via one or more intermediary device.
[0090] It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps can be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refers to at least one of something selected from the group consisting of A, B, C …. And N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc.
[0091] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention can be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE PRESENT DISCLOSURE
[0092] The present disclosure provides a fin-based SCR architecture that has distributed current configuration and enhanced ESD protection.
[0093] The present disclosure provides a simple and effective fin-based SCR architecture that has distributed current configuration and enhanced ESD protection.
[0094] The present disclosure provides a reliable and efficient fin-based SCR architecture that has distributed current configuration and enhanced ESD protection.
[0095] The present disclosure provides a robust fin-based SCR architecture that has distributed current configuration and enhanced ESD protection.
,CLAIMS:1. A silicon-controlled-rectifier (SCR) disposed on a substrate, said SCR comprising:
a set of fins made of a semiconducting material, each of said set of fins comprising an active region that is above shallow trench isolation (STI) surface, an inactive region that is sandwiched between STI region, extending between an anode and a cathode and including a junction region there between;
one or more first transverse fins that traverse the set of fins at one or more respective tapping points positioned between the anode and a first end of the SCR and between one or more second transverse fins and the anode, wherein
the one or more second transverse fins traverse the set of fins at one or more respective tapping points, wherein the one or more second transverse fins are positioned between the one or more first transverse fins and the cathode and between the cathode and a second end of the SCR;
such that positioning of the one or more first transverse fins and the one or more second transverse fins facilitates maintaining of uniform current distribution in the set of fins.

2. The SCR as claimed in claim 1, wherein the device comprises one or more anodes, one or more cathodes, the one or more first transverse fins and the one or more second transverse fins and one or more unit-cells, wherein the one or more the one or more first transverse fins and the one or more second transverse fins are positioned at predefined the one or more unit-cells.

3. The SCR as claimed in claim 1, wherein the one or more first transverse fins are positioned between the anode and the first end of the device, wherein the one or more first transverse are away from a well wherein the anode is placed and wherein the anode and the cathode are placed close to the junction.

4. The SCR as claimed in claim 1, wherein the one or more second transverse fins are positioned between the cathode and the second end of the device, wherein the one or more second transverse are away from a well wherein the cathode is placed wherein the anode and the cathode are placed close to the junction.

5. The SCR as claimed in claim 1, wherein the set of fins are scaled in horizontal and vertical direction to increase current handling capability.

6. A semiconductor device disposed on a substrate, said device comprising:
a set of fins made of a semiconducting material, each of said set of fins comprising an active region that is above shallow trench isolation (STI) surface, an inactive region that is sandwiched between STI region extending between an anode and a cathode and including a junction region there between;
one or more first transverse fins that traverse the set of fins at one or more respective tapping points positioned between the anode and a first end of the SCR and between one or more second transverse fins and the anode, wherein
the one or more second transverse fins traverse the set of fins at one or more respective tapping points, wherein the one or more second transverse fins are positioned between the one or more first transverse fins and the cathode and between the cathode and a second end of the SCR;
such that positioning of the one or more first transverse fins and the one or more second transverse fins facilitates maintaining of uniform current distribution in the set of fins.

7. The device as claimed in claim 6, wherein depth of junctions of any or a combination of the anode and the cathode are greater than a predefined depth and wherein depth of any or a combination of the first transverse fins and the second transverse fins are less than the predefined depth and wherein the substrate is any semiconductor, an insulator or a combination thereof.

8. The device as claimed in claim 6, wherein an electrostatic discharge (ESD) protection circuit is configured between a VDD and a ground, wherein the one or more first transverse fins are connected to a VDD, the anode is connected to a PAD, the one or more second transverse fins and the cathode are connected with the ground and wherein the SCR is triggered transiently by the ESD circuit between the VDD and the ground to provide protection between the PAD and the ground.

9. The device as claimed in claim 6, wherein a gate contact between any or a combination of the first transverse fins and the anode, and the second transverse fins and the cathode are connected to any or a combination of trigger circuit and a power bus, and wherein the device comprises a plurality of guard rings.

10. An integrated circuit, said circuit comprising:
a set of fins made of a semiconducting material, each of said set of fins comprising an active region that is above shallow trench isolation (STI) surface, an inactive region that is sandwiched between STI region extending between an anode and a cathode and including a junction region there between;
one or more first transverse fins that traverse the set of fins at one or more respective tapping points positioned between the anode and a first end of the SCR and between one or more second transverse fins and the anode, wherein
the one or more second transverse fins traverse the set of fins at one or more respective tapping points, wherein the one or more second transverse fins are positioned between the one or more first transverse fins and the cathode and between the cathode and a second end of the SCR;
such that positioning of the one or more first transverse fins and the one or more second transverse fins facilitates maintaining of uniform current distribution in the set of fins.