CLIAMS:1. A field effect transistor device comprising:
a substrate;
a fin structure disposed over said substrate;
a source region and a drain region, wherein said substrate extends from said source region to said drain region; and
an epitaxial layer partially covering said source region and disposed over said fin, wherein said epitaxial layer is at least partially covered by a gate stack to enable channel formation in epitaxial region and to enable vertical tunneling from said source region to said channel along gate electric field.
2. The device of claim 1, wherein said epitaxial layer hosts the channel, and wherein said tunneling takes place from said source to said epitaxial layer when gate voltage is applied.
3. The device of claim 1, wherein application of gate voltage enables alignment of conduction band of the epitaxial region with valence band of said source region to allow tunneling of electrons from said source region to said epitaxial region.
4. The device of claim 1, wherein said epitaxial layer is a lightly doped epitaxial layer.
5. The device of claim 1, wherein portion of said epitaxial layer that is not covered by said gate stack is consumed by Silicidation.
6. The device of claim 1, wherein said substrate is any or a combination of a semiconductor or an insulator.
7. The device of claim 1, wherein the fin structure is made of any or a combination of Si, SiGe, Ge, materials belonging to III – V, materials belonging to III – Nitride groups, transition metal dichalcogenides, and 2-dimensional semiconductors.
8. The device of claim 1, wherein the epitaxial layer is made of any or a combination of Si, SiGe, Ge, materials belonging to III – V, materials belonging to III – Nitride groups, transition metal dichalcogenides, and 2-dimensional semiconductors.
9. The device of claim 1, wherein said source region has a lower band gap than said epitaxial layer, and wherein said drain region has a higher band gap than said epitaxial layer.
10. The device of claim 1, wherein said source region and said epitaxial layer form a hetro-junction.
11. The device of claim 1, wherein a dielectric or semiconducting tunnel barrier is inserted between the source region and the epitaxial layer.
12. The device of claim 1, wherein mobile carriers tunnel from the source to the epitaxial layer, and thereafter from the epitaxial layer to the drain.
13. A field effect transistor device comprising:
a substrate;
a nanowire disposed over said substrate;
a source region;
a drain region, wherein said substrate extends from said source region to said drain region; and
an epitaxial layer partially covering said source region and disposed over said fin, wherein said epitaxial layer is covered by a gate stack to enable channel formation in epitaxial region and to enable vertical tunneling from said source to said channel.
14. The device of 12, wherein the nanowire is embedded between semiconducting islands that are disposed over the substrate, and wherein the semiconducting islands form source and drain contacts.
,TagSPECI:TECHNICAL FIELD
[0001] The present disclosure generally relates to the field of semiconductor devices and nanotechnology. In particular, the present disclosure pertains to a fin enabled tunnel Field Effect Transistor.
BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] Nano electronic devices are generally fabricated on semiconductor substrates as integrated circuits. A complementary metal-oxide-semiconductor (CMOS) field effect transistor is one of the core elements of the integrated circuits. Dimensions and operating voltages of CMOS transistors are continuously reduced, or scaled down, to obtain ever-higher performance and packaging density of the integrated circuits.
[0004] One of the problems due to the scaling down of CMOS transistors is that the power consumption keeps increasing. This is partly because leakage currents increase due to short channel effects. The problem of leakage current has been addressed by Fin field effect transistors (FinFET) where the conducting channel is wrapped by a thin silicon "fin" that forms the body of the device. Thickness of the fin (measured in the direction from source to drain) determines the effective channel length of the device. The Wrap-around gate structure provides a better electrical control over the channel and thus helps in reducing the leakage current and overcoming other short-channel effects.
[0005] It took almost 20 years for FinFET technology to mature and become a reality for semiconducting products replacing planar devices. As technology evolution doesn't allow abrupt changes, FinFETs too enjoy advancements from planar nodes like High-?? metal gate, raised/epi source-drain, strained silicon and gate last process. FinFET technology has allowed the semiconductor devices to reach a size as small as 10 nm and question now is what would replace Si or SiGe FinFET and would there be serious change in technological evolution while scaling below 10nm nodes.
[0006] To answer the first question, various competing concepts, such as quantum well channel FinFET, III-V FinFET, Nanowire FET and Tunnel FETs are being explored. Of these concepts, tunnel FETs are able to address problem related to decrease in the supply voltage. Scaling down of devices has failed to provide any reduction in the supply voltage mainly due to the fact that the sub threshold swing is limited to minimally about 60 mV/decade, such that switching the transistor from ON to OFF needs a certain voltage variation and therefore a minimum supply voltage. Given the fact that FinFET and Nanowire FET devices are limited by thermionic injection (SSmin = 60mV/dec), tunnel FETs where tunneling phenomena allows sub-60mV sub-threshold operation, are proposed to replace FinFET/Nanowire FET devices beyond 11nm node.
[0007] For the above advantages, namely absence of short-channel effects, low off-currents and a lower than 60 mV/dec sub threshold that has been the physical limit of conventional MOSFETs enabling use of lower supply voltages, the Tunnel field-effect transistors (TFETs) are typically advertised as successors of metal-oxide semiconductor field-effect transistors (MOSFETs). However, all-silicon TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier.
[0008] During last 15 years there have been extensive investigations on Tunnel FET devices for ultra low power and high performance operation. FIG. 1A and FIG 1B illustrate ON and OFF state respectively of a typical very early TFET concept. Despite several advancements like SiGe source, Low-K drain spacer, High-??source spacer, low drain doping, highly doped source, abrupt source junction profiles, post silicidation implant, band gap engineering and double gate architectures, such devices suffered from extremely low ON currents. This was primarily attributed to limited tunneling cross-section/area available in gated P-i-N diodes (for this reason they are also known as point tunneling FETs). To overcome this problem, vertical tunneling/ area scaled tunneling/ line tunnelling devices have been proposed. FIG. 2A illustrates schematic arrangement of a typical Planar Area Scaled TFET as against a typical point TFET illustrated in FIG. 2B. Such devices have theoretically shown significantly improved ON current, reduced leakage and sub-threshold slope, attributed to increased tunneling cross section and gate-field aligned binary tunneling mechanism. Though there are concerns in terms of dealing with trap assisted tunnelling (TAT) and diffused junction profiles, there is a need to take this concept to Fin-based technologies, allowing smooth transition from FinFET technology to Fin-based vertical Tunnel FETs, while enjoying benefits of FinFET architecture.
[0009] All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
[0010] In some embodiments, the numbers expressing quantities of ingredients, properties such as concentration, reaction conditions, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term “about.” Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
[0011] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0012] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0013] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all Markush groups used in the appended claims.
OBJECTS OF THE INVENTION
[0014] An object of the present disclosure is to provide an efficient FET with lower leakage and high drive current for various miniaturized electronic circuits such as low power – high performance wireless systems.
[0015] Another object of the present disclosure is to provide a FET that can operate with supply voltage as low as 0.3 – 0.4V without a loss of performance.
[0016] Another object of the present disclosure is to provide a novel Fin enabled vertical or area scaled tunneling FET for sub-10nm channel length operation.
[0017] Another object of the present disclosure is to provide a Gate-field aligned tunneling in Fin-based architecture, which improves ON current due to increased electric field and band alignment.
[0018] Another object of the present disclosure is to provide a 3D Fin-based architecture for increased gate control over the tunneling region.
[0019] Another object of the present disclosure is to provide an improved sub-threshold slope and OFF current by increased gate control over tunneling region and channel, respectively.
[0020] Another object of the present disclosure is to provide a method to fabricate the disclosed Fin enabled area scaled tunnel FET that does not require any quantum technological jump from the existing infrastructure and maintains continuity with the present day technology.
SUMMARY
[0021] Aspects of the present disclosure relate to a field effect transistor that incorporates vertical tunneling in Fin-based field effect transistor. In an aspect, the disclosed architecture enables reduction in gate length to as low as 10nm. It also exhibits marked improvement in respect of ON current, OFF current, transconductance, output resistance, unity gain frequency and footprint area over conventional vertical tunneling FET or planar area scaled devices having corresponding drive capability.
[0022] In an embodiment, architecture of the disclosed FET can facilitate area tunneling along the gate electric field that enhances tunneling cross-sectional area (area scaled tunneling). In an aspect, area scaled tunneling can be provided in a Fin-based structure, thus providing a transition from FinFET to Fin-TFET technology without significant technological changes.
[0023] In an embodiment, the Fin or nanowire based structure can incorporate P+ source and N+ drain with a lightly (N) doped epitaxial layer partially overlapping the source. Alternatively, there can be N+ source and P+ drain with a lightly (P) doped epitaxial layer partially overlapping the source. The channel between the source and drain can be lightly (P or N) doped.
[0024] In an embodiment, the lightly doped epitaxial region can be wrapped from three directions by a gate stack (dielectric and metal stack), which enables channel formation in the epitaxial region and enhances tunneling from source to the channel. In an aspect, the epitaxial region hosts the channel or inversion layer and vertical tunneling takes place from the source to epitaxial region when gate voltage is applied. In another aspect, the device architecture can improve the tunneling cross-sectional area and reduce the tunneling barrier while reducing the device foot print. In yet another aspect, the Fin structure improves control over the channel region, which improves the OFF state behavior. It also enhances electric field in ON-state condition and increases the drive current. Smaller foot print, higher ON current, and improved sub-threshold operation increases the ON current per device foot print area and reduces the power dissipation.
[0025] In an embodiment, the source material can include SiGe that can, due to its lower band gap, reduce barrier height, lower effective mass, and enhance electric field at the source – epi interface. Higher interface electric field lowers the tunneling distance, which together with reduced barrier height and effective mass, improves the tunneling probability without significantly affecting the leakage characteristics.
[0026] In an embodiment, the disclosure provides doping concentration of the source, which in combination with SiGe composition, can ensure a significant improvement in ON current with very small change in leakage current i.e. no significant increase in the channel leakage.
[0027] In an embodiment, the disclosure provides epitaxial region thickness, doping strength of epitaxial region and overlap length (LOV) of the epitaxial region with the source that are engineered to further enhance the performance of the disclosed TFET by achieving further increase in the ON state current without increase in OFF state leakage current.
[0028] In an embodiment, the disclosure provides Fin geometry comprising its width (WFIN), height (HFIN) and edge radius (rcur) that have been optimized.
[0029] According to one embodiment, method of the present disclosure can be configured for fabrication of the disclosed fin enabled area scaled Tunnel Field Effect Transistor in accordance with embodiments of the present disclosure. In an embodiment, the method can include the steps of patterning the fin, and depositing a dummy gate stack and forming a spacer. The method further can include the step of implanting source and drain and performing their annealing, and carrying out silicidation. The method can further involve removing the dummy gate stack and the spacer, and growing an epitaxial layer with in-situ doping, and then depositing a gate stack. Further, the method can involve depositing source, drain and gate contacts, and finally, depositing first interlayer dielectric and Chemical mechanical polishing (CMP). In an aspect, the disclosed method can use gate last process, and low temperature local epitaxial growth process of standard FinFET CMOS process line and does not require any quantum technological jump from the existing infrastructure and maintains continuity with the present day technology.
[0030] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components
BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0032] FIG. 1A and FIG. 1B illustrate schematic arrangement of a typical early TFET (n-channel gated P-i-N TFET) concept along with its Band Diagram in OFF and ON state respectively.
[0033] FIG. 2A and FIG. 2B illustrate schematic arrangement of a typical Planar Area Scaled TFET and a typical point TFET respectively.
[0034] FIG. 3 illustrates an exemplary isometric representation of the fin enabled area scaled Tunnel Field Effect Transistor in accordance with embodiments of the present disclosure.
[0035] FIG. 4A to FIG. 4C illustrate exemplary cross sectional details of the fin enabled area scaled Tunnel Field Effect Transistor along sections C1, C2 and C3 respectively in accordance with embodiments of the present disclosure.
[0036] FIG. 5 illustrates an exemplary conduction and valance band diagram depicting band alignment and bending under OFF and ON state of the fin enabled area scaled Tunnel Field Effect Transistor along section C4 in accordance with embodiments of the present disclosure.
[0037] FIG. 6 illustrates an exemplary graph depicting comparison of input characteristics of the disclosed fin enabled area scaled Tunnel Field Effect Transistor as against those of a planar area TFET and point (Gated P-i-N) TFET in accordance with embodiments of the present disclosure.
[0038] FIG. 7 illustrates an exemplary graph depicting comparison of output characteristics of the disclosed fin enabled area scaled Tunnel Field Effect Transistor as against those of a planar area TFET and point (Gated P-i-N) TFET in accordance with embodiments of the present disclosure.
[0039] FIG. 8 illustrates an exemplary process flow diagram for fabrication of the disclosed fin enabled area scaled Tunnel Field Effect Transistor in accordance with embodiments of the present disclosure.
DETAILED DESCRIPTION
[0040] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0041] Each of the appended claims defines a separate invention, which for infringement purposes is recognized as including equivalents to the various elements or limitations specified in the claims. Depending on the context, all references below to the "invention" may in some cases refer to certain specific embodiments only. In other cases it will be recognized that references to the "invention" will refer to subject matter recited in one or more, but not necessarily all, of the claims.
[0042] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0043] All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0044] Various terms as used herein are shown below. To the extent a term used in a claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
[0045] Embodiments of present disclosure relate to a field effect transistor that incorporates vertical tunneling in Fin-based field effect transistor. The proposed disclosure provides a roadmap for beyond FinFET technologies while enjoying advantages of FinFET like structure without demanding technological abruptness from existing FinFET technology nodes to beyond FinFET nodes.
[0046] In an aspect, the disclosed device can have a gate length as low as 10nm and compared to the conventional vertical tunneling FET or planar area scaled devices, can have up to 100% improvement in ON current, 15x reduction in OFF current, 3x increase in the trans conductance, 30% improvement in output resistance, 55% improvement in the unity gain frequency with 6x reduction in the footprint area for a given drive capability. Furthermore, the disclosed device can bring the average and minimum sub-threshold slope (SS) down to 40mV/dec and 11mV/dec respectively at 10nm gate length. This gives a path for beyond FinFET System on Chip (SoC) applications by enjoying analog, digital and RF performance improvements.
[0047] In an embodiment, the disclosed FET incorporates area tunneling along the gate electric field to enhance the tunneling cross-sectional area (area scaled tunneling). In an aspect area scaled tunneling can be provided in a Fin-based structure that allows smooth transition from FinFET to Fin-TFET technology without significant technological changes.
[0048] In an embodiment, the Fin based structure can incorporate P+ source and N+ drain with a lightly (N) doped epitaxial layer partially overlapping the source. Alternatively there can be N+ source and P+ drain with a lightly (P) doped epitaxial layer partially overlapping the source. The channel between the source and drain can be lightly (P or N) doped. In an alternate embodiment, the fin structure can be replaced by a nanowire supported at two ends by a suitable structure. In the exemplary device the doping level of the source (NSOURCE), drain (NDRAIN) and substrate (NSUBST) is maintained as 5x1020, 1x1020 and 1x1016 respectively.
[0049] In an embodiment, the lightly doped epitaxial region can be wrapped from three directions by a gate stack (dielectric and metal stack), which enables channel formation in the epitaxial region and enhances tunneling from source to the channel. In an aspect, the epitaxial region hosts the channel or inversion layer and vertical tunneling takes place from the source to epitaxial region when gate voltage is applied. In another aspect, the device architecture improves the tunneling cross-sectional area, reduces the tunneling barrier while reducing the device foot print. In yet another aspect, the Fin structure improves the control over the channel region, which improves the OFF state behavior. It also enhances electric field in ON-state condition and increases drive current. Smaller foot print, higher ON current and improved sub-threshold operation increases the ON current per device foot print area and reduces the power dissipation.
[0050] In an embodiment, the source material can be SiGe and can include up to 45% Germanium. In an aspect, SiGe source, due to its lower band gap, reduces the barrier height, lowers the effective mass, and enhances the electric field at the source – epi interface. Higher interface electric field lowers tunneling distance, which together with reduced barrier height and effective mass, improves the tunneling probability without significantly affecting the leakage characteristics. In another aspect, the proposed doping concentration of the source in combination with proposed SiGe composition ensures a significant improvement in ON current with very small change in leakage current with no significant increase in the channel leakage.
[0051] In an embodiment, the epitaxial region thickness, doping of epitaxial region and overlap (LOV) of the epitaxial region with the source are engineered to further enhance the performance of the disclosed TFET by achieving further increase in the ON state current without increase in OFF state leakage current. In the exemplary device, the epitaxial region thickness (TEPI), doping of epitaxial region (NEPI) and overlap (LOV) of the epitaxial region with the source can be maintained as 2 nm, 3x1019 and 40 nm respectively.
[0052] In an embodiment, the Fin geometry can include its width (WFIN), height (HFIN) and edge radius (rcur) being optimized, wherein in an exemplary device, width, height, and edge radius of the fin can be maintained as 10 nm, 40 nm and 2 nm respectively.
[0053] In an embodiment, a method to fabricate the proposed device is provided, wherein the disclosed method can use gate last process and low temperature local epi growth process of standard FinFET CMOS process line, and therefore does not require any quantum technological jump from the existing infrastructure and maintains continuity with the present day technology.
[0054] Referring now to FIG. 3, wherein a fin enabled area scaled tunnel field effect transistor 300 is disclosed. Depicted therein is an isometric view of the disclosed device. The device 300 can include a three dimensional nano sized structure 302 configured over a substrate such as box 304. The substrate 304 can be a semiconductor or an insulator or a combination of both. In an embodiment, the three-dimensional nano sized structure 302 can be fin shaped as depicted in the exemplary illustration in FIG. 3. It is to be understood that though various embodiments of the present disclosure have been explained with reference to a fin shaped structure, the three dimensional nano sized structure 302 can be of any other suitable shape such as a nano wire and all such variations are well within the scope of the present disclosure.
[0055] In an embodiment, the fin can be of one or more materials selected out of Si, SiGe, Ge, other materials belonging to III – V or III – Nitride groups, transition metal dichalcogenides or other 2-Dimentional semiconductors.
[0056] In an embodiment, fin structure can include a source 306 and a drain 308 at its two ends with a lightly doped epitaxial layer (or epitaxial region) (not shown here) extending from edge of the drain 308 to cover the channel between the drain 306 and source 304, and further extend to partially cover the source 306. Alternatively, the epitaxial layer can cover the entire Fin. In an embodiment, the source 306 can have a lower bandgap than epitaxial region, the drain 308 can have a higher bandgap than epitaxial region; and source 306 and epitaxial regions can form a hetro-junction. Further a dielectric or semiconducting tunnel barrier can be inserted between source 306 and epitaxial region. The arrangement can make mobile carriers tunnel from source 306 to the epitaxial region and thereafter from epitaxial region to the drain 308.
[0057] In an embodiment, the epitaxial region can be of one or more materials selected out of Si, SiGe, Ge, materials belonging to III – V or III – Nitride groups, transition metal dichalcogenides or other 2-Dimentional semiconductors.
[0058] In an embodiment, the lightly doped epitaxial region can be wrapped from three directions by a gate stack (dielectric and metal stack), which can enable channel formation in the epitaxial region and enhance tunneling from source to the channel. The gate stack can be configured to cover the entire epitaxial layer. In an embodiment of implementation, it is also possible to have a configuration where gate stack partially covers the epitaxial layer wherein epitaxial layer outside gate can be consumed by Silicidation.
[0059] In an aspect, the epitaxial region can host the channel or inversion layer, and vertical tunneling can take place from the source to epitaxial region when gate voltage is applied. In another aspect, the device architecture improves the tunneling cross-sectional area, reduces the tunneling barrier while reducing the device foot print. In yet another aspect, the Fin structure improves the control over the channel region, which improves the OFF state behavior. It also enhances electric field in ON-state condition and increases the drive current. Smaller foot print, higher ON current and improved sub-threshold operation increases the ON current per device foot print area and reduces the power dissipation.
[0060] In an embodiment, the source 306 can be of first conductivityy type (P+) and drain 308 of second conductivity type (N+) and the fin region between source 306 and drain 308 can be be lightly doped first or second conductivity type (P or N). The lightly doped epitaxial layer can be second conductivity type (N+) partially overlapping the source.
[0061] Alternatively and to make a complimentary device, the source 306 can be of second conductivity type (N+) and drain 308 of first conductivity type (P+) with a lightly doped epitaxial layer that can be first conductivity type (P+) partially overlapping the source. Further, the channel between the source 306 and the drain 308 can be lightly doped first or second conductivity type (P or N).
[0062] In an alternate embodiment, the three dimensional nano sized structure 302 can be a nanowire supported at its two ends by suitable means. In implementation, the nanowire can be embedded between two semiconducting islands disposed over a substrate wherein the two semiconducting islands can form source and drain contacts with other details and parameters remaining same as in case of a fin structure.
[0063] In an aspect, the source region doping can be an important device design parameter, especially for area scaled concepts. Experiments with different doping level have shown increase in ON current with increasing source doping without significantly affecting the leakage current before onset of band-to-band tunneling. Lowering of threshold voltage is also observed which in turn is advantageous for the TFET device in conjunction with quantum confinement effects. This behavior is attributed to an increased electric field across the source-epi interface as a function of source doping, which in-turn reduces the depletion width and also causes the valance band of source to move upwards. These two effects reduce the tunnel barrier width and move the conduction band in the epitaxial region relatively down. This eventually reduces the turn-on voltage of the device and improves the ON current by increasing the tunneling probability. As the epitaxial layer is depleted by the gate electric field at nil gate voltage, no significant change in the OFF current up-to a certain doping is seen. Above the source doping of 1x1021cm-3, an alignment of valance (source side) and conduction (channel) bands under OFF state condition was observed, which in-turn increases the leakage current at nil gate voltage. Above a certain source doping, which also depends on the Ge %, an exponential increase in the leakage current with respect to the source doping was observed.
[0064] In an embodiment, the source 306 can be made of material SiGe. In an aspect, Germanium content of the SiGe source is another key parameter that seriously affects the SS, ON and OFF currents. Increasing Ge content reduces the band gap, hence improves the tunneling current. At the same time, if Ge% is sufficiently high, it increases the OFF current on account of an early alignment of conduction and valence bands. Moreover, decreased band gap also results in increase in the drain-to-source leakage.
[0065] In an embodiment, experiments with different Ge content and doping level of the source has established that an optimum combination of doping and Ge content can be in the range of 30-45% Ge and doping of 5x1020 - 1x1021cm-3. In the exemplary device 300, germanium content of 45% and source doping of 5x1020 cm-3 can be maintained.
[0066] In an embodiment, the doping level of the drain (NDRAIN) and substrate (NSUBST) can be maintained as 1x1020 and 1x1016 respectively in the exemplary device 300.
[0067] FIG. 4A to FIG. 4C illustrate exemplary cross sectional details of the fin enabled area scaled Tunnel Field Effect Transistor 300 along sections C1, C2 and C3 respectively in accordance with embodiments of the present disclosure. FIG. 4A depicts a horizontal cross section along the cross section plain C1, wherein overlap of the epitaxial layer 402 over the source 306 is shown as LOV. The epitaxial layer can start from edge of the drain 308 and overlap the source 306. Further, the lightly doped epitaxial region can wrap the fin structure 302 over the three faces of the fin 302. The epitaxial region can be wrapped from three directions by a gate stack dielectric and metal stack, which enables channel formation in the epitaxial region and enhances tunneling from source 306 to the channel. In an aspect, the epitaxial region hosts the channel or inversion layer and tunneling takes place from the source 302 to epitaxial region (vertical tunneling) when gate voltage is applied. In an aspect the disclosed device architecture improves the tunneling cross-sectional area, reduces the tunneling barrier while reducing the device foot print. Moreover, Fin structure 302 improves the control over the channel region with resultant improved OFF state behavior. The same also enhances electric field under ON-state condition and increases the drive current. Smaller foot print, higher ON current and improved sub-threshold operation increases the ON current per device foot print area and reduces the power dissipation.
[0068] In an embodiment, epitaxial layer region 402 can be engineered to further improve the device performance. ON current improvement by increasing source doping can be limited up-to a certain doping concentration that is a function of Ge %. However, it can be improved further by suitably engineering the epitaxial doping (NEPI), its thickness (TEPI) and its overlap (LOV) 402 with source 306. An increased doping of the epitaxial region 402 can result in higher electric field (i.e. smaller tunneling width) across the tunnel junction. Moreover, increased doping of the epitaxial region 402 can bring conduction band in epitaxial region closer to the valance band of source, which can result in an increase in ON current at the cost of minimal leakage current increase that can be attributed to field enhanced trap assisted tunneling across the junction. Moreover, increasing the epitaxial region 402 doping can lower the conduction band edge relative to the source 306. Hence, above a given doping, as a function of thickness of the epitaxial region 402, leakage current increases exponentially.
[0069] The second engineering parameter of the epitaxial region 402 can include epitaxial region thickness (TEpi), which defines the tunneling width under ON state condition. In principle it is advisable to keep tunneling width as low as possible, in order to improve the ON current. However, lowering epitaxial region thickness to reduce tunneling width can cause serious mobility degradation due to an increased field enhanced scattering. These competing behaviors result in an optimum epitaxial region thickness for a given epitaxial region doping. At lower TEpi, current falls due to increased scattering. However, the same at higher TEpi can be attributed to increased tunneling width. It is worth highlighting that above a certain epitaxial region doping it is hard to deplete the channel completely by gate field, which is attributable to an OFF state tunneling between the source and the epitaxial layer. This can eventually result in an increased leakage for highly doped epitaxial region 402 with an increased TEpi.
[0070] The third engineering parameter of the epitaxial region 402 can include source to epitaxial region overlap length (LOV). In an aspect, the LOV can determine the tunneling area, thereby ON current of the device. Increasing LOV increases the ON current linearly, as the tunneling area increases linearly. However, for higher LOV, ON current increases sub-linearly, which can be attributable to an increased channel resistance of the device. Finally, at very high LOV, ON current saturates and can be limited by intrinsic channel 404 in series with tunnel junction. It is worth highlighting that OFF current also increases linearly due to an increased tunneling cross sectional area in which the field enhanced trap assisted tunneling dominates.
[0071] In the exemplary device, the epitaxial region thickness (TEPI), doping of epitaxial region (NEPI) and overlap (LOV) of the epitaxial region with the source has been maintained as 2 nm, 3x1019 cm-3 and 40 nm respectively.
[0072] FIG. 4A and FIG. 4B depict vertical cross sections along the cross section plain C2 and C3 respectively, wherein cross section of the fin duly wrapped by the epitaxial layer and gate is shown. Fin edge radius 422, fin width 452, and fin height 454 are known in the art to be important device design parameters for FinFETs. In an embodiment, electric field distribution for different edge top radius (rCur) 422 of the device and device’s drain current (ID) vs. gate voltage (VG) characteristics as a function of fin edge radius 422 were investigated. It was found that Fin edge radius 422 plays an important role in the proposed ASF-TFET design also. As the Fin edge radius 422 is decreased from 5nm to 2nm, the peak electric field at the source - channel interface near the Fin edge increases by 10%. This eventually results in a 10% increase in ON current without affecting the leakage characteristics. This depicts impact of an increased electrostatic control over the channel and the tunnel junction and justifies the importance of Fin enablement of Area Scaled TFET. Similarly, effect of Fin shape on the ID vs: VG characteristic of the proposed device was investigated and the device’s characteristic was found to be robust against the Fin shape. Further, it was found that the OFF current, threshold voltage and SS do not change as a function of Fin width 452 and Fin height 454. However, ON current improves significantly as the Fin width 452 and the Fin height 454 are scaled from 55nm and 90nm respectively to 15nm and 10nm respectively. This can be attributed to an improved electrostatic control over the tunneling interface as the Fin width 452 and Fin height 454 are scaled down. In the exemplary device width, height and edge radius of the fin have been maintained as 10 nm, 40 nm and 2 nm respectively.
[0073] FIG. 5 illustrates an exemplary conduction and valance band diagram 500 depicting band alignment and bending under OFF and ON state of the fin enabled area scaled Tunnel Field Effect Transistor 300 along section C4 (FIG. 4A) in accordance with embodiments of the present disclosure. At VG = 0 (dotted lines) zero alignment between the valence band of source and the conduction band of epitaxial region reveals an OFF state behavior, attributed to lack of tunnel state across the interface. When a gate voltage is applied (solid line) the conduction band of the epitaxial region aligns with the valence band of the source, allowing tunneling of electrons from source to the epitaxial region. These carriers are swept away, via the channel formed in the epitaxial region under the gate, by the drain electric field. In this way current flows from drain through epitaxial layer to source. In an aspect, the tunneling barrier width of the disclosed device 300 is less than the epitaxial layer thickness as TBarrier = TEpi - TInv, where TInv is inversion region thickness. This can allow greater control on the tunneling barrier width.
[0074] FIG. 6 and FIG. 7 illustrate exemplary graphs 600 and 700 respectively depicting comparison of input and output characteristics of the disclosed fin enabled area scaled Tunnel Field Effect Transistor 300 as against those of a planar area TFET and point (Gated P-i-N) TFET in accordance with embodiments of the present disclosure. The input (ID vs: VG) and output (ID vs: VD)characteristic extracted from 3D TCAD simulations, as presented in graph 600 and 700 respectively, clearly bring out the marked improved performance of the disclosed fin enabled area scaled Tunnel Field Effect Transistor 300 over its planar counterpart, i.e. the conventional line TFET devices or planar area scaled TFET devices. For a fair comparison, same design parameters as discussed and optimized in the preceding paragraphs were used on as applicable basis for both planar area scaled TFET and disclosed device 300. In order to justify the scalability and advantages of the proposed device, the comparisons were made for 20nm as well as 10nm channel length devices. Moreover, different Fin width devices were also used for the comparison. In all the cases an ON current improvement from 40% (LG=20nm) to 100% (LG=10nm) per unit electrical width was observed when compared to the planar area scaled TFET device.
[0075] In an aspect, the reported improvement is due to increased gate electric field in the overlap region 402. The increased gate field in the overlap region increases the tunneling probability because of the 3D nature of the gate, which enhances the electro static control of gate over the channel and overlap regions. In an aspect, the planar device unexpectedly shows an ON current reduction when channel length was scaled from 20nm to 10nm. This is attributed to an effective gate electric field lowering in the overlap region on account of increased drain field. However, on the other hand, drain field in the proposed device doesn’t significantly influence the gate electric field in the overlap region due to 3D gate and fully depleted channel. This leads to an ON current improvement by 100%, when scaled down to 10nm channel length.
[0076] In an aspect, for channel length scaling, the key challenge is OFF state source-to-drain tunneling which increases exponentially when channel length is scaled. To mitigate OFF state source-to-drain tunneling, an excellent electrostatic control of gate over the channel is required. A 15 times reduction in the source-to-drain leakage current for 10nm channel length device was observed which is attributed to an improved electrostatic integrity due to 3D nature of gate and fully depleted Fin. This allows scalability below 10nm channel lengths by keeping the leakage current unchanged. These observations prove that the planar device can’t be scaled below gate length of 20nm, whereas the proposed device has a potential to be scaled below 10nm gate lengths. A comparison of the output characteristics of the disclosed device 300 with its planar counterpart for gate length of 20nm and 10nm brings out lower ON resistance, improved saturation characteristics, higher ON current and 30% higher output resistance (1/gds) which brings out advantages of the proposed device compared to its planar counterpart.
[0077] FIG. 8 illustrates an exemplary process flow diagram 800 for fabrication of the disclosed fin enabled area scaled Tunnel Field Effect Transistor in accordance with embodiments of the present disclosure. In an embodiment, the method can include the steps of, at 802, patterning the fin and at step 804, depositing a dummy gate stack and forming a spacer. At step 806, the method can be configured to implant source and drain and perform their annealing, and at step 808, carrying out silicidation. At step 810, the method can involve removing the dummy gate stack and the spacer, and at step 812, growing an epitaxial layer with in-situ doping, and then at, step 814, depositing a gate stack. Further, at step 816, the method can involve depositing source, drain and gate contacts, and finally, at step 818 can include depositing first interlayer dielectric and Chemical mechanical polishing (CMP). In an aspect, the disclosed method can use gate last process, and low temperature local epitaxial growth process of standard FinFET CMOS process line and does not require any quantum technological jump from the existing infrastructure and maintains continuity with the present day technology.
[0078] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.
ADVANTAGES OF THE INVENTION
[0079] The present disclosure provides an efficient FET with lower leakage and high drive current for various miniaturized electronic circuits such as low power – high performance wireless systems.
[0080] The present disclosure provides a FET that can operate with supply voltage as low as 0.3 – 0.4V without a loss of performance.
[0081] The present disclosure provides a novel Fin enabled vertical or area scaled tunneling FET for sub-10nm channel length operation.
[0082] The present disclosure provides a Gate-field aligned tunneling in Fin-based architecture, which improves ON current due to increased electric field and band alignment.
[0083] The present disclosure provides a 3D Fin-based architecture for increased gate control over the tunneling region.
[0084] The present disclosure provides an improved sub-threshold slope and OFF current by increased gate control over tunneling region and channel, respectively.
[0085] The present disclosure provides a method to fabricate the disclosed Fin enabled area scaled tunnel FET that does not require any quantum technological jump from the existing infrastructure and maintains continuity with the present day technology.