Description:RELATED APPLICATIONS
[0001] This patent application is related to India Patent Application No. 202044041620, filed on 25 September 2020, entitled “ FLEXIBLE ON-DIE FABRIC INTERFACE”.
[0002] This application claims benefit to U.S. Provisional Patent Application Serial No. 62/944,773, filed December 6, 2019, the disclosure of which is considered part of and is hereby incorporated by reference in its entirety in the disclosure of this application.
[0003] This application claims benefit to U.S. Non-Provisional Patent Application Serial No. 16/914,327, filed June 27, 2020, the disclosure of which is considered part of and is hereby incorporated by reference in its entirety in the disclosure of this application.

FIELD
[0004] This disclosure pertains to computing system, and in particular (but not exclusively) to point-to-point interconnects.

BACKGROUND
[0005] Advances in semi-conductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a corollary, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple cores, multiple hardware threads, and multiple logical processors present on individual integrated circuits, as well as other interfaces integrated within such processors. A processor or integrated circuit typically comprises a single physical processor die, where the processor die may include any number of cores, hardware threads, logical processors, interfaces, memory, controller hubs, etc.
[0006] As a result of the greater ability to fit more processing power in smaller packages, smaller computing devices have increased in popularity. Smartphones, tablets, ultrathin notebooks, and other user equipment have grown exponentially. However, these smaller devices are reliant on servers both for data storage and complex processing that exceeds the form factor. Consequently, the demand in the high-performance computing market (i.e. server space) has also increased. For instance, in modern servers, there is typically not only a single processor with multiple cores, but also multiple physical processors (also referred to as multiple sockets) to increase the computing power. But as the processing power grows along with the number of devices in a computing system, the communication between sockets and other devices becomes more critical.
[0007] In fact, interconnects have grown from more traditional multi-drop buses that primarily handled electrical communications to full blown interconnect architectures that facilitate fast communication. Unfortunately, as the demand for future processors to consume at even higher-rates corresponding demand is placed on the capabilities of existing interconnect architectures.

BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1 is a simplified block diagram illustrating an example embodiment of a system on chip (SoC) device.
[0009] FIG. 2 is a simplified block diagram of an example logical flow view of an example computing system.
[0010] FIG. 3 is a simplified block diagram illustrating an example flexible on-die fabric interface.
[0011] FIG. 4 is a simplified block diagram illustrating an example Compute Express Link (CXL) topology.
[0012] FIGS. 5A-5B are simplified block diagrams illustrating embodiments of a flexible on-die fabric interface.
[0013] FIG. 6 is a timing diagram illustrating signaling over a channel of an example flexible on-die fabric interface.
[0014] FIG. 7 is a timing diagram illustrating signaling over a channel of an example flexible on-die fabric interface including use of a blocking signal.
[0015] FIG. 8 is a timing diagram illustrating credit return signaling over a channel of an example flexible on-die fabric interface.
[0016] FIG. 9 is a simplified block diagram illustrating a portion of a global channel of an example flexible on-die fabric interface.
[0017] FIG. 10 is a diagram illustrating an example initialization state machine for an example flexible on-die fabric interface.
[0018] FIG. 11 is a timing diagram illustrating initialization of an example flexible on-die fabric interface.
[0019] FIG. 12 is a timing diagram illustrating a first example of a disconnect flow in an example flexible on-die fabric interface.
[0020] FIG. 13 is a timing diagram illustrating a second example of a disconnect flow in an example flexible on-die fabric interface.
[0021] FIGS. 14A-14B are flow diagrams illustrating example techniques for signaling using an example flexible on-die fabric interface.
[0022] FIG. 15 illustrates an embodiment of a block diagram for a computing system including a multicore processor.
[0023] FIG. 16 illustrates another embodiment of a block diagram for a computing system including a multicore processor.
[0024] FIG. 17 illustrates an embodiment of a block diagram for a processor.
[0025] FIG. 18 illustrates another embodiment of a block diagram for a computing system including a processor.
[0026] FIG. 19 illustrates an embodiment of a block for a computing system including multiple processors.
[0027] FIG. 20 illustrates an example system implemented as system on chip (SoC).

DETAILED DESCRIPTION
[0028] In the following description, numerous specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and micro architectural details, specific register configurations, specific instruction types, specific system components, specific measurements/heights, specific processor pipeline stages and operation etc. in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the embodiments of the present disclosure. In other instances, well known components or methods, such as specific and alternative processor architectures, specific logic circuits/code for described algorithms, specific firmware code, specific interconnect operation, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expression of algorithms in code, specific power down and gating techniques/logic and other specific operational details of computer system haven’t been described in detail in order to avoid unnecessarily obscuring the present disclosure.
, Claims:1. An apparatus comprising:
agent circuitry to support a set of coherent interconnect protocols, and
an interface to couple to an interconnect fabric, wherein the interconnect fabric is configured to support the set of coherent interconnect protocols, and
the interface comprises:
a global channel to use a first plurality of physical lanes, wherein the global channel is to communicate control signals to support the interface;
a request channel to use a second plurality of physical lanes, wherein the request channel is to communicate messages associated with requests to the other agents of the fabric;
a response channel to use a third plurality of physical lanes, wherein the response channel is to communicate messages associated with responses to other agents of the fabric and the responses comprises responses without payload data; and
a data channel to use a fourth plurality of physical lanes, wherein the data channel is to communicate messages associated with data transfers to other agents on the fabric, wherein the data transfers comprise payload data.