This invention relates to data acquisition systems for use with flight data
recorders and, more particularly, to flight data acquisition units for receiving flight data
signals in a variety of signal forms.
BACKGROUND OF THE INVENTION
Flight data recorders are monitoring and recording instruments, carried aboard
an aircraft, which systematically monitor and store the instantaneous values of various
aircraft parameters. Early recorders were analog electromechanical devices which
periodically marked, in analog form, the value of a given airplane parameter on a
moving wire or other permanent storage medium. The time of occurrence of the
parameter was also suitably scribed into the medium opposite the mark for the sensed
parameter. Subsequently, digital flight data recorders have been developed which
operate by converting each analog aircraft parameter into a corresponding digital signal,
and storing the digital signals on a permanent storage medium such as magnetic tape.
The numerous mechanical parts employed in the analog and digital type
electromechanical flight data recorders have rendered such units expensive to construct
and bulky in design, requiring periodic maintenance of the mechanical parts. In addition,
extraction of the stored data from these data recorders requires physical removal of the
storage medium.
The development of solid state memory devices, such as electrically erasable
read-only memory, has led to the design of all solid state flight data recorders. The solid
state flight data recorders commonly employ a data acquisition system (DAS) which
receives and processes the various aircraft input signals to be monitored and stored
under the control of a central processing unit (CPU). The analog signals are converted
to digital signals by the DAS and, under CPU control, are passed over a data bus to the
solid state memory devices. Programming within the CPU controls the processing of
input airplane signals to corresponding digital signals through the DAS and the
subsequent transference of these digital signals to controlled locations in the solid state
memory.
The signals representative of monitored aircraft parameters are typically either
discrete level signals or analog signals. Discrete signals are typically switch positions
Annexure‐II
and produce either a high or a low level output depending upon the status of the
particular switch. A typical example in an aircraft is a squat switch, which indicates
whether or not a load is being borne by the landing gear.
Further, it is desirable to conform the flight data recorder such that it is capable of
being conveniently modified to operate in any one of several different types of aircraft.
To this end, the DAS is preferably configured such that its inputs may be assigned by
the CPU to handle any analog or discrete input signal. Further, the levels of the various
signals at the inputs of the DAS must often be sealed for proper processing within the
DAS. For example, inasmuch as all input signals are analog-to-digital (A/D) converted,
the DAS typically includes a conventional A/D converter. The accuracy of an A/D
converter is a function of the signal level applied at the input to the converter. To
minimize A/D converter errors, therefore, it is essential that each aircraft parameter
sensor signal be scaled before being applied to the A/D converter. In order to assure a
universal flight data recorder design, the scaling factors applied
SUMMARY OF PRESENT INVENTION
The present invention, therefore, is directed to a data acquisition system for use
in a flight data recorder. An aspect of the present invention is the ability of the data
acquisition system to process a set of parameter sense signals in response to a single
CPU request. In this way, integrity of multiple signal sensor data is assured and
overhead on CPU operation is reduced.
A further aspect of the invention is the universal application of the present data
acquisition system. Analog, Synchro, Frequency or Discrete aircraft parameter signals
may be assigned to any of the multiple data acquisition system inputs under CPU
control. Further, the DAS is responsive to CPU control to vary the scaling applied to
each input signal.
Briefly, according to the invention, a data acquisition system for an aircraft flight
data recorder is responsive to a central processor unit (CPU) for selectively processing
a plurality of input signals. The data acquisition system comprises a multiplexer which
outputs selected sets of the input signals, with each selected input signal set being
output responsive to a corresponding address command signal. Logic is responsive to a
single command from the CPU for producing each address command signal. Each
signal in a selected signal set is processed by provided processing means.
Annexure‐II
FDAU contains signal processing electronics whose role is to acquire the signals.
Acquired data is converted into digital data & send to Data Recorder Unit (DRU) through
Harvard Bi phase link (Arinc 573/717 Serial Interface) for further processing.
The Main functions of Data Acquisition System are:
• Acquisition/Conversion of Analogue, Frequency, Discrete, & Synchro & MIL-
1553B aircraft parameters into a suitable digital form for recording the same
in Protected Memory Module (PMM) by DRU unit.
• Generation of Harvard Bi Phase data for communicating with DRU.
• Built in self-test to verify correct operation of the FDAU.
• Conversion of Aircraft’s 28V DC supply to stabilized DC power of 5V, ±15V
and +5V excitation to operate the unit.
The FDAU contains the following electronics modules.
1. FDAU Processor Module (FPM)
2. Analog & Synchro Acquisition Module (ASAM)
3. Frequency & Discrete Acquisition Module (FDAM)
4. Power Supply Module (PSM)
5. FDAU Mother Board
Preferably, the data acquisition system includes digital memory for storing each
analog-to-digital converted instantaneous value of a signal in a selected signal set. The
controller produces an interrupt signal to the CPU upon all of the analog-to-digital
converted instantaneous values of the signals in a selected signal set being stored in
the digital memory. Preferably, the logic circuit responds to a single CPU command
signal to:
(a) Produce a predetermined address command signal such that the multiplexer outputs
the set of selected input signals,
(b) Produce predetermined gain control command signals such that each signal in a
selected signal set is amplified by a predetermined gain factor, and
(c) Activate the controller such that the analog-to digital converted instantaneous value
of each signal in a selected signal set is loaded into the digital memory.
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the present invention will become more apparent
and descriptive in the description when considered together with figures/flow charts
presented:
Figure 1: is a Block Diagram of Flight Data Acquisition Unit (FDAU)
Figure 2: is a Block Diagram of FDAU Processor Module (FPM)
Figure 3: is a Block Diagram of Analog & Synchro Acquisition Module (ASAM)
Figure 4: is a Block Diagram of Frequency & Discrete Acquisition Module (FDAM)
Figure 5: is a Block Diagram of Power Supply Module (PSM)
Annexure‐II
DETAILED DESCRIPTION
Figure: 1 is a block diagram illustrating the principal components of a flight data
acquisition unit of FDR. A flight data recorder is carried aboard an aircraft and
systematically monitors and stores information related to aircraft parametric data. Such
recorded data may be analyzed at a subsequent time to yield information related to the
source of an aircraft mishap, or simply to provide a diagnostic and information tool as to
the aircraft's performance.
The flight data recorder must be capable of receiving and processing three
distinct types of parametric data. The first data grouping is analog data. The analog data
may be any one of four distinct types. Information related to an angle, such as engine
nozzle position, is commonly provided by a Synchro sensor. Each Synchro sensor
typically provides three active signals which are phase and amplitude related to a
reference signal (commonly 400 Hz in aircraft). By processing the three active signals in
the known manner, the angle of the parameter being monitored is derived. A second
type of analog data is AC ratiometric data. AC ratiometric data is commonly provided in
aircraft by a sensor known as a linear variable differential transformer (LVDT).
Discrete data are signals which assume either a low or a high state in response
to the status of the parameter being monitored. Such signals are, commonly, produced
by switches, an example being the aircraft squat switch which produces a discrete
output indicating whether or not the aircraft landing gear is under load.
Both the analog and the discrete data are processed within the flight data
recorder through a data acquisition system. The function of the data acquisition system
is to receive each analog and discrete input signal and, under external control,
sequentially convert each input signal to a corresponding digital signal. The digital
signals are then output on a system bus. The data acquisition system is described in
detail hereafter.
FDAU Processor Module (FPM):
The FDAU Processor Module (FPM) is the core of the FDAU. It acquires Analog,
Frequency, Discrete, and Synchro signals through other I/O Cards in the FDAU. These
I/O cards are interfaced with the processor’s data, address and control bus, which are
brought out on the PCB edge connector. The processor card also exchanges certain
data and configuration parameters through the MIL-STD 1553-B and transmit these
data along with acquired a/c data (Analog, Discrete, Frequency & Synchro) to DRU
through ARINC717 Interface.
The module consists of on board memory of FLASH EPROM and 512KB Static
RAM for code and data respectively and NVRAM for storing Sorties information and
MIL-STD 1553-B RT’s memory is also mapped on to the micro-controller’s memory
space.
Annexure‐II
An RS-232 serial asynchronous interface is provided to enable communication
with a Host computer. This link may be used for debugging as well as downloading
application software.
The card also supports a serial ARINC-717 interface, which can be programmed
for various pre-determined data rates.
A mini ACE 1553-B RT device is used to support communication over the MILSTD
1553-B data bus interconnects. This device sits directly on to the micro-controller’s
bus. The Channel ‘A’ and Channel ‘B’ signals of the mini ACE device are interfaced to
the MIL-STD 1553-B bus through a pair of pulse transformers. The RT address lines are
accessible externally, so that the address can be easily configured.
The module features a full-buffered system for external bus expansion for
interfacing other IO modules using 16-bit bi-directional buffers.
The block diagram of FDAU Processor Module (FPM) is placed at Figure – 2.
Features of FPM:
• Motorola micro controller @ 16 MHz
• Onboard oscillators for micro controller, MIL-1553B and UART
• Flash EPROM and SRAM
• 16-bit memory access
• One Asynchronous serial port with RS232 interface
• The Card is ARINC-717 interface compliant with Harvard Bi-phase
standard.
• One MIL-STD-1553B interface
• 16-bit Bus expansion
Analog & Synchro Acquisition Module (ASAM):
ASAM is used both for Analog as well as Synchro signal processing. It takes
aircraft parameters as input and converts the selected parameter into 12-bit digital data.
For analog parameters, Analog to Digital Converter is carried out while Synchro to
digital converter converts Synchro parameters to digital. It can handle analog input data
of both Uni-polar & Bi-polar type.
This module provides input impedance buffer for analogue DC aircraft parameter,
which are an integral part of the analog multiplexers & multiplex the signals into a
common data bus.
The Block diagram of the ASAM is presented at figure – 3.
Features of ASAM:
• Twenty Three Analog signal inputs
• 12-bit ADC
• Differential Multiplexers
Annexure‐II
• Signal conditioning
• Built In Test for ASAM
• Synchro to Digital Converter
• Resistance to Voltage converter (for OAT Parameter)
• Over Voltage & Spike Protection
Frequency & Discrete Acquisition Module (FDAM):
The discrete part of the module accept separate isolated inputs and convert them
into a serial data stream with TTL compatible level. The discrete parameters of the A/C
are fed through opto-couplers, which maintain isolation between the SSFDR and aircraft
sensors.
The differential frequency signals are fed to signal conditioning and convert it to
single ended. These frequencies are multiplexed by analog multiplexer. This singleended
signal is fed to voltage comparator (Schmitt Trigger), which converts into TTL
logic pulses. This signal then fed to the Flip-Flop that is used to gate “Freq Clock” pulse
to one of channel of TPU module of microcontroller for one period of selected frequency
signal. The Block Diagram of Frequency & Discrete Module is shown in Figure -4.
Features of FDAM:
• Discrete inputs
• Frequency inputs
• Signal Conditioning Circuits for Discrete & Frequency Signals
• Opto-Coupler Isolation for Discrete Signals
• In Built testing of Card.
• Spike Suppression
Power Supply Module (PSM):
The power supply module is a sub-assembly of Solid State Flight Data Recorder.
Its function is to convert an aircraft 28V DC supply into four outputs, which are
independently short circuit protected and jointly isolated from input. The nominal values
of the four outputs are +5V (1.2A), +15V (0.4A), -15V (0.34A), and +5V excitation
(1.2A).
This module accepts the 28V DC aircraft supply and feed to input over voltage
protection circuit, which is protected against over voltage. After over voltage protection,
capacitor & diode are used for reducing at the noise of input supply & prevent the
spikes. Then input signal is fed to EMI filter module which is specifically designed to
reduce the reflected input ripple current of DC/DC converters. After filtering, the signals
are feed to triple output DC-DC converter (5V,± 15V), & single output (+5V excitation)
DC-DC converter.
Annexure‐II
DC-DC Converter generated outputs are passed through capacitor filter to
reduce the noise at the output. DC-DC converter +15V is also passed through +5V IC
regulator circuit to set +5V excitation voltage.
The Block diagram for Power Supply Module is given at Figure-5.
FDAU Mother Board:
This is the main interfacing board for FADU hardware modules. All the PCB
mating female connectors reside on this board and each hardware module fits into each
respective mating connectors. Each connector is provided with separate lock to avoid
wrong insertion of cards. This also interfaces with the inputs and outputs from the
external unit connectors.

WE CLIAMS:-
Accordingly, the description of the present invention is to be considered as illustrative only and is for the purpose of teaching those skilled in the art of the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and exclusive use of all modifications which are within the scope of the appended claims is reserved. The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. FDAU for an aircraft flight data recorder responsive to a central processor unit (CPU) for processing a plurality of input signals to provide a digitally encoded signal representative of a selected set of input signals each time the CPU provides a simple command signal, said digitally encoded signal being used by said CPU for generation of recorded flight data information, said data acquisition system comprising:
Multiplexing means for outputting said selected set of said input signals, each selected input signal set being output responsive to a corresponding address command signal;
Logic means responsive to said single command from said CPU for producing each address command signal; and
Processing means for processing each signal in a selected signal set to supply said digitally encoded signal representative of said selected set of input signals.

2. The FDAU of claim 1, wherein said processing means comprises: gain controlled amplifier means responsive to gain control command signals from said CPU for amplifying each signal in a selected signal set by a predetermined gain factor; Controller means for pre-determinedly coupling the instantaneous value of each signal in the selected signal set to the input of said analog-to-digital converter means; and means for supplying said corresponding signals at the output of said analog-to-digital converter means as said digitally encoded signal representative of said selected set of input signals.

3. The FDAU of claim 2, wherein said controller means produces an interrupt signal to said CPU upon all the signals in a selected signal set being stored in said digital memory means.

4. The FDAU of claim 4, wherein said logic means responds to a single CPU command signal to:

(a) produce a predetermined address command signal such that said multiplexing means outputs said set of selected input signals,

(b) produce predetermined gain control command signals such that each signal in a selected signal set is amplified by a predetermined gain factor, and

(c) Activate said controller means such that the analog-to-digital converted instantaneous value of each signal in a selected signal set is loaded into said digital memory means.

5. A FDAU for an aircraft flight data recorder of the type that selectively records flight data information, said FDAU being responsive to a central processor unit (CPU) for selectively processing multiple input signals and supplying to said CPU for utilization in selective recording of flight data information a digital signal representative of a selected set of said input signals.

6. The FDAU of claim 4, further comprising: digital memory means for storing each analog-to-digital converted instantaneous value of a signal in a selected signal set; and wherein said controller means produces an interrupt signal to said CPU upon all of the analog-to-digital converted signals in a selected signal set being stored in said digital memory means.

7. The FDAU of claims 7, further comprising: logic means responsive to a single CPU command signal for:
(a) Producing said address command signals applied to said multiplexing means for selection of said selected sets of selected input signals,
(b) producing said applied gain control command signals such that each signal in a selected signal set is amplified by a predetermined gain factor, and
(c) Activating said controller means such that the analog-to-digital converted instantaneous value of each signal in a selected signal set is loaded into said digital memory means.

8. A FDAU as claimed in any of the preceding claims wherein a dedicated watchdog is used and it has to be triggered periodically by software to avoid occurring of Watchdog Timeout event.

9. A FDAU as claimed in any of the preceding claims wherein an RS-232 serial asynchronous interface is provided to enable communication with a Host PC, a serial ARINC-717 interface, which can be programmed for various pre-determined data rates.

10. A FDAU as claimed in any of the preceding claims wherein a CPLD is used to provide glue logic and Harvard Bi-phase encoding, wherein a mini ACE 1553-B RT device is used to support communication over the MIL-STD 1553-B data bus interconnects. The RT address lines are accessible externally, so that the address can be easily configured, a supervisory circuit is used to provide highly reliable reset to the system. ,TagSPECI:As per Annexure-II