Description:The present application claims priority to U.S. Non-Provisional Patent Application No. 17/484,409 filed on 24 September 2021 and titled “FLOW ENHANCEMENT STRUCTURE TO INCREASE BANDWIDTH OF A MEMORY MODULE” the entire disclosure of which is hereby incorporated by reference.

FIELD
This disclosure relates to memory modules and in particular to cooling a memory module in a computer system.

BACKGROUND
A memory module is a printed circuit board on which memory integrated circuits (“chips”) are mounted to another printed circuit board, such as a motherboard, via a connector (also referred to as a “socket”). The connector is installed on the motherboard and a memory module is inserted into the connector. The connector enables interconnection between a memory module and a circuit on the motherboard. A dual in-line memory module (DIMM) has separate electrical contacts on each side of the memory module.
The DIMM can include dynamic (read/write) memory, a volatile read/write memory in which the cells require the repetitive application of control signals generated inside or outside the integrated circuit to retain stored data. Each repetitive application of the control signals is normally called a refresh operation or cycle.
A refresh time interval is the time interval between the beginnings of successive signals that are intended to restore the level in a dynamic memory cell to its original level. The refresh time interval is determined by the system in which the dynamic memory operates. A maximum value is specified that is the longest interval for which correct operation of the dynamic memory is to be expected.
The maximum time interval between refresh operations is typically in the range of milliseconds for dynamic (read/write) memory, for example, Dynamic Random Access Memory (DRAM) and is dependent on the ratio of charge stored in memory cell capacitors to leakage currents. Leakage currents increase with temperature, so the time interval between refresh operations is decreased as the temperature increases. For example, the time interval between refresh operations is typically decreased by a factor of 2 (that is, the refresh rate is increased) when the temperature of the DRAM exceeds 85 °C (185 °F).
Refresh operations in DRAM consume power and reduce bandwidth for memory access (read/write operations). For example, the increase in power consumption for a 16 Gigabit (Gb) Quad Rank Load Reduced Double Data Rate Dual In-Line Memory Module with synchronous dynamic random access memory (SDRAM) devices that are compatible with memory technologies such as DDR5 (Double Data Rate version 5, originally published in July 2020) when the time interval between refresh operations is decreased by a factor of 2 could be about 5 Watts.
, Claims:1. A memory subsystem comprising:
a channel structure, the channel structure comprising:
a horizontal support member; and
a flow enhancing structure, the flow enhancing structure having one end connected to the horizontal support member; and
at least two memory modules, a first memory module and a second memory module, each of the first memory module and the second memory module comprising a plurality of memory integrated circuits, the horizontal support member to extend from a top of the first memory module to the top of the second memory module, the other end of the flow enhancing structure to extend into a memory module channel between the first memory module and the second memory module, the flow enhancing structure to disrupt airflow through the memory module channel to increase heat transfer from a first memory integrated circuit near the flow enhancing structure.

2. The memory subsystem of Claim 1, wherein the first memory integrated circuit has a higher temperature than another of the plurality of memory integrated circuits closer to a source of the airflow.

3. The memory subsystem of Claim 2, wherein the memory modules are dual in-line memory modules and the memory integrated circuits are a Dynamic Random Access Memory.

4. The memory subsystem of Claim 1, wherein the flow enhancing structure is a cylinder.

5. The memory subsystem of Claim 1, wherein the flow enhancing structure is in the center of the memory module channel.

6. The memory subsystem of Claim 1, the channel structure comprising a second a flow enhancing structure to extend into the memory module channel between the first memory module and the second memory module.

7. The memory subsystem of Claim 1, comprising a third memory module, the horizontal support member to extend from the top of the first memory module to the top of the third memory module.

8. The memory subsystem of Claim 1, wherein the memory integrated circuits are a non-volatile memory.

9. A system comprising:
a memory subsystem comprising
a channel structure, the channel structure comprising:
a horizontal support member; and
a flow enhancing structure, the flow enhancing structure having one end connected to the horizontal support member; and
at least two memory modules, a first memory module and a second memory module, each of the first memory module and the second memory module comprising a plurality of memory integrated circuits, the horizontal support member to extend from a top of the first memory module to the top of the second memory module, the other end of the flow enhancing structure to extend into a memory module channel between the first memory module and the second memory module, the flow enhancing structure to disrupt airflow through the memory module channel to increase heat transfer from a first memory integrated circuit near the flow enhancing structure; and
a display communicatively coupled to a processor to display data stored in the memory integrated circuits.

10. The memory subsystem of Claim 9, wherein the first memory integrated circuit has a higher temperature than another of the plurality of memory integrated circuits closer to a source of the airflow.

11. The memory subsystem of Claim 10, wherein the memory modules are dual in-line memory modules and the memory integrated circuits are Dynamic Random Access Memory.

12. The memory subsystem of Claim 9, wherein the flow enhancing structure is a cylinder.

13. The memory subsystem of Claim 9, wherein the flow enhancing structure is in the center of the memory module channel.

14. The memory subsystem of Claim 9, the channel structure comprising a second a flow enhancing structure to extend into the memory module channel between the first memory module and the second memory module.

15. The memory subsystem of Claim 9, comprising a third memory module, the horizontal support member to extend from the top of the first memory module to the top of the third memory module.

16. The memory subsystem of Claim 9, wherein the memory integrated circuits are non-volatile memory.