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Fpga Based Graphic Processing Device

Abstract: The graphic processing device accepts data inputs from any data processing device and generates the graphical and alpha-numeric diplay information for display equipments. It is desinged around the concept of flexible and customisable digital graphic processing.

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Patent Information

Application #
Filing Date
28 December 2014
Publication Number
27/2016
Publication Type
INA
Invention Field
COMPUTER SCIENCE
Status
Email
Parent Application

Applicants

Hindustan Aeronautics Limited
Hindustan Aeronautics Limited, Avionics Division, P.O. Korwa, Amethi, Pin-227412, UP, India

Inventors

1. LEELADHAR ARJA
Hindustan Aeronautics Limited, Avionics Division, P.O. Korwa, Amethi, Pin-227412, UP, India

Specification

FIELD OF THE INVENTION
The field of this invention is design of System on Chip (Soc) as a flexible
device to generate a user-need specific, resource optimized graphic
processing device using hardware description languages and necessary
software components.
BACKGROUND OF THE INVENTION
Generation of synthetic graphic symbology has attained apex importance in
various fields of electronics including Human Machine Interface (HMI) design.
The graphic processing infrastructure available in open market is highly
monochromatic that it is not adoptable in a cost-resource effective manner for
across the spectrum of graphic applications. Hence forth, this invention
bridges the gap with a flexible, user-level custom system on chip solution for
graphic processing for various strata of graphic requirements.
SUMMARY OF PRESENT INVENTION
In accordance with one aspect of present invention, it interacts with the data
processing device with a shared memory resource.
In accordance with second aspect of present invention, it computes the
graphical information from digital data.
In accordance with another aspect of present invention, it computes alphanumeric
display information from digital data.
In accordance with yet another aspect of present invention, it provides video
output for display panel devices.
Annexure‐II
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the present invention will become more
apparent and descriptive in the description when considered together with
figures/flow charts presented:
Fig. 1 is a representation of block level design of graphic processing device.
Fig. 2 is a representation of data exchange protocol with shared memory
resource between data processing device and graphic processing device.
Fig. 3 is an event flow diagram for the generation of video data
DETAILED DESCRIPTION
Introduction:
Graphic processing or computation of digital graphic data requires analytical
as well as quantitative details of the object to be displayed. It needs high
amount data computation capacity to generate the display frame from
mathematical algorithms and models. A graphic processing device is
expected to perform these heavy data computations and generates the video
output in displayable format.
Detailed design:
The graphic processing device is designed around an FPGA (Field
Programmable Gate Array).(Refer fig 1) It receives the information to be
displayed from the data processing device which can be internal to the FPGA
or external. It uses shared resources with data processing device to exchange
communication. A dual port static random access memory is used for this
purpose.
All the common primitives which are essential for 2-dimensional synthetic
graphic generation are analyzed. These primitives include lines, polygons,
circles, circle derivatives and conic sections. Mathematical algorithm is
adopted for all the shapes in a computational prospective.
A data exchange protocol is designed to facilitate the communication between
data processing device and graphic processing device. (Refer fig 2) All the
global information is stored in a series of configurable memory regions. This
information can be customized as per the graphic processing requirements.
The communication will be initiated by the data processing device by
providing necessary digital information to display at a configurable memory
Annexure‐II
region. Graphic processing devices respond by reading the data and
acknowledging the data processing device.
Data received by the graphic processing device further analyzed to determine
the number of objects to be displayed and co-ordinates of the each object as
per a fixed reference point on the screen.
All the graphic data will be computed using computational algorithms. Further
the computed data will be converted into a stream of image frames (video
signal) which can be received by any standalone display device. (Refer fig 3)

WE CLAIMS:-
Accordingly, the description of the present invention is to be considered as illustrative only and is for the purpose of teaching those skilled in the art of the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and exclusive use of all modifications which are within the scope of the appended claims is reserved.

We Claim that:

1. The graphic processing system comprises, i) A field programmable gate array logic device hardware ii) functional packages of processing logic cores iii) Configuration details in hardware description language iv) electronic circuit elements v) logic information associated with the system

2. The system as in the claim1, is capable of generating synthetic graphic object information for lines, polygons, circle, circle derivatives and conic sections.

3. The system as in claim1, is capable of interfacing with any external data processing device with memory access capability

4. The system as in claim 1,is capable of generating graphic information for any pre-determined symbol having bitmap information.

5. The system as in claim 1, is capable of capable of generating parallel digital RGB video signal with configurable bpp(bits per pixel)

6. The system as in claim 1, is capable of capable of generating parallel digital RGB video signal with configurable display resolution in horizontal and vertical dimensions

7. The system as in claim 1, is capable of generating parallel digital RGB video signal for any standalone display equipment with necessary interface. ,TagSPECI:As per Annexure-II

Documents

Application Documents

# Name Date
1 drawings.pdf 2014-12-30
1 Specification.pdf 2014-12-30
2 FORM3MP.pdf 2014-12-30
2 form5.pdf 2014-12-30
3 FORM3MP.pdf 2014-12-30
3 form5.pdf 2014-12-30
4 drawings.pdf 2014-12-30
4 Specification.pdf 2014-12-30