FIELD OF INVENTION
This invention relates to High Frequency Three Phase Inverter. More particularly, the present invention relates to a FPGA based three phase high frequency inverter. The present invention provides a single chip solution for implementation of various complex digital control functions in hardware.
BACKGROUND and PRIOR ART
A conventional three-phase inverter aims to transform DC power to three-phase AC power to drive a load. The three-phase AC inverter consists of a plurality of transistors coupled in parallel. These transistors are generally insulated gate bipolar transistors (IGBTs). The gates of the transistors are controlled by first PWM control signals, the upper and lower arm control signals corresponding respectively to R, Y and B phases. Taking the R phase for an example, the transistors are driven by gate drivers.
The inverter described above still has some technical problems, such as current distribution, malfunctioning, low efficiency and capacity. Details on these are elaborated as follows:
Since the static and dynamic characteristics of IGBTs are not always the same, controlling with direct parallel operation results in different current flowing through two or more IGBTs when turned on in a static condition or switching dynamically. As a result, current distribution in the IGBTs is not equal. Under some conditions, the IGBTs could overheat and burn out. As the transistors use the same set of control signal to pass through gate control circuits and drive the IGBTs, therefore if one IGBT is opened or the actuation circuit is abnormal (such as signal interruption), in terms of the parallel structure, as long as one IGBT is turned on normally, the overall output actuation is not affected. The actual load current waveform is also the same as the normal signal. Hence, malfunctioning of the IGBT cannot be detected, and also protection of the IGBT is difficult. Further, Isolation of the malfunction is also not easy. Moreover, when one IGBT malfunctions, excessive current could flow through

another IGBT and When the malfunction is not detectable, the other IGBT could burn out. Thus, it lacks of reliability.
The power loss of the general inverter can be classified as conduction loss and switching loss (including turn-on losses and turn-off loss). In general, a higher switching frequency of the IGBT has a more desirable output waveform, but it is associated with greater power loss and lower efficiency. For an inverter of a greater capacity, to maintain a high switching frequency to achieve a desired waveform output is difficult.
In term of capacity, the safety current of the IGBT must be reduced as the switching frequency increases. Moreover, the dividing current is not equal when the IGBTs are coupled in parallel. Hence, the total safety current reduces. Pulse width modulator (PWM) inverters are used in three phase bridges, H-bridges, and half-bridge configurations. The bus capacitors, typically electrolytic, consist of two or more capacitors connected in series or parallel that is fed from a rectifier or actively switched front end section.
FPGA are semiconductor devices consisting of programmable logic components which can be configured and re-programmed to perform wide range of functionalities of digital circuits. A computational architecture can be implemented inside the FPGA by interconnection of the logic blocks using programmable interconnect resources. The complexity of these digital circuits varies from simple logic gates to complex combinational and sequential circuits.
The ability of re-programming the FPGA allows a user to not only design customized architectures but also gives access to more complex integrated circuit designs without getting involved in high engineering and development costs associated with ASIC development. It also provides the scope for improvement or any modifications that are required after the completion of the design.
Field programmable gate arrays (FPGA) is making considerable inroads into the digital signal processing marketplace. They are increasingly growing because of the

shorter development time involved in providing a complete digital control solution which in turns leads to faster time-to-market.
Prior-art modular formats are about the conventional microprocessors and digital signal processors. The DSP/microcontrollers are based on architectures having limited generic, pre-defined functionality and fixed peripheral set. The sequential execution of the code is another major drawback in such devices which leads to time sharing of the peripherals and other resources, thus resulting in considerable drop of performance.
With FPGA there is no such fixed architecture present instead customized and concurrent architectures are implemented in order to achieve high degree of parallelism. Algorithms are implemented directly in hardware using these reconfigurable logic gates. This not only enhances the timing and performance but also eradicates any architectural compromises present in conventional microcontroller or DSP based systems. FPGA also provides the advantage of future upgradation as per the requirement of the user. New peripherals as well as architectural changes can be implemented in the FPGA to meet new standards and protocols. Therefore, due to this backdrop DSP/microcontroller based systems become obsolete as they fail to match up the dynamic needs and changing standards.
Reference to be made to a publication by Yogesh Aggarwal, Electronics For You, pp 116-122 , August 2006, which discloses FPGA design of a controller for three-phase inverters. It is a universal designed controller for three-phase inverters. The chip is designed in very high-speed integrated hardware description language (VHDL) and implemented on a field-programmable gate array (FPGA).
Reference may also be made to a publication by M. N. Mdlsa et.al, American Journal of Applied Sciences Volume 4 Issue 8, pp 584-586, 2007. This discloses FPGA based SPWM bridge inverter. This explains methodology to generate sinusoidal pulse width modulation (SPWM) signal using FPGA technology with number of switching pulses 38, switching frequency 2 KHz and switching time 500 us.

Further, reference may be made to a publication by S. Mekhilef, Engineering e-Transaction, Volumel, No 2 pp 40-45, December 2006, disclosing Xilinx FPGA based multilevel PWM single phase inverter. A Xilinx FPGA based multilevel PWM single-phase inverter was constructed by adding bi-directional switches to the conventional bridge topology. The inverter can produce three and five different output voltage levels across the load.
Yet further, reference may be made to a publication by Kharrat M. W et.al, Microelectronics, 2001, ICM 2001 Proceedings, the 13th Annual Conference of the lEEE,_pp 185- 188 directing to FPGA based-IC design for inverter with vector modulation technique. This paper presents an application of a xilinx FPGA device, in the CX4000 family, producing Pulse Width Modulation (PWM) signals with the vector modulation technique for an IGBT inverter.
Reference may be made to a publication by Eftichios Koutroulis et.al, Journal of Systems Architecture, Volume 52, Issue 6, pp 332- 344, June 2006 relating to high frequency pulse width modulation implementation using FPGA and CPLD ICs. This paper explains the development of high-frequency PWM generator architecture for power converter control using FPGA and CPLD ICs. The resulting PWM frequency depends on the target FPGA or CPLD device speed grade and the duty cycle resolution requirements. The post-layout timing simulation results are presented, showing that PWM frequencies up to 3.985 MHz can be produced with a duty cycle resolution of 1.56%.
Now, reference may be made to a publication by Yokoyama T et.al, The 29th Annual Conference of the IEEE, Volume 1, Issue , 2-6 pp 180 - 185, November 2003 which discloses an instantaneous dead beat control for PWM inverter using FPGA based hardware controller. This article explains a new approach for real time digital feedback control of PWM inverter, in which an ideal instantaneous deadbeat control is realized without any sampling compensation method using FPGA based hardware controller.

Further, reference may be made to a publication by Lentijo, S, Power Electronics Specialists Conference (IEEE 35th Annual), Volume.5 pp 3588- 3592 June 2004 which discloses FPGA based sliding mode control for high frequency power converters. This paper explains the use of high switching speed power switches, which requires additional efforts in control development.
US patent no 7,274,243 is adaptive gate drive for switching devices of inverter. This inverter includes control circuitry having a field programmable gate array (FPGA) and includes power circuitry having a plurality of FETs for operating a switching device, such as a trench gate insulated gate bipolar transistor (IGBT device)
US patent no 6201720 relates to an apparatus and methods for space-vector domain control in uninterruptible power supplies. This invention provides power conversion methods which may improve phase regulation of polyphase AC voltages in the presence of load imbalances.
US patent no 7199622 is directed to an interleaving control type inverter. The inverter control structure of the invention employs a multi-phase frequency converter using triangular wave modulation or an inverter transforming DC to AC under a constant frequency and a constant voltage or an inverter transforming AC to DC. The alternating parallel control signal uses a triangular wave to determine the zero current switching point of the power transistor.
US patent no's 7126409 and 6838925 are three level inverter. This invention relates to a high efficiency three-level inverter apparatus containing both bipolar and field effect transistors.
CN101005211 is high frequency emergency power system. This belongs to high frequency inversion including fly back converter based charger, push-pull DC-DC boost converter and half bridge driver.

Thus most of the conventional system describes inverter using DSP/ controller. One of the inverter is using FPGA but it is a three level inverter. There needed a inverter which can eliminate the need of bulky transformer and can provide a single chip solution for implementation of various complex digital control functions in hardware.
With all the above discussed restrictions or limitations, it is essential to have improved solar cell array controller. The present invention provides FPGA high frequency three phase inverter. The present invention provides a single chip solution for implementation of various complex digital control functions in hardware and thereby drastically reducing the software overhead present in conventional microcontroller based systems and thus achieving better timing control.
OBJECT OF THE INVENTION
Primary object of the present invention is to provide field programmable gate arrays (FPGA) based high frequency inverter for generation of AC power signals from a DC source at the time of power failure of the AC line source to circumvent the above issues mentioned in the general inverter.
It is another object of the present invention to generate multiple pulse width modulated signals at different frequencies and duty cycles together with control signals for handling various power stages involved in high frequency inverter.
It is another object of the present invention to generate multiple pulse width modulated signals with dead band control using the FPGA for driving IGBT/MOSFETs in 3-phase H-bridge configuration.
It is still another object of the present invention to eliminate the need of external PWM controller required for maintaining constant DC bus output voltage of DC-DC converter by use of field programmable gate arrays.

It is another object of the present invention to generate fixed frequency pulse width modulated signals using FPGA for power supply circuit required for IGBT/MOSFET drivers without using dedicated control integrated circuit.
It is another object of the present jnvention is to provide FPGA based high frequency three phase inverter in which power supply circuit feeds and independently controls the critical power supply points in the system.
It is another object of the present invention to provide an inverter in which load conditions can be set/ programmed using an external computer.
It is another object of the present invention to replace micro-controller and DSP based systems by field programmable gate arrays, thus providing a single chip solution for implementation of various complex digital control functions in hardware and thereby drastically reducing the software overhead present in conventional microcontroller based systems and thus achieving better timing control.
It is another object of the present invention to provide control and generation of pulse width modulated signals for battery charger using the FPGA.
It is another object of the present invention to provide control for LCD/TFT and smart panel based display using FPGA for displaying the information to the user. This dedicated hardware control implementation eliminates any architectural or software compromises required for handling slow peripherals such as LCD display in the conventional micro-controllers.
Yet another object includes a power inverter system comprising IGBTs to provide AC wherein the regulated AC output is three-phase.
Another object is to provide a DC/DC converter system supplying DC power supply to different sections and drivers.

Another object is to provide a power inverter system which controls the operation of air conditioner or any other connected equipment based upon the ambient temperature of the telecom shelter and battery conditions, hence optimum usage of inverter battery and long backup from inverter.
Another object is to provide a power inverter system which controls the operation of the SMPS Power Plant based upon the battery status of the SMPS Power Plant hence long backup from the inverter and also good life of SMPS power plant battery bank.
Another object also provides a power inverter system which has additional generator start facility by giving command to generator through FPGA to optimize the use of generator available and also to make sure that the telecom site operation goes on uninterrupted.
Another object is to provide a power inverter system which diagnoses the problem in the inverter for example the status of the battery, battery life, overload, short circuit etc. and sends a SMS to the telecom site operator for remedial action.
Still another object is to provide a power inverter system wherein the unbalanced dividing current resulting from different IGBT characteristics can be resolved and the abnormal signal of one power transistor or gate driver may be detected easily through the current waveform.
Further object is to provide a power inverter system wherein the switching loss of the power transistor will be reduced, the overall efficiency will be increased, the failure rate of the inverter will be reduced and the total reliability will be increased.
Yet another object of the invention is to provide a power inverter system in paralleling mode which increases the capacity and reduces the overall cost of the system. The modular feature of this system greatly enhances the reliability, decreases the cost as compared to having an equivalent system to handle higher load rating.

Yet another object of the present invention is to provide future up-gradation by using FPGA which can be reprogrammed for any changes required in the hardware configuration of the control logic depending on the specific needs of the product.
Yet another object of the present invention is to provide a power inverter system in which IGBT's can be replaced by MOSFETs as per requirement.
Yet another object of the present invention is to provide a power inverter system in which FPGA communicates with display devices.
Yet another object of the present invention is to provide a power inverter system wherein battery equalizer unit and battery monitoring and management are provided inside the system.
SUMMARY
According to the present invention, a high frequency three phase inverter is provided in which micro-controller and DSP based systems are replaced by Filed Programmable Gate Arrays (FPGA). This invention provides a single chip solution for implementation of various complex digital control functions in hardware. The Space Vector Modulation PWM (SVM) controller is realized in hardware inside the FPGA in which High Frequency 3-Phase Inverter provides additional advantage of superior harmonic quality and large under modulation range that extends the modulation factor. The FPGA also communicates with user interface devices. The information to the user is also provided in the form of audio messages.
In an aspect of the present invention, a high frequency three phase inverter and control method is provided to facilitate high quality and low output total harmonic distortion operation of three phase power inverters. Three phase power generation is through single FPGA using PWM with space-vector modulation technique, thus eliminating the need for dual micro-controllers that are used in conventional systems.

The entire inverter function is controlled by the single field programmable gate array (FPGA), being used in the system. The inverter includes field programmable gate array (FPGA) for handling control operations and generation of multiple pulse width modulated signals. Dedicated hardware control logic is implemented inside the FPGA for handling switching devices of multiple power stages and also for achieving rest of the functionality of the high frequency inverter. Although isolated gate bipolar transistor (IGBT) power switches are the preferred embodiment in high voltage inverter applications, other power switches used in the lower voltage applications (FET's for example) are within the scope of the invention. These inverters have very high inrush bearing capability as compared to generators.
The three phase power inverter and control method constituting a system having power source, such as a three-phase configured AC source that connects to the charger section. The charging is being controlled by the custom designed charger controller in the FPGA which has programmable settings for battery charging voltage and charging current, temperature compensation, equalization charge control of battery bank. Heavy-duty charger with charging current ranging from 20A - 200A is provided to charge the batteries.
This inverter supports paralleling of multiple systems where in the load sharing between systems connected in parallel can be regulated. The PWM signals from each of the systems connected in parallel will be phase locked with the rest of the systems. Data signals in the paralleling block shall ensure that in an eventuality of a system failure, the load shall be shared by the rest of the systems as per available capacity of each remaining system without manual intervention. This feature improves the appending capability of the system when the user wishes to increase the capacity of the existing system with minimal cost. The reliability of overall system is greatly enhanced by paralleling system.
In an embodiment of the present invention, the display devices can be such as but not limited to LCD/TFT display, touch screen/smart panel, keyboard and other peripherals,

In an embodiment of the present invention, the present invention communicates with external computer/ peripheral devices with RS-232, RS-485, USB and other external interfaces (controllers/drivers implemented within FPGA).
In an embodiment of the present invention, the heavy-duty charger with any value of charging current is provided to charge the batteries
BRIEF DESCRIPTION OF THE FIGURES
Further objects and advantages of this invention will be more apparent from the ensuing description when read in conjunction with the accompanying drawings and wherein:
FIG. 1 shows a block diagram of inverter according to the present invention
FIG 2 shows the circuit diagram of FPGA architecture and implementation of 3-phase
high frequency inverter.
FIG 3 shows the circuit diagram of feedback sensing and PWM generating circuitry
logic.
DETAIL DESCRIPTION OF THE INVENTION WITH REFERENCE TO THE ACCOMPANYING DRAWINGS:
Reference may be made to FIG. 1 indicating the overall view of the functionality of the system i.e. high frequency inverter with grid charger 100. There is a DC-DC converterlOl feeds the voltage to the FPGA. The 3- phase H-bridge inverter 100 converts the DC bus voltage into 3-phase sine wave AC power through space vector modulation PWM generated by controller in the FPGA 102. The output of the 3-Phase H-bridge converter 103 after filtering through LC filter/isolations transformer 104 can be transferred to load 105 by transfer switch 106 in case of the failure or bad quality of grid power 107. The six pulse width modulated signals for the three phase operation with dead band control are generated using the FPGA based controller 102 for driving these IGBT/ MOSFETs. Output independent control of the each phase as per the feedback received at the input is handled by the 3 phase H-bridge controller 103.

The FPGA 102 also communicates with devices 108 such as the TFT display, touch screen/smart panel and other user interface with video/ photo/data display capability. Information is provided to the user in the form of audio messages/ buzzer beeps/ sounds etc 109. A keypad based user interface 110 is also present where controls for the inverter 100 like start/ stop, reset etc are provided by the user to control the inverter 100. The communication interface 111 is primarily based on RS-232 / USB other generic protocols.
The output side of the FPGA 102 comprising of IGBT/MOSFET drivers 112 arranged in H bridge configuration for a 3-Phase output. LC filter 104 is provided to remove the desired high frequency component from H-bridge output. The isolation transformer 104 may be used to provide galvanic isolation of the load and the 3-Phase H-bridge output. Output voltage sense section senses 113 the output AC voltage level in inverter mode and sends the relevant data to the corresponding controller 102 for processing. Similarly, output current sense senses 114 the corresponding current level.
The IGBT driver cards 112 receive input signals from inverter control circuit 102 which is implemented within FPGA 102 and provides output drive signals to 3-Phase H bridge controller 103. The two complementary PWM signals generated by the FPGA 102 will not be high simultaneously as this is controlled by the appropriate logic circuitry by providing a dead band. IGBT driver card 112 provides isolation between FPGA 102 side and IGBT 103 side with the help of isolated drivers 112. If there is any short circuit or voltage drop in the IGBT 103 side and VCE becomes greater than the specified value then the driver takes protection and FPGA 102 disables the PWM signals.
The input to the FPGA 102 comprises of sensing circuits such as input voltage sense 115 and zero cross/ phase sense 116. Charger ON/OFF 117A switch enables the charger 117 in case of a grid supply failure or if the grid supply is out of the specified region. The present invention comprises power supply section 118 connected to charger transfer switch 106, charging current sense circuit 119, load 105, circuit

breaker 120, surge protection 121 and heat sink temperature sensing 122. The paralleling block 123 enhances the capability of this inverter 100 to be combined with other inverters in parallel thus increasing the overall system capacity handling capability and reliability. This structure of the implementation requires a minimum inverter number (N) to handle the current load and maximum faulty inverter number (X) that a system can handle. The reliability of the system increases with greater 'N' value as the load handling capability of the parallel system still is intact in an eventuality of multiple inverter failure less than F value. The (N+X) combination is a highly reliable mode of operation.
The parallel interleaved DC-DC converters 124 shall operate in the interleaved mode controlled by the phase shifted PWM signals. The phase shift between the PWM signals will be determined by the number of converters in parallel. The reduced operational temperature and peak ripple current, increased switching efficiency, reduced energy storage requirement at the input capacitor and output capacitors.
Various voltage and current sensing circuits such as DC bus sense 125 to sense high DC bus 125A, battery current 126 and battery voltage sense 127 are also present to sense the battery 128 parameters. Selectable menu options such as but not limited to display time/date, back-up time remaining, settings for charging time, load setting, charging current setting, O/P voltage setting within range, KWH on mains and inverter are also provided in the inverter. An external memory 129 is connected to the memory interface to store/ retrieve the data from FPGA 102.
This is a talking inverter which gives audio cues to the end user. There is also a provision for inserting the rate of electricity so that consumer can see for the particular appliance bill on the mains line which is being calculated at the back. Particular load can be stored and memorized for wattage consumption for particular appliance. All the parameters such as but not limited to starting current are stored in the system so that appliances can be seen using wattage individually and collectively. The hourly as well KWh usage is recorded and stored in the memory. The system also checks correct identity of the systems through a unique identity tracking mechanism.

The present invention 100 also provides real time web based remote monitoring as well as multiple user local monitoring for inverter with the help of power management software using internet. In the present invention, the inverter 100 also has the connectivity through GSM device. It provides connectivity of the inverter to the internet without a computer. Using this, the user can monitor and control the product from a remote location using mobile phone. This feature is very useful at those remote locations where the user does not have a computer and desires to check the status of the inverter. It is also advantageous to monitor the inverter in households where computer is not available. Additional advantage of this facility is that, it reduces the cost of the inverter and does not require additional telephone lines. The data is recorded locally by the monitoring system and relayed to the server via the GSM network. Using the password, user can retrieve his unit's data at any time with the help of any internet access anywhere in the world. GSM device is connected to the inverter via FPGA 102 through the RS232/ RJ45/ USB cable and through GPRS connectivity, data is transmitted to the remote locations.
Reference may be made to fig. 2, 200. Separate hardware modules such as interleaved DC-DC controller 201, power supply controller 202, 3 Phase H-bridge controller 203, charger controller 204, display controller 205, keypad interface 206 and communication interface 207 controller are implemented inside the FPGA 102. The control of the output power is achieved by controlling the IGBTs 103 with the help of pulse width modulated (PWM) signals generated by the inverter FPGA controller 102, via the isolated gate driver circuits 112. The space vector PWM (SVM) of this 3-phase inverter provides additional advantage of superior harmonic quality and large under modulation range that extends the modulation factor. The implementation of SVM also takes care of neutral point voltage balancing. The control unit provides the necessary logic and control signals required to achieve the overall functionality of the high frequency inverter 100. A central processing unit (CPU) 208 is also used in conjunction with the control unit 209 which may have the internal flash memory 210. The data processing capability of the CPU 208 has the flexibility of programmable system architecture and control unit 209 allows the implementation of 16-bit or higher 32-bit CPU 208 as per the control application requirement and features provided with the system.

The ADC controller 211 is capable of handling multi channel ADC devices. It will scan each channel periodically. The period of the scan is determined by the speed of the clock at which the digital data is read out from the ADC 211. The data from each channel is automatically mirrored to their respective controllers in the FPGA 102. These controllers process the data as and when required by the system 100. This enables continuous, automated and accurate monitoring of the data without any intervention from CPU 208 or firmware.
The FPGA 102 comprises of logic circuitry to control the various hardware modules such as interleaved DC-DC controller 201, Power Supply controller 202, 3-phase bridge controller 203, Charger controller 204, Display controller 205, Keypad interface 206, communication interface 207 and paralleling controller 213. The heart of the FPGA 102 is the Central Processing Unit (CPU) 208. The CPU 208 is used in conjunction with the control unit 209 which has the access to the internal flash memory. The control unit 209 provides necessary logic and control signals required to achieve the overall functionality of the three phase high frequency inverter 100. The data processing capability of the CPU 208 can vary from 8,16 or 32-bit as per the control application requirement.
The FPGA 102 also communicates with devices 108 such as LCD/TFT display, touch screen/ smart panel and other user interface. Dedicated display controller 205 is implemented in hardware for controlling the operation of these display/smart panels 108. FPGA 102 monitors the parameters such as but not limited to battery voltage, charging current and temperature for controlling the operation of the charger by pulse modulated signal with automatic and manual temperature equalization.
If the battery 128 is completely charged, FPGA 102 switches the charger 117 from a boost cum absorption state to a float state. The charger 117 has a built-in over current and under/over input AC voltage protection. The system is cold start capable. There is a unique identifier for each of the inverter system through unique identification number provided within FPGA 102.

This architecture helps in achieving output rectification time of less than a couple of micro seconds. This fast rectification circumvents the need to wait till end of cycle for correction and thus aids in achieving a better THD factor and overall quality of power delivered to the load. The timing errors between the controller blocks in the FPGA 102 will drastically reduce. This increases the data transfer integrity between blocks in the FPGA 102 and eliminates the inter IC communication. This also reduces the data corruption in high noise environments.
The display controller 205 provides control for display devices 108 such as but not limited to LCD/TFT and touch screen/smart panel. Smart panels or touch screens provide bi-directional interface where information is processed and displayed on the basis of human feedback. Other display systems can be easily accommodated with modifications in the display controller. A keypad based user interface 110 is provided where controls for the inverter 100 like start/stop, reset etc are provided to the user. Alarms 109 relating to various parameters and conditions such as 'No Load', 'Emergency', 'Full Load', and 'Overload' are provided to the user in the form of audio messages/ buzzer beeps/ sound etc.
The communication interface 111 provided in the invention is primarily based on RS-232/ USB protocol which is commonly used in communication with the PC. This communication can be achieved at different baud rates/ speeds selected by the user. Other communication protocols such RS-422, RS-485 or 10/100 Ethernet access can also be used as per the application requirement.
A real time clock (RTC) 214 is used in the present invention. Continuous operation of this clock 214 is achieved by an alternate source of power even if the primary source is not available. The RTC 214 is driven by an external crystal oscillator of such as but not limited to the frequency 32Khz.
Reference may be made to FIG. 3 indicating the description of the system in view of the ADC voltage and current sensing and PWM generation 300. The invention comprises of ADC controller 211 which converts the ADC serial data to parallel data of all the channels sequentially without intervention of the CPU. The external ADC

converts the analog signals to digital format. Various voltage and current sensing circuits such as DC bus sense 125, battery current 126 and battery voltage sense 127 are also provided. The ADC controller 211 is a completely automated - multi channel scan capable - custom controller. This controller 211 scans and stores the current value of each channel sequentially at a periodicity determined by the read out serial clock to the external ADC. This is a continuous automated operation without the intervention of CPU 208 or the firmware. Data from each channel is updated constantly in the respective dedicated registers. The values from these registers are available to various controllers within the FPGA 102 for further processing.
Various voltage and current signals are sensed and fed to an analog to digital converter which converts these analog signals to the digital format required by the ADC 211 controller residing in the FPGA 102. On the basis of these feedback signals, control logic decisions are made inside the FPGA 102 in order to have the desired output.
The comparator block 301 receives and compares the real time instantaneous value from the dedicated registers and expected instantaneous ideal SINE value from the look up table. The difference between the two is calculated. This difference is sent to PWM generator block every time the difference is calculated. This process of calculating the difference and passing the output to the PWM generator block 302 is repeated for multiple times within a given full cycle period of the feedback sine wave. Since the error correction is carried out almost instantaneously and iterated multiple times within a given full cycle of the feedback sine wave, the THD factor is improved. Also, the correction response time to non linear load and the quality of the output power of the inverter is dramatically enhanced.
The PWM generator 302 multiplies the input from the comparator with modulation index factor and adjusts the "time-on" period of the PWM signals accordingly. The dead-band controller 303 induces the dead-band to prevent short circuiting in the

output of the complementary signals. The PWM signals, thus generated, drive the IGBT/MOSFET driver 112 to eventually generate the sine wave which passes through the LC filter/ isolation transformer 104 and eventually drive the load 105.
The above may be considered as exemplary embodiment.
It is to be understood that the above-described embodiments are illustrative of only a few of the many possible specific embodiments, which can represent applications of the principles of the invention. However, numerous and varied other arrangements can be readily devised in accordance with these principles by those skilled in the art without departing from the spirit and scope of the invention.

WE CLAIM:
1. A field programmable gate array based three phase high frequency inverter with grid charger comprises an interleaved DC-DC converter, three phase H bridge converter converts the DC bus voltage into 3-phase sine wave AC power through space vector modulation PWM generated by controller in the FPGA comprising of sensing circuits such as input voltage sense, zero cross/ phase sense, charger, charger ON/OFF switch, power supply section connected to charger transfer switch, charging current sense circuit, load, circuit breaker, output current sense, surge protection, heat sink temperature sensing, paralleling block, interleaved DC-DC converter, voltage and current sensing circuit such as DC bus sense, battery current and battery voltage sense, and external memory, the output of the FPGA comprising of PWM signals which drive the IGBT/MOSFET drivers, converts DC to AC, after filtering through any filtration means transferred to load by transfer switch in case of the failure or bad quality of grid power, communicates with display devices, alarms, keypad based user interface and communication interface
2. A three phase high frequency inverter with grid charger as claimed in claim 1, wherein any filtration means are such as EMI/ EMC filter, LC Filter or isolation transformer devices.
3. A field programmable gate array based three phase high frequency inverter with grid charger as claimed in any of the preceding claims, wherein the rates of electricity are inserted in the inverter and power consumption data is provided to the user.
4. A field programmable gate array based three phase high frequency inverter with grid charger as claimed in any of the preceding claims, wherein the load can be stored and memorized for wattage consumption for particular appliance in which all the parameters are stored in the system so that appliances is seen during using wattage.
5. A field programmable gate array based three phase high frequency inverter with grid charger as claimed in any of the preceding claims, wherein the field programmable gate array comprises of an interleaved DC-DC controller, power supply controller, 3-Phase H-bridge controller, charger controller, display controller, keypad interface, communication interface controller, paralleling controller, real time clock and central processing unit in conjunction with the control unit having memory.


6. A field programmable gate array based three phase high frequency inverter with grid charger as claimed in any of the preceding claims, wherein a unique identification code is provided within the FPGA which may be read with the help of the firmware and keeps track of each inverter.
7. A field programmable gate array based three phase high frequency inverter with grid charger as claimed in any of the preceding claims, wherein the ADC controller continuously scans, stores and processes the current value of every channel at a periodicity determined by the read out serial clock to the analog to digital converter..
8. A field programmable gate array based three phase high frequency inverter with grid charger as claimed in any of the preceding claims, wherein the comparator receives and compares the real time instantaneous value with the expected value from the look up table, calculates the difference, and sends the calculated difference to pulse width modulated generator in which the output correction calculation is repeated up to any number of times.
9. A field programmable gate array based three phase high frequency inverter with grid charger as claimed in any of the preceding claims, wherein the inverter reduces the timing errors between the controller, increases the data transfer integrity, reduces data corruption and eliminates the inter integrated circuit communication.
10. A field programmable gate array based three phase high frequency inverter with grid charger as claimed in any of the preceding claims, wherein the communication interface interacts and gives cues to the user.
11. A field programmable gate array based three phase high frequency inverter with grid charger substantially as herein described with reference to the accompanying drawings.