DESC:TECHNICAL FIELD
[001] The present disclosure relates generally to communication device, in particular it relates to a field-programmable gate array (FPGA) based configurable device front end for acoustic signal conditioning.

BACKGROUND
[002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[003] A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL). FPGAs include an array of programmable logic blocks, and a hierarchy of "reconfigurable interconnects" that allow the blocks to be "wired together", like many logic gates that can be inter-wired in different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. Many FPGAs can be reprogrammed to implement different logic functions, allowing flexible reconfigurable computing as performed in computer software.
[004] A transceiver is a device comprising both a transmitter and a receiver that are combined and share common circuitry or a single housing for transmitting and a receiving signals in communications devices such as cellular telephones, cordless telephone sets, handheld two-way radios, mobile two-way radios, etc. The transmitter and receiver are used in underwater acoustic communication devices as well as in the devices, which can measure depth in water. However, the conventional devices include separate transmitter hardware and receiver hardware for acoustic signal conditioning.
[005] Therefore, there is need in the art to provide a simple and efficient hardware device, which can obviate the above-mentioned problemand provide both the receiver and transmitter as a single configurable hardware module for acoustic signal conditioning.

OBJECTS OF THE PRESENT DISCLOSURE
[006] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are as listed herein below.
[007] It is an object of the present disclosure to provide field-programmable gate array (FPGA) based configurable device with motherboard and at least one first and second daughter boards to perform front end signal conditioning required for transmit chain and receive chain respectively.
[008] It is an object of the present disclosure to provide FPGA based motherboard configured to act as a transmit controller and receiver controller depending on the plug-in daughter boards residing on it
[009] It is an object of the present disclosure to provide each daughter board which process ‘N’ channels simultaneously based on requirement and operational frequency, presently configured for 8 channels simultaneously.
[0010] It is an object of the present disclosure to provide daughter boards designed which supports multiple frequencies depending on the application requirement.
[0011] It is an object of the present disclosure to provide field-programmable gate array (FPGA) based configurable device, where the number of channels in the daughter boards are ‘N’, depending on that ,the plug-in arrangements in the FPGA motherboard card is reconfigured to accommodate 1 to ‘M’ plug-in cards .
[0012] It is an object of the present disclosure to provide field-programmable gate array (FPGA) based configurable device demonstrated for acoustic frequency range and can be used to implement transceivers for predefined frequency range.
[0013] It is an object of the present disclosure to provide field-programmable gate array (FPGA) based motherboard realized as standard VME ( Versa Module Eurocard bus) form factor for ease of plugin and can also be configured for VPX (extension of VME (Versa Module Eurocard bus )) or other standard form factor for modularity
[0014] It is an object of the present disclosure to provide an efficient, multifunctional and innovative field-programmable gate array (FPGA) based device.

SUMMARY
[0015] The present disclosure relates generally to communication device, in particular it relates to a field-programmable gate array (FPGA) based configurable device front end for acoustic signal conditioning.
[0016] An aspect of the present disclosure pertains to a field-programmable gate array (FPGA) based configurable device, the device can include at least one first section, where each of the at least one first section can include an FPGA based motherboard, at least one first daughter board operatively coupled to the FPGA based motherboard; and at least one second daughter board operatively coupled to the FPGA based motherboard, where each of the least one first daughter board and the least one second daughter board can be configured to perform in a first mode and a second mode; where in the first mode each of the at least one first daughter board and the at least one second daughter operate as a transmitter link, and in the second mode each of the at least one first daughter board and the least one second daughter operate as receiver a link.
[0017] In an aspect, the FPGA based motherboard can be configured to operate as a transmit controller and a receiver controller at same time.
[0018] In an aspect, the at least one first daughter boards can be an analogue board with Digital to Analog Converter (DAC) and at least one second daughter board can be an analogue board with Analog to Digital Converter (ADC), and wherein each of the at least one first and the at least one second daughter boards facilitate to perform front end signal conditioning required for transmit chain and receive chain respectively.
[0019] In an aspect, the at least one first and the at least one second daughter boards can be configured to support predefined acoustic frequency range
[0020] In an aspect, the FPGA based motherboard can be configured to perform as a N channel transmitter cum receiver board, wherein the FPGA based motherboard associated with the at least one first daughter board with N channels is for transmission link, and at least one second daughter board with N channels is for reception link.
[0021] In an aspect, a count of a number of channels in the device can be increased by plugging in multiple sets of the FPGA based motherboard along with the at least one first daughter board and at least one second daughter board.
[0022] In an aspect, the FPGA based motherboard can be configured to perform as a RS422 communication card, which supports Ethernet to RS422 conversion and distribution up to 16 RS422 signal pairs.
[0023] In an aspect, the FPGA based motherboard can be used as a Nx2 channel transmitter board when associated with two transmission daughter boards.
[0024] In an aspect, the FPGA based motherboard is used as a Nx2 channel receiver board when associated with two receiver daughter boards.
[0025] Various objects, features, aspects and advantages of the inventive subject matter will become apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The diagrams are for illustration only, which thus is not a limitation of the present disclosure.
[0027] FIG. 1 shows a mechanical layout of motherboard and daughter boards configuration of the proposed device, in accordance with embodiments of the present disclosure.
[0028] FIG. 2 illustrates an exemplary block diagram of the FPGA mother board with plug-in boards, in accordance with embodiments of the present disclosure.
[0029] Persons skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and may have not been drawn to scale. For example, the dimensions of some of the elements in the figure may be exaggerated relative to other elements to help to improve understanding of various exemplary embodiments of the present disclosure. Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures.

DETAILED DESCRIPTION
[0030] In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without some of these specific details.
[0031] If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0032] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0033] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0034] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.
[0035] Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those of ordinary skill in the art. Moreover, all statements herein reciting embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future (i.e., any elements developed that perform the same function, regardless of structure).
[0036] The present disclosure relates generally to communication device, in particular it relates to a field-programmable gate array (FPGA) based configurable device front end for acoustic signal conditioning.
[0037] According to an aspect the present disclosure pertains to a field-programmable gate array (FPGA) based configurable device, the device can include at least one first section, where each of the at least one first section can include an FPGA based motherboard; at least one first daughter board operatively coupled to the FPGA based motherboard; and at least one second daughter board operatively coupled to the FPGA based motherboard, where each of the least one first daughter board and the least one second daughter board can be configured to perform in a first mode and a second mode; where in the first mode each of the at least one first daughter board and the at least one second daughter operate as a transmitter link, and in the second mode each of the at least one first daughter board and the least one second daughter operate as receiver a link.
[0038] In an embodiment, the FPGA based motherboard can be configured to operate as a transmit controller and a receiver controller at same time.
[0039] In an embodiment, the at least one first daughter boards can be an analogue board with Digital to Analog Converter (DAC) and at least one second daughter board can be an analogue board with Analog to Digital Converter (ADC), and wherein each of the at least one first and the at least one second daughter boards facilitate to perform front end signal conditioning required for transmit chain and receive chain respectively.
[0040] In an embodiment, the at least one first and the at least one second daughter boards can be configured to support predefined acoustic frequency range
[0041] In an embodiment, the FPGA based motherboard is configured to perform as a N channel transmitter cum receiver board, wherein the FPGA based motherboard associated with the at least one first daughter board with N channels is for transmission link, and at least one second daughter board with N channels is for reception link.
[0042] In an embodiment, a count of a number of channels in the device can be increased by plugging in multiple sets of the FPGA based motherboard along with the at least one first daughter board and at least one second daughter board.
[0043] In an embodiment, the FPGA based motherboard can be configured to perform as a RS422 communication card , which support Ethernet to RS422 conversion and distribution up to 16 RS422 signal pairs.
[0044] In an embodiment, the FPGA based motherboard can be used as a Nx2 channel transmitter board when associated with two transmission daughter boards.
[0045] In an embodiment, the FPGA based motherboard is used as a Nx2 channel receiver board when associated with two receiver daughter boards.
[0046] FIG. 1 shows a perspective view of motherboard and daughter boards configuration of the proposed device, in accordance with embodiments of the present disclosure.
[0047] As illustrated in an embodiment, the proposed field-programmable gate array (FPGA) based configurable device 100 (also referred to as device 100 hereinafter),the device 100 can include at least one first section, where each of the at least one first section can include an FPGA based motherboard 102 . The device 100 can include at least one first daughter board 104 and at least one second daughter board 106 (also referred to as plug-in cards 104 and 106 or daughter cards 104 and 106 or analogue cards 104 and 106 or analogue boards 104 and 106 hereinafter).The daughter cards 104 and 106 can be operatively coupled to the FPGA based motherboard 102 , The daughter cards 104 and 106 can be configured to perform in a first mode and a second mode; where in the first mode each of the at least one first daughter board 104 and the at least one second daughter board 106 can operate as a transmitter link, and in the second mode each of the at least one first daughter board 104 and the least one second daughter board 106 can operate as a receiver link.
[0048] In an embodiment, the FPGA based motherboard 102and the daughter cards 104 and 106 can be configured to operate for a predefined acoustic frequency range. The FPGA based motherboard 102 can be configured to perform as a N channel transmitter cum receiver board, where the FPGA based motherboard associated with the at least one first daughter board with N channels is for transmission link, and at least one second daughter board with N channels is for reception link.
[0049] The FPGA based motherboard 102 can be configured to operate as a transmit controller or as a receiver controller for 2N channels associated with the daughter boards 104 and 106 respectively. Also the FPGA based motherboard 102 can be configured to perform as N channel transmitter cum receiver board. When the FPGA based motherboard 102 can be associated with the first daughter board 104 with N channel for transmission link, the FPGA based motherboard can act as transmitter board and when the FPGA based motherboard 102 can be associated with the second daughter board 106 with N channel for reception link, the FPGA based motherboard can act as receiver board
[0050] In an embodiment, the FPGA based motherboard 102 can be configured to perform as a RS422 communication card , which support Ethernet to RS422 conversion and distribution up to 16 RS422 signal pairs. The FPGA based motherboard 102 can also be used as a Nx2 channel transmitter board when associated with two transmission daughter boards and as Nx2 channel receiver board when associated with two receiver daughter boards .The FPGA based motherboard can accommodate wide range of channel availability when used as a Nx2 channel transmitter and channel receiver.
[0051] In an embodiment, the FPGA based motherboard 102 can also be configured to perform as a communication card that can support Ethernet to RS422 conversion for distributing multiple signal pairs and can be used as a Nx2 channel transmitter board while using the transmission based daughter card. Further, the FPGA based motherboard 102 can be used as Nx2 channel receiver board while using the receiver based daughter card. In another embodiment, the same FPGA motherboard 102 without any plug-in daughter cards, can be used for RS422 serial communication, for distributing16 signal pairs.
[0052] In another aspect of the embodiment, the daughter boards 104 and 106 can include a first daughter board 104, which can be an analogue board with Digital Analog Converter (DAC), and a second daughter board 106, which can be an analogue board with Analog to Digital Converter (ADC).Both the boards 104,106 can be configured to perform as front end signal conditioning required for transmitting and receiving chain respectively. The daughter boards 104,106 can be configured to support predefined frequency. In an implementation, the count of a number of channels in the FPGA based configurable device 100 can be increased by plugging in multiple sets of the FPGA based motherboard 102 along with the at most two daughter boards. The plug-in card one 104can support transmission link in one card slot, and another plug-in card two 106 can support receiver link in another slot ,such that at a time, the FPGA based configurable device 100 can act as a transmitter card as well receiver card for an ‘N’ channel system.
[0053] FIG. 2 illustrates an exemplary block diagram of the FPGA mother board with plug-in boards/ daughter boards of the proposed device , in accordance with embodiments of the present disclosure.
[0054] As illustrated in FIG. 2, in an embodiment, the proposed field-programmable gate array (FPGA) based configurable device 100 can includes a FPGA based mother board 102 with a pair of plug-in or daughter boards 104 and 106.For example, the FPGA motherboard 102 can have a standard VME(Versa Module Eurocard bus) form Factor (233.35mm X 160mm).The FPGA motherboard 102 card can also have a System on chip (SOC) 202,as the main module, where the SOC can include the FPGA and a microprocessor. The FPGA motherboard 102 can include related peripheral, and interface devices such as double data rate ( DDR),where the DDR can be a SDRAM (synchronous dynamic random access memory and can have high transfer data rate)Flash memory, Ethernet Drivers, level translators and data buffers.
[0055] In an embodiment, a power circuit can be coupled with the connector P1 206 and can be configured to provide standard VME rail voltages for FPGA based configurable device 100 operation.
[0056] In another embodiment, the voltage compatibility of the FPGA motherboard 102 with daughter boards 104 an 106 can be achieved through level translators or level shifters, both for input and output signals of the FPGA..
[0057] In an embodiment, the VME P1 connector 206 in the board can be a power connector. The standard VME voltage can be obtained through P1connector 206.The P2 -208 and P0- 204 connectors can be used for signal routing to and from between external interfaces or other external boards and the FPGA based configurable device 100. The FPGA motherboard 102 card can be provided with 4 numbers of standard 20 pin connectors, 2 numbers for each pair of daughter boards 104 and 106.The FPGA motherboard card 102 can be realized as standard VME form factor for ease of plug- in and can also be configured for VPX (extension of VME( Versa Module Eurocard bus) ) or other standard form factor for modularity. Each daughter boards 104 and 106 can be of 100mmX100mm dimension to process ‘N’ channels simultaneously based on requirement and operational frequency .Each daughter boards 104,106 can be configured for 8 channels simultaneously. The daughter boards 104,106 can be designed for supporting multiple frequencies depending on the application requirement. The number of channels in the daughter boards can be ‘N’, and depending on the number of channels N, plug-in arrangements in the FPGA motherboard card 102 can be reconfigured to accommodate 1 to ‘M’ plug-in cards.
[0058] In an embodiment, the pair of daughter boards 104,106 or plug-in cards like plug-in card one 104 and plug-in card two 106 can be analogue cards to do signal conditioning of signals. Two types of plug-in card designs can be implemented to support receiver and transmit links separately. The plug-in card one 104 and plug-in card two 106 can be of same design. In an implementation, if two plug-in boards containing ‘N’ channel each and supporting transmission link are plugged together, then the entire FPGA motherboard 102 card along with the plug-in cards 104,106 can be used as a transmit board to process ‘2N’ channels at a time. In another implementation, if two plug-in boards 104 and 106 containing ‘N’ channel each and supporting receiver link are plugged together, then the entire FPGA motherboard card 102 along with the plug-in cards 104 and 106 can be used as a receive board to process ‘2N’ channels at a time. In an illustrative embodiment, the plug-in card one 104 and plug-in card two 106 can have eight channels each respectively. When the plug-in card one and plug-in card two supporting transmission link are plugged together , the FPGA based motherboard 102 can act as a transmit board and can process 16 channels at a time. When the plug-in card one and plug-in card two with eight channels each , supporting receiver link are plugged together , the FPGA based motherboard 102 can act as a receive board to process 16 channels at a time.
[0059] In another illustrative embodiment, by plugging in each type of the ‘N’ channel plug-in card in each slot, the single motherboard cum plug-in card combination can be used as a transmitter board as well as receiver board for an ‘N’ channel system. The FPGA motherboard 102 in transmission link can generate signals to be transmitted, and in receiver link, the same card can be used for capturing and processing the signals. In both cases the signals can be conditioned using analogue boards 104 and 106.
[0060] In an embodiment, each daughter cards 104 and 106 can be provided with two numbers of 20 pin standard connectors to aid plugging in with motherboard 102. One of the connectors can cater all the digital signals and another connectors can support analogue signals. The digital signals of both types of analogue boards are not in same voltage level. Hence the compatibility of the FPGA mother board 102 with daughter boards 104,106 can be achieved by using suitable level translators, both for input and output signals of FPGA. Also the hardware is presently tested and configured for acoustic signal conditioning; the same configuration can be taken over to realize front end transceiver for predefined frequency ranges.
[0061] In an embodiment, the FPGA based configurable device 100 can include multiple FPGA based motherboard 102 with at least one first and second daughter boards 104 and 106 associated with each of the FPGA based motherboard 102.
[0062] It is to be appreciated by a person skilled in the art that, though various embodiments of the FPGA based configurable device 100 are presently tested and configured for acoustic signal conditioning, however, the same configuration can be taken over to realize front end transceiver for predefined frequency ranges, and all such embodiments are within the scope of the present invention
[0063] Thus, it will be appreciated by those of ordinary skill in the art that the diagrams, schematics, illustrations, and the like represent conceptual views or processes illustrating systems and methods embodyingthis invention. The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing associated software. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the entity implementing this invention. Those of ordinary skill in the art further understand that the exemplary hardware, software, processes, methods, and/or operating systems described herein are for illustrative purposes and, thus, are not intended to be limited to any particular named.
[0064] While embodiments of the present invention have been illustrated and described, it will be clear that the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the invention, as described in the claim.
[0065] In the foregoing description, numerous details are set forth. It will be apparent, however, to one of ordinary skill in the art having the benefit of this disclosure, that the present invention may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention.
[0066] As used herein, and unless the context dictates otherwise, the term "coupled to" is intended to include both direct coupling (in which two elements that are coupled to each other contact each other)and indirect coupling (in which at least one additional element is located between the two elements). Therefore, the terms "coupled to" and "coupled with" are used synonymously. Within the context of this document terms "coupled to" and "coupled with" are also used euphemistically to mean “communicatively coupled with” over a network, where two or more devices are able to exchange data with each other over the network, possibly via one or more intermediary device.
[0067] It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refers to at least one of something selected from the group consisting of A, B, C …. N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc.
[0068] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE PRESENT DISCLOSURE
[0069] The present disclosure provides field-programmable gate array (FPGA) based configurable device with motherboard and at least one first and second daughter boards to perform front end signal conditioning required for transmits chain and receive chain respectively.
[0070] The present disclosure provides FPGA based motherboard configured to act as a transmit controller and receiver controller depending on the plug-in daughter boards residing on it.
[0071] The present disclosure provides each daughter board which process ‘N’ channels simultaneously based on requirement and operational frequency, presently configured for 8 channels simultaneously.
[0072] The present disclosure provides daughter boards designed which supports multiple frequencies depending on the application requirement.
[0073] The present disclosure provides field-programmable gate array (FPGA) based configurable device where the number of channels in the daughter boards are ‘N’, depending on that ,the plug-in arrangements in the FPGA motherboard card is reconfigured to accommodate 1 to ‘M’ plug-in cards .
[0074] The present disclosure provides field-programmable gate array (FPGA) based configurable device demonstrated for acoustic frequency range and can be used to implement transceivers in a predefined frequency range.
[0075] The present disclosure provides field-programmable gate array (FPGA) based motherboard realized as standard VME ( Versa Module Eurocard bus) form factor for ease of plug in and can also be configured for VPX (extension of VME (Versa Module Eurocard bus )) or other standard form factor for modularity
[0076] The present disclosure provides an efficient, cost effective and innovative field-programmable gate array (FPGA) based device.
,CLAIMS:1. A field-programmable gate array (FPGA) based configurable device, the device comprising:
at least one first section, wherein each of the at least one first section comprises:
an FPGA based motherboard;
at least one first daughter board operatively coupled to the FPGA based motherboard; and
at least one second daughter board operatively coupled to the FPGA based motherboard;
wherein each of the least one first daughter board and the least one second daughter board is configured to perform in a first mode and a second mode;
wherein in the first mode each of the at least one first daughter board and the at least one second daughter operate as a transmitter link, and in the second mode each of the at least one first daughter board and the least one second daughter operate as receiver a link.
2. The device as claimed in claim 1, wherein the FPGA based motherboard is configured to operate as a transmit controller and a receiver controller.
3. The device as claimed in claim 1, wherein at least one first daughter boards is an analogue board with Digital to Analog Converter (DAC) and at least one second daughter board is an analogue board with Analog to Digital Converter (ADC), and wherein each of the at least one first and the at least one second daughter boards facilitate to perform front end signal conditioning required for transmit chain and receive chain respectively.
4. The device as claimed in claim 3, wherein the at least one first and the at least one second daughter boards are configured to support predefined acoustic frequency range
5. The device as claimed in claim 1, wherein the FPGA based motherboard is configured to perform as a N channel transmitter cum receiver board, wherein the FPGA based motherboard associated with the at least one first daughter board with N channels is for transmission link, and at least one second daughter board with N channels is for reception link.
6. The device as claimed in claim 1, wherein a count of a number of channels in the device is increased by plugging in multiple sets of the FPGA based motherboard along with the at least one first daughter board and at least one second daughter board.
7. The device as claimed in claim 1, wherein the FPGA based motherboard is configured to perform as a RS422 communication card , which support Ethernet to RS422 conversion and distribution up to 16 RS422 signal pairs.
8. The device as claimed in claim 1, wherein the FPGA based motherboard is used as a Nx2 channel transmitter board when associated with two transmission daughter boards.
9. The device as claimed in claim 1, wherein the FPGA based motherboard is used as a Nx2 channel receiver board when associated with two receiver daughter boards.