FPGA PERIPHERAL ROUTING WITH SYMMETRIC EDGE TERMINATION AT FPGA BOUNDARIES
FIELD OF THE INVENTION
This invention relates to an FPGA incorporating peripheral routing with symmetrical edge termination at the boundaries. The invention also relates to a method for incorporating symmetrical edge termination at FPGA chip boundaries.
BACKGROUND OF THE INVENTION
FPGAs are programmable devices containing an array of programmable logic blocks connectable by programmable routing resources. IO pads at the chip periphery can interact with the core logic. The FPGA can be programmed to implement a wide range of circuits providing a large variety of designs. The efficiency of the implementation in terms of area and speed depends not only on the FPGA architecture, but also largely on effectiveness of the physical layout and interconnections. Automated software tools define the connectivity provided by programmable interconnections. The automated Place & Route is a complex activity. An FPGA architecture that facilitates this activity can have a very considerably influence the quality of the output produced. A good architecture exploitable by the software is ideal. Symmetric architectures aid in the development of efficient software algorithms.
The problem of maintaining of symmetry is acute in the regions neighboring the chip periphery. The worst affected is the routing architecture. The Xilinx Virtex device attempts to correct this problem by reflecting back the lines hitting the edge [12] as shown in figure 1. This approach successfully maintains constant channel width in the FPGA. But at the same time two other changes occur:
1. A new switching module [11] is required to be defined at the periphery.
2. The segments no longer adhere to the properties demonstrated in the core.
A peripheral routing channel [13] is also introduced that is different from the core channel. These changes present new architectural components to be modeled by the software. These requirements introduce considerable complexities in the software algorithm resulting in inefficiencies and delays.

The XC 4000 architecture is relatively simple with a connection box interfacing the terminating core routing channel to the peripheral segments. Moreover, the XC 4000 routing consists of single length line segments.
SUMMARY OF THE INVENTION
The object of this invention is to overcome these drawbacks and provide a FPGA device that maintains symmetry in the interconnection routing even at the periphery.
It is another object of the invention to establish predictable and uniform routing delays.
It is yet another object of the invention to reduce the schematic and layout design time of the FPGA owing to the virtue of a uniform tile.
To achieve these and other objects the invention provides a scheme for peripheral routing that provides symmetrical routing across its entire area including the periphery by incorporating peripheral routing lines of equal length that are symmetrically deflected orthogonally. The symmetrical peripheral routing lines are connected to switch boxes and connection boxer at the periphery for maintaining constant routing channel width.
BRIEF DESCRIPTION OF THE DRAWINGS
The objects and advantages of the invention will become more apparent in reference to the following description and the accompanying drawings, wherein:
FIG. 1 shows peripheral routing according to the prior art.
FIG. 2 shows vertical edge section of an FPGA according to the prior art
FIG. 3 shows an embodiment peripheral routing according to the present invention.
FIG. 4 shows a second embodiment of peripheral routing according to the present invention.
FIG. 5 shows a third embodiment of peripheral routing according to the present invention
DETAILED DESCRIPTION
A basic FPGA architecture comprising PLBs (Programmable Logic Blocks), switch boxes, and connection boxes has been described in the present embodiment. However it will be apparent to a person of ordinary skill in the art that the description is applicable to more complex architectures as well.
Figure 2 illustrates a vertical edge section of an FPGA. Segments [22] are staggered in the channel for increased routing flexibility. Segments start and finish at switch boxes [22a]. Line segments spanning more than one PLB tend to cause asymmetry in the channel close to the periphery. As it will become apparent, this asymmetry is directly proportional to the composition of the channel. The segment length of the tracks constituting the channel chiefly contributes to the irregularities seen at the edge. The segment length in the present embodiment is kept at four quad lines (segments spanning four PLB faces), which doesn't necessarily imply spanning of four PLBs. The PLB sides traversed may be of the same PLB. As the tracks approach the edge, they tend to extend beyond the last PLB. For instance, a quad line emerging from a switch box adjacent to the last PLB would tend to finish at a switch box 4 PLB sides away. Due to non-existence of such a PLB the line would end abruptly or would have to be done away with. This would lead to an unbalanced architecture.
The present invention maintains architectural symmetry by orthogonal deflection of such lines. The lines are symmetrically deflected in the two possible orthogonal directions. The line segments retain their property of spanning four PLBs. As shown in figure 3 and figure 4 in the preferred embodiment, one IO pad [24] is associated per PLB tile. The implementation exploits the concept of virtual depth by visualizing IO pad [24] and the PLBs along the edge as PLBs in a virtual array extending beyond the edge. For example, a track originating from a switch box adjoining the PLB on the west edge and turning northwards may be virtually reconstructed by unfolding the bent line westward. The lOs and the abutting PLBs facing the lOs are then visualized as logic blocks extending beyond the edge.
The switch box and connection box topologies can be retained from the core after inserting some lines in the channel induced at the periphery so as to maintain constant channel width. As shown in figure 4 side (23 aW) of a switch box at the periphery has its side facing the chip edge removed, but this does not have any adverse impact on its topology. A minor change in
the connection box topology of the IO pads interfacing with the so-formed peripheral routing might arise due to differences between the PLB & IO ports tapping the channel. However, the entire structure is a highly symmetrical, closed, well-knit peripheral routing framework.
A common requirement is to have a peripheral channel wider than the core routing channel. Figures 3 and 4 delineate two of the many possible schemes to widen the peripheral channel in accordance with the invention. In figure 3, the side of the switch box facing the edge is utilized to induce a supplementary channel [23b]. In figure 4, the bent segments are not terminated at a switch box. A 3-sided switch box [23a] accommodates the extra lines in two of its three sides. One of its sides [23aE] acts as a receptor of lines ending from the channel [22]. Connection boxes for IO pad and PLB interface are inserted between the peripheral switch boxes [23a].
Another embodiment illustrated in figure 5 accomplishes the object of the invention by merging lines deflected from adjacent channels. The lines are merged in accordance with their basic property. In fig. 5, a quad line is redefined as a segment spanning four PLBs, and not PLB sides as stated in earlier embodiments. An auxiliary channel is also introduced with properties similar to the one in fig. 4.
As will be appreciated by those skilled in the art, the proposed peripheral routing scheme results in a highly symmetric, easy to build architecture with low complexity in all domains. Many more embodiments are possible in the light and spirit of the present invention. For example, line segments of lengths other than four in a channel can be handled effectively in other possible embodiments. A line segment can be redefined to suit a particular architecture with the re-characterization altering the PLBs spanned by a segment at the periphery.

We claim:
1. A Field Programmable Gate Array (FPGA) providing symmetrical routing across its
entire area including the periphery, comprising:
peripheral routing lines of equal length that are symmetrically deflected orthogonally and are connected to,
switch boxes and connection boxes at the periphery, for maintaining constant routing channel width.
2. A Field Programmable Gate Array (FPGA) as claimed in claim 1 wherein the
peripheral routing lines are quad lines that span four PLB sides.
3. A Field Programmable Gate Array (FPGA) as claimed in claim 1 wherein the
deflected routing lines from adjacent channels are merged in accordance with their
basic property.
4. A Field Programmable Gate Array (FPGA) as claimed in claim 1 wherein the switch
boxes and the connection boxes are inserted between the peripheral switch boxes.
5. A method for providing symmetrical routing across its entire area including the
periphery, comprising the steps of:
symmetrically deflecting peripheral routing lines of equal length orthogonally,
and
connecting switch boxes and connection boxes at the periphery, for
maintaining constant routing channel width.
6. A method for providing symmetrical routing across its entire area including the
periphery, as claimed in claim 5 wherein the peripheral routing lines are quad lines
that span four PLB sides.
7. A method for providing symmetrical routing across its entire area including the
periphery, as claimed in claim 5 including the merging of the deflected routing lines
from adjacent channels in accordance with their basic property.

8. A method for providing symmetrical routing across its entire area including the
periphery, as claimed in claim 5 including inserting switch boxes and the connection
boxes between the peripheral switch boxes.
9. A Field Programmable Gate Array (FPGA) providing symmetrical routing across its
entire area including the periphery substantially as herein described with reference to
and as illustrated in figures 3 to 5 of the accompanying drawings.
10. A method for providing symmetrical routing across its entire area including the
periphery substantially as herein described with reference to and as illustrated in
figures 3 to 5 of the accompanying drawings.