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"Frame Sync Method Based On Discrete Logarithms"

Abstract: Method for transmitting data having a first format or format 1 in a data stream complying with a second format, the second format or format 2 consisting of a stream of data symbols incorporating, in a regular manner, a symbol dedicated to synchronization and placed every r data symbols, the symbol dedicated to synchronization being the current term of a series S(t) satisfying a linear recurrence, the data being split in format 1 into data blocks of fixed size that include kr symbols, the data symbols being considered as elements of a finite field GF(q) where q is the number of elements in the field, in which the series S(t) satisfies a linear recurrence over GF(q) and admits, as characteristic polynomial, a primitive polynomial P of degree n for GF(q), and is periodic with a period T=qn-1, α being a root of P in the field GF(qn). Figure to be published: Figure 2B.

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Patent Information

Application #
Filing Date
04 June 2010
Publication Number
09/2015
Publication Type
INA
Invention Field
COMPUTER SCIENCE
Status
Email
Parent Application
Patent Number
Legal Status
Grant Date
2020-11-03
Renewal Date

Applicants

THALES
45 RUE DE VILLIERS, 92200 NEUILLY-SUR-SEINE, FRANCE

Inventors

1. ERIC GARRIDO
13, AVENUE MADELEINE, 95230 SOISY/MONTMORENCY, FRANCE
2. GUILLAUME FUMAROLI
42, BOULEVARD LEFEBVRE, 75015 PARIS, FRANCE
3. XAVIER BERTINCHAMPS
12 BIS, RUE DES CHAMPIOUX, 95100 ARGENTEUIL, FRANCE

Specification

FRAME-SYNC METHOD BASED ON DISCRETE LOGARITHMS The invention relates to a method for transmitting data having a first format or format 1 in a data stream complying with a second format or format 2. The invention applies to data stream transmission systems, notably if these transmissions are simplex and synchronous. It is applicable for example in VLF (very low frequency) or LF (low frequency) radio communication systems in which the data is broadcast in the format defined by STANAG 5065 (LF MSK mode) or STANAG 5030. These systems are used for broadcasting messages to surface ships in the case of STANAG 5065 and to submarines in the case of STANAG 5030. The invention is applied for various waveforms, for example, MSK (minimum frequency-shift keying) and CPFSK (continuous-phase frequency-shift keying). Figure 1A shows an example of a VLF/LF broadcasting system split into three separate entities, the various functionalities of which have been shown in the figure. The system comprises a command center 1, a VLF/LF radio transmission station 2 and receiving platforms 3, such as surface ships or submarines, which receive the messages broadcast by the VLF/LF transmission station. The command center 1 may be positioned on a remote site connected to the VLF/LF transmission station via an inter-site link. The function of the control center is notably the generation 4 of messages to be transmitted and then their transfer 5 to the VLF/LF transmission station. The VLF/LF transmission station 2 receives the messages coming from the command center and broadcasts them on the VLF/LF (very low-frequency/low-frequency) channel 6. To fulfill these functions, the station contains a gateway 7 for interface with the network, one or more encryptors 8, a VLF/LF modulator 9 and a transmission system 10 or broadcasting equipment. Depending on the architecture adopted for implementing the method, the encryptors may be located in the command center or in the transmission station. To illustrate the subject of the present invention, the description addresses the second solution. The system for receiving the broadcast messages mainly comprises a receive antenna 11, a receiver 12, a VLF/LF demodulator 13, a message-receiving terminal 14 and one or more decryptors 15. The transmission stations transmit continuously. In the absence of messages to be transmitted, stuffing messages may be injected into the data stream. Among the receiving platforms, submarines are not continuously listening for transmitted messages. A mechanism is therefore required for synchronizing the receiving equipment with the data stream. For example, a data stream broadcast according to the STANAG 5030/5065 formats incorporates a synchronization sequence corresponding to a Fibonacci sequence transmitted continuously with the useful data. The Fibonacci sequence is recognized by the receiving equipment, namely a demodulator and a decryptor - and enables this equipment to by synchronized with the data stream. The principle is robust enough to tolerate the channel-induced transmission errors. In addition, by having quite precise clocks both in transmission and in reception, once synchronization has been established it may be maintained, even in the absence of receiving a signal since the data stream is synchronous. The encryptors placed in cut-off mode protect the confidentiality of the data stream. In this case, an encryptor (see figure 1B) ensures: • protection of the messages before their transmission, using the encryption function 20, • protocol adaptation 21, notably async-to-sync conversion, between the messages received from the inter-site network and the modulator, • generation of bit stuffing 22 in the absence of a message at its input. The decryptor on the platform receiving the messages ensures, in this case: • decryption 23 of the messages transmitted over the VLF/LF radio channel and demodulated by the demodulator, • protocol adaptation 24, notably sync-to-async conversion, between the demodulator and the data receive terminal, • received stuffing suppression 25. It should therefore be noted that the encryptors and decryptors integrate both an encryption function and other functions denoted generally in this document by "encoding" and "decoding" (see figure 1B). In the case of the aforementioned STANAG format, the data is transmitted in the form of a data stream of a telegraphy channel, according to figure 2A, the stream being organized as a 7-bit frame (Frame t), comprising 6 data bits and one current bit of the Fibonacci series, used for synchronization. At reception, the demodulator is responsible for the following processes: demodulation of the symbols and recognition of the Fibonacci series and synchronization. These various processing operations are known to those skilled in the art and will not be explained in detail in the present description. The Fibonacci series used is a non zero binary sequence that verifies a linear recurrence (in the two-element Galois field, GF(2)):S(t) = S(t-3)+S(t-31), in which "+" denotes addition modulo 2. It is generated for example by a linear feedback shift register (or LFSR) of characteristic polynomial P(X) = 1+X28+X31. Let E(t) = (S(t), S(t+1 ) S(t+30)), where t ≥ 0, be the current (31-bit vector) state of the LFSR register that delivers S(t). The period of the non zero series (S(t), t≥0) is also the period of the series of states of the register (E(t), t≥0) and is equal to T=231-1, since the polynomial P is a primitive polynomial. In transmission, this register is used in the encryptor and advances by one step at each frame. Each current 7-bit frame, noted Frame(t), includes the current bit S(t) of the Fibonacci series. The Fibonacci series thus incorporated ensures frame sync and code sync as will be described below. The current state E(t) of the LFSR shift register may be used as initialization vector for encrypting the data bits of the current frame. The 6 bits of useful data in the current frame are encrypted, for example by a bit-by-bit XOR logic with 6 bits of a pseudorandom number calculated with a cryptographic algorithm using a traffic key K and the current state E(t) of the LFSR. The Fibonacci series is transmitted in cleartext and for example according to the STANAG 5030/5065 format. At reception, a test of the three-term recurrence relation (S(t) = S(t-3) + S(t-31)) over a sufficiently wide window allows it to be detected in the received cryptostream and then fixes the splitting into a 7-bit word unambiguously, this process being known by the expression "frame sync". Each frame is then decrypted with the state of the register correctly found and maintained in the decryptor (a transition of the LFSR at each new frame). The existence of a continuously incorporated linear series in the transmission of a data stream which is both synchronous and simplex enables the demodulation and decryption equipment to be synchronized in a robust and reliable manner. However, this technique freezes the transmitted-data format and restricts this format to a few bits, typically one character. The invention makes it possible, while retaining this mechanism, its advantages and already existing infrastructures, to transmit other types of data effectively and therefore to broaden the field of applications. This processing is carried out in the encrypting equipment in transmission and in the encrypting equipment at reception. Although the above description mentions only the Fibonacci series S(t) = S(t-3) + S(t-31), the present invention applies to any equipment carrying out a continuous synchronization process based on a series verifying a linear recurrence. In the rest of the description, the useful data is encoded in format 1 or format 2. The encoding operation generates data comprising useful data and/or data associated with an error-correcting code and/or any other technical information conventionally used in coding/decoding processes (see figure 2B): a) in format 1, the data is grouped in blocks of a fixed size, including kr symbols; b) in format 2, the data is grouped in blocks of a fixed size, called superframes, which themselves consist of frames: - a frame is a window of the data stream including r data symbols and 1 symbol dedicated to synchronization, the symbol dedicated to synchronization being distributed every r data symbols. This dedicated symbol is a current term of a series S(t) verifying a linear recurrence; - a superframe is a window of the data stream consisting of k consecutive frames, therefore including kr data symbols and k synchronization symbols. The invention relates to a method for transmitting data having a first format or format 1 into a data stream complying with a second format, the second format or format 2 consisting of a stream of data symbols incorporating, in a regular manner, a symbol dedicated to synchronization and placed every r data symbols, the symbol dedicated to synchronization being the current term of a series S(t) satisfying a linear recurrence, the data being split in format 1 into data blocks of fixed size that include kr symbols, the data symbols being considered as elements of a finite field GF(q) where q is the number of elements in the field, in which the series S(t) satisfies a linear recurrence over GF(q) and admits, as characteristic polynomial, a primitive polynomial P of degree n for GF(q), and is periodic with a period T=qn-1, α being a root of P in the field GF(qn), characterized in that it comprises at least the following steps: - in transmission, the series S(t) is generated by a linear controller, the current state E(t) of which is αt written in a particular base of GF(qn), during the data stream transmission phase, - the input data is formatted in several data blocks according to format 1, - the kr data symbols constituting a block in format 1 are positioned in the data part consisting of k consecutive frames in format 2, thereby corresponding to a superframe, in which a frame corresponds to a window of the stream of format 2 including r data symbols and 1 symbol dedicated to synchronization, and a superframe corresponds to a window of the stream in format 2 consisting of k consecutive frames, thereby including kr data symbols and k synchronization symbols, - the various data blocks in format 1 are placed in succession in superframes, - the rank t of the first frame, frame(t), in a superframe including a block, is chosen so that the value modulo k of t is equal to a fixed value "a"; in the superframe reception phase: - the format 1 synchronization is determined in reception by completing the format 2 conventional frame-sync method for recognizing the synchronization series S(t) sent into the data stream, carrying out the following steps: - reconstructing E(t), the current state of the controller having generated the series on the basis of the symbols S(t), - letting E(to) be the recognized state associated with the first frame of the stream processed in reception, determination, from the value y = E(to), of the unique integer t lying within the [0, T-1] interval that satisfies the equation αt = y, using a discrete logarithm calculation over GF(qn), and - once the rank t0 is recognized, deduction of the rank of all the other frames that follow and the position of the superframes including the blocks in format 1, the first frame of a superframe including a data block having, as rank, an integer the remainder modulo k of which is equal to the arbitrary value "a" chosen. The method may comprise at least the following steps: for transmitting a stream of data blocks in format 1, at the initialization step, the elements of the counter CPT and the linear controller LFSR are set in the following manner: before transmission of the first frame, the current counter CPT is in any state X, that imposed after energizing the equipment or obtained after transmission of preceding traffic; the transmitter then calculates d = X modulo k and makes u elementary transitions of the components LFSR and CPT, where u is equal to: - 0 if d = a modulo k; - 1 if d = a+k-1 modulo k; - 2 if d = a+k-2 modulo k; - k-1 if d = a+1 modulo k. According to one embodiment, the residues are processed in the following manner: in the case in which the period T=(qn-1) is not a multiple of k and is of the form Qk+h, where 0 < h < k, a complete cycle of T powers of a absorbs Qk frames, and therefore Q superframes, and h frames remain at the end of this cycle, these being included in a special superframe called residue superframe, comprising only h frames instead of k frames associated with the h last powers of a in the cycle : αT-h, αT-(h-1),..., αT-1. The residue superframe incorporates, for example, stuffing and/or data according to a particular coding, in transmission and in reception and it is identified as the superframe positioned on the frame of rank (T-h). The method may integrate, in the superframe: - redundancy bits associated with an error-correcting code, - explicit stuffing information, such as flags, indicating whether the transported data in the superframe is useful data or whether it corresponds to stuffing. Other features and advantages of the present invention will become apparent on reading the following description of an exemplary embodiment given by way of illustration but implying no limitation, together with the figures that represent: • figure 1A, an example of the architecture of a VLF/LF broadcasting system; • figure 1B, the operation of an encryptor and a decryptor in the method; • figure 2A, the organization of a bit frame using a synchronization bit; • figure 2B, the splitting into frame, superframe and data block in format 1 and format 2; • figure 3, a representation of a linear feedback shift register; • figure 4, a control matrix for a linear code used in an example of the coding principle; and • figure 5, an example of the shift register when implementing the method of the invention. To make the method according to the invention easier to understand, the following example is given for a system in which the data format has to satisfy that defined in STANAG 5030/5065. The data terminal at the interface with the encryptor delivers a data stream in a format which is not necessarily directly adapted to the splitting into a frame of r = 6 bits of STANAG 5030/5065. The nonlimiting example of the method given here relates to transportation of an n-area data stream in the frames of STANAG 5030/5065 in an optimized manner in the following sense: - the bits transmitted in the data part of the frames of STANAG 5030/5065 are all used to encode the useful or stuffing symbols and optionally the redundancy bits associated with an error-correcting code; - no data bit in the frames is used explicitly for recognizing the splitting into n-area symbols or packets of n-area symbols at reception (symbol sync) in normal operation of the method according to the invention. To implement the method according to the invention, the transmitter of the system comprises for example an LFSR controller for generating the series S(t) verifying the linear occurrence, having a current state E(t) and a counter modulo T, CPT(t). The receiver is equipped in the same way with an LFSR controller and a counter CPT(t) modulo T. During transmission of the data stream, the input data is formatted into data blocks according to format 1. According to one example of implementing the method, the encoder of the system carries out a step of encoding the useful data in format 1. As shown in figure 2B, it is considered that the useful data consists of L packets of N bits. These L packets are positioned in the data part consisting of k consecutive frames in format 2, corresponding to a superframe. The frames in format 2 correspond for example to the STANAG 5030/5065 format. The rank t of the first frame, frame (t), in a superframe including a block in format 1 is chosen so that the value of t is equal to 0 modulo k and more generally equal to an arbitrary value modulo k. Apart from the L useful packets (LN bits), a superframe may include: - L bits for indicating for each packet whether it actually corresponds to useful data or whether it corresponds to stuffing; - optionally, redundancy bits in order to add an error-correction and/or -detection service called FEC (Forward Error Correction) that takes into account the BER (Bit Error Rate) constraints of the radio channel. As an example, the description provides two possible ways in which the useful data may be split: - a splitting privileging the data rate in which the superframe consists of K=3 frames transporting L=2 useful bytes (N=8) without any redundancy; - a splitting in which the superframe consists of k=4 frames transporting L=2 useful bytes (N=8) and incorporating an error-correcting code. The coding of the useful data in superframes is all the more effective when no additional bit is allocated for providing superframe sync (detection of the new superframe splitting). Like frame sync, superframe sync is deduced from the Fibonacci series imposed by STANAG 5030/5065 as explained above. Example 1: Embodiment without redundancy on a byte stream In this embodiment, the superframe consists of 3 frames. It serves to transmit a block of L = 2 useful bytes (N=8) (d, 02) in 3 elementary frames of the STANAG 5030/5065 format (k=3, r=6). This superframe therefore includes k * r = 3 * 6 = 18 useful data bits and k=3 bits for the sync (Fibonacci sequence). The 18 data bits are specifically: -8 bits (a0,a1,a2,a3,a4,a5,a6,a7) of the useful byte Oi1 -8 bits (b0,b1,b2,b3,b4,b5,b6,b7) of the useful byte O2, -f1: 1 bit indicating if O1 is a useful byte or stuffing; -f2: 1 bit indicating if O2 is a useful byte or stuffing. Example 2: Embodiment with redundancy on a byte stream In this embodiment, the superframe consists of 4 frames. This superframe serves to transmit a block of L=2 useful bytes (N=8) (O1, 02) in k=4 elementary frames of the STANAG 5030/5065 format (k=4, r=6). This superframe therefore includes k *r = 4 * 6 = 24 useful data bits and k=4 bits for the sync (Fibonacci sequence). The 24 data bits are specifically: -8 bits (a0,a1,a2,a3,a4,a5,a6,a7) of the useful byte O1; -8 bits (b0,b1,b2,b3,b4,b5,b6,b7) of the useful byte O2; -f1: 1 bit indicating whether d is a useful byte or stuffing; -f2: 1 bit indicating whether 02 is a useful byte or stuffing; -6 redundancy bits (r0,r1,r2,r3,r4,r5) coming from a Hamming code with a parity bit. The control matrix defining the code is given in figure 5. This Hamming code with parity used for coding the 24-bit word systematically corrects one error and detects two of them. For example: (Formula Removed) the + sign corresponding to the binary XOR operation. Superframe sync In the previous splittings, no bit is allocated for ensuring the sync in a superframe, i.e. one for determining unambiguously the split into a superframe on the data stream processed at reception. The superframe sync is determined using the synchronization sequence already used for the elementary frames, for example the Fibonacci series in the case of STANAG 5030/5065. The Fibonacci series is generated by a linear controller of characteristic polynomial P = 1 + X28 + X31. Let a be a route of P in the finite field GF(231). We consider an equivalent implementation of the LFSR that generates the series S(t) in the form of a divider register that explicitly carries out the multiplication by a in the polynomial base (1,α,α2,..,α30). This equivalent implementation of the LFSR shows that the current state E(t) = (s(t), s(t+1) s(t+30)) is a 31-bit vector which, with close permutation of the components, may be interpreted as the element αt of the finite field GF(231) decomposed in the polynomial base (1,α,α2,...,α30). More precisely the current state of the register E(t) = (s(t),...,s(t+31)) of the LFSR is associated with the element: αt = s(t+27) α0 + s(t+26)α1 + s(t+25) α2 + ... + s(t) α27 + s(t+30) α28 + s(t+29) α29 + s(t+28) α30. (Equation 1). This example is shown in figure 6. The starting point a0 = 1 is associated with the state of the LFSR E(to) = (s(t0),s(t0+1) s(to+30)) in which the 31 components s(to + i) are zero except for s(to + 27), which is equal to 1. A superframe comprises k frames (in the examples, k = 4 in the embodiment with redundancy and k = 3 in the embodiment without redundancy). At transmission, the encoder makes the first frame in a superframe be associated with a state E(t) of the register in correspondence with an element αt for which the value of t is equal to a fixed value "a"-modulo k. For the rest of the explanation, the arbitrary assumption chosen is a = 0, which amounts to taking t as a multiple of k (t = ku). For this example (a=0), the k states of the register that are associated with the k frames of a superframe will therefore be of the form: E(t) = αku , E(t+1) = αku+1, E(t+2) = αku+2, ... , E(t+k-1) = αku+k-1. At any start of the data stream processing, the encoder chooses an initial current state E(t*) in order to generate the Fibonacci series associated with the element a'* with t* being a multiple of k. At transmission this may for example be carried out by explicitly controlling, in addition to the LFSR register that generates the Fibonacci series S(t), the current state of which is E(t), a 31-bit counter that encodes t such that E(t) is associated with αt. Upon the key change, the LFSR register controlled by the encryptor is set to its initial value E(t0) explained above (Equation 1) and the counter t is set to its value to=0. Next, at each new frame processed, the current LFSR register advances by one step and the counter t is incremented by 1 modulo T in order at any instant to maintain knowledge of the 2 data items: - the current state E(t) of the LFSR register associated with αt; and - its logarithm t in [0, T-1]. At reception, once the frame sync has been recovered, the current state of the LFSR register Y = (s(t),...,s(t+31)) associated with the first processed frame, i.e. frame(t), is available. The method then considers the element of the finite field GF(231): y = s(t+27) α0 + s(t+26)α1 + s(t+25) α2 + ... + s(t) α27 + s(t+30) α28 + s(t+29) α29 +s(t+28)α30. A discrete logarithm calculation on the finite field F(231) then makes it possible to find the unique value of t in [0,231-2] such that αt = y. More generally, the calculation can be carried out in a finite field GF(qn) having qAn elements: by observing the remainder modulo k of t, the receiver then deduces therefrom the position of the first superframe that it can process: for any v, with 0 < v < k, if t is of the form ku-v, the first superframe is [frame(t+v), frame(t+v+1),..., frame(t+v+k-1)]. Once it has recognized the rank to, the decoder forming part of the decryptor can deduce therefrom the rank of all the other frames that follow and therefore the position of the superframes including the blocks in format 1. The first frame of a superframe including a data block has as rank a multiple of k. Of course, once the superframe sync has been determined initially, it is easily maintained in the current regime by processing the stream of frames per packet of k consecutive frames. To adjust the positioning of the blocks of format 1 in the frames of format 2, or the place in which a block of format 1 has to be, the transmitter and the receiver of the system according to the invention control two controllers: - a controller of the LFSR type, which generates the synchronization sequence or series S(t) and the current state E(t) of which is in correspondence with the element αt of GF(qn); and - a counter modulo t, the current state CPT(t) of which is the value of the rank t. At each new frame received (in format 2) or transmitted, the LFSR undergoes a transition, this transition calculating the new state E(t+1) from its previous volume E(t). Likewise, the counter CPT is incremented by 1 at each new frame: CPT(t+1)=CPT(t)+1 modulo T. To transmit a stream of data blocks in format 1 into frames of format 2, the transmitter presets the controllers LFSR and CPT, for example in the following manner: before the first frame in format 2 is transmitted, the current counter CPT is in general in any state X, that which is imposed by turning the equipment on or obtained after transmission of previous traffic. The transmitter then calculates d=X modulo k and carries out a number u of elementary transitions of the LFSR and CPT elements, in which u is equal to: 0, if d = 0 modulo k; 1, if d = k-1 modulo k; 2, if d = k-2 modulo k; k-1, if d = 1 modulo k. Processing of the residues The period T=(231-1) is not divisible by k and is of the form kQ+r, where 0

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1 4006-DELNP-2010-RELEVANT DOCUMENTS [30-09-2023(online)].pdf 2023-09-30
1 abstract.jpg 2011-08-21
2 4006-delnp-2010-form-5.pdf 2011-08-21
2 4006-DELNP-2010-RELEVANT DOCUMENTS [30-09-2022(online)].pdf 2022-09-30
3 4006-delnp-2010-form-3.pdf 2011-08-21
3 4006-DELNP-2010-FORM 4 [05-02-2021(online)].pdf 2021-02-05
4 4006-DELNP-2010-IntimationOfGrant03-11-2020.pdf 2020-11-03
4 4006-delnp-2010-form-2.pdf 2011-08-21
5 4006-DELNP-2010-PatentCertificate03-11-2020.pdf 2020-11-03
5 4006-delnp-2010-form-1.pdf 2011-08-21
6 4006-DELNP-2010-PETITION UNDER RULE 137 [01-10-2020(online)].pdf 2020-10-01
6 4006-delnp-2010-drawings.pdf 2011-08-21
7 4006-DELNP-2010-Proof of Right [01-10-2020(online)].pdf 2020-10-01
7 4006-delnp-2010-description (complete).pdf 2011-08-21
8 4006-DELNP-2010-Written submissions and relevant documents [01-10-2020(online)].pdf 2020-10-01
8 4006-delnp-2010-correspondence-others.pdf 2011-08-21
9 4006-delnp-2010-claims.pdf 2011-08-21
9 4006-DELNP-2010-Correspondence to notify the Controller [15-09-2020(online)].pdf 2020-09-15
10 4006-delnp-2010-abstract.pdf 2011-08-21
10 4006-DELNP-2010-US(14)-HearingNotice-(HearingDate-17-09-2020).pdf 2020-08-17
11 4006-delnp-2010-Form-18-(24-11-2011).pdf 2011-11-24
11 4006-DELNP-2010-REQUEST FOR ADJOURNMENT OF HEARING UNDER RULE 129A [13-08-2020(online)].pdf 2020-08-13
12 4006-delnp-2010-Correspondence-Others-(24-11-2011).pdf 2011-11-24
12 4006-DELNP-2010-US(14)-ExtendedHearingNotice-(HearingDate-17-08-2020).pdf 2020-07-15
13 4006-DELNP-2010-FORM 3 [12-08-2017(online)].pdf 2017-08-12
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14 4006-DELNP-2010-FER.pdf 2018-02-14
14 4006-DELNP-2010-US(14)-ExtendedHearingNotice-(HearingDate-16-07-2020).pdf 2020-06-30
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16 4006-DELNP-2010-FORM 4(ii) [08-08-2018(online)].pdf 2018-08-08
17 4006-DELNP-2010-Verified English translation (MANDATORY) [29-08-2018(online)].pdf 2018-08-29
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18 4006-DELNP-2010-Retyped Pages under Rule 14(1) (MANDATORY) [29-08-2018(online)].pdf 2018-08-29
19 4006-DELNP-2010-ABSTRACT [29-08-2018(online)].pdf 2018-08-29
19 4006-DELNP-2010-OTHERS [29-08-2018(online)].pdf 2018-08-29
20 4006-DELNP-2010-COMPLETE SPECIFICATION [29-08-2018(online)].pdf 2018-08-29
20 4006-DELNP-2010-FORM-26 [29-08-2018(online)].pdf 2018-08-29
21 4006-DELNP-2010-DRAWING [29-08-2018(online)].pdf 2018-08-29
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22 4006-DELNP-2010-DRAWING [29-08-2018(online)].pdf 2018-08-29
22 4006-DELNP-2010-FER_SER_REPLY [29-08-2018(online)].pdf 2018-08-29
23 4006-DELNP-2010-COMPLETE SPECIFICATION [29-08-2018(online)].pdf 2018-08-29
23 4006-DELNP-2010-FORM-26 [29-08-2018(online)].pdf 2018-08-29
24 4006-DELNP-2010-OTHERS [29-08-2018(online)].pdf 2018-08-29
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25 4006-DELNP-2010-2. Marked Copy under Rule 14(2) (MANDATORY) [29-08-2018(online)].pdf 2018-08-29
25 4006-DELNP-2010-Retyped Pages under Rule 14(1) (MANDATORY) [29-08-2018(online)].pdf 2018-08-29
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28 4006-DELNP-2010-US(14)-HearingNotice-(HearingDate-16-04-2020).pdf 2020-03-18
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31 4006-delnp-2010-Correspondence-Others-(24-11-2011).pdf 2011-11-24
31 4006-DELNP-2010-US(14)-ExtendedHearingNotice-(HearingDate-17-08-2020).pdf 2020-07-15
32 4006-delnp-2010-Form-18-(24-11-2011).pdf 2011-11-24
32 4006-DELNP-2010-REQUEST FOR ADJOURNMENT OF HEARING UNDER RULE 129A [13-08-2020(online)].pdf 2020-08-13
33 4006-delnp-2010-abstract.pdf 2011-08-21
33 4006-DELNP-2010-US(14)-HearingNotice-(HearingDate-17-09-2020).pdf 2020-08-17
34 4006-delnp-2010-claims.pdf 2011-08-21
34 4006-DELNP-2010-Correspondence to notify the Controller [15-09-2020(online)].pdf 2020-09-15
35 4006-delnp-2010-correspondence-others.pdf 2011-08-21
35 4006-DELNP-2010-Written submissions and relevant documents [01-10-2020(online)].pdf 2020-10-01
36 4006-DELNP-2010-Proof of Right [01-10-2020(online)].pdf 2020-10-01
36 4006-delnp-2010-description (complete).pdf 2011-08-21
37 4006-DELNP-2010-PETITION UNDER RULE 137 [01-10-2020(online)].pdf 2020-10-01
37 4006-delnp-2010-drawings.pdf 2011-08-21
38 4006-DELNP-2010-PatentCertificate03-11-2020.pdf 2020-11-03
38 4006-delnp-2010-form-1.pdf 2011-08-21
39 4006-DELNP-2010-IntimationOfGrant03-11-2020.pdf 2020-11-03
39 4006-delnp-2010-form-2.pdf 2011-08-21
40 4006-delnp-2010-form-3.pdf 2011-08-21
40 4006-DELNP-2010-FORM 4 [05-02-2021(online)].pdf 2021-02-05
41 4006-DELNP-2010-RELEVANT DOCUMENTS [30-09-2022(online)].pdf 2022-09-30
41 4006-delnp-2010-form-5.pdf 2011-08-21
42 4006-DELNP-2010-RELEVANT DOCUMENTS [30-09-2023(online)].pdf 2023-09-30
42 abstract.jpg 2011-08-21

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