A) TECHNICAL FIELD

[0001] The present invention generally relates to power supply systems and particularly to voltage regulators such as linear regulators for supplying stable power to microprocessors in electronic devices over a wide range of load currents. The present invention more particularly relates to ultra low drop out regulators for supplying stable power to automotive, portable instruments, cellular phones, pagers, desk top computers, laptop computers, camcorders, medical devices where the load current varies over wide ranges.

B) BACKGROUND OF THE INVENTION

[0002] Power management is a very important issue in portable electronic applications. The need for multiple on chip voltage levels makes voltage regulators a critical part in any electrical system design. The microprocessor driven applications in portable electronic devices need large current in the order of few amperes.

[0003] Linear regulators have been used for a long time as the standard power systems with regulated voltage spanning from 3V to 24V and output currents ranging from 100mA to 5A. Their use is mainly due to a better load transient response, less noise, more simple design and cheaper than the equivalent switching regulators. But these linear regulators are relatively inefficient due to the high power losses.

[0004] More recently the linear regulators have been developed for automotive, portable instruments, cellular phones, pagers, desktops and laptops, camera recorders and medical applications, where the load current can vary over a wide range of values. But the linear regulators could not supply a stable voltage across all loading conditions.

[0005] Ultra Low Dropout Regulators (ULDO) achieve high efficiency at the cost of a compromise with the stability of the regulator. The Low Drop Out (LDO) regulator supplying large current in the order of few amperes to microprocessors needs to be stable over a wide range of output capacitors, its range of Equivalent Series Resistance (ESR) values and power supply variations. While maintaining the stability over such a wide range of varying parameters, the quiescent current may increase significantly or the system could typically have poor transient response. The constraints could also be undesirable in terms of board size and cost in order to achieve stability.

[0006] LDO Regulators using NMOS transistor as a pass element are stable over wide range of loading conditions and do not require any capacitor at the output for stability purposes. This is due to the fact that NMOS transistor is in a source follower configuration thereby offering low output impedance across wide range of load currents. However better transients demand a larger output capacitor. Hence NMOS regulators must be designed to incorporate wide range of output capacitor values and should exhibit stability over wide range of ESR values for a wide current band.

[0007] The frequency compensation techniques of such a regulator becomes complicated in a way that the regulator has to be stable over a wide range of output capacitor and its ESR values along with widely varying current loading conditions. High load current regulators (in the range of 5A to 7A) require a very large power FET as a pass element and hence the pole due to its parasitic capacitance can not be ignored. Also, as the capacitance value of the output capacitor tends to increase in the order of 100 ^F to 200pF, the pole due to such a large capacitor, even in the presence of low output impedance exhibited by the NMOS power PET in source follower configuration, is often well within the loop bandwidth for low load currents. This leads to a two pole LDO system loop thereby creating problems in providing stable outputs. Sometimes the loop bandwidth may be reduced rarely to improve the stability. Moreover the addition of a fixed frequency zero to the LDO loop may not improve the phase margin. This is due to the fact that the output pole Poui which directly depends on the load current and output capacitor can swing several decades in the frequency domain depending on the load current swing and the output capacitor value thereby making the placement of fixed frequency zero very much uncertain. The output pole Pout is given by 1/ (2*n*Rioad*Cour) where Rioad is the output load resistance and Cgut is the output capacitance. In spite of the placement of fixed frequency zero, it could happen that the frequencies of the output pole Pout and the pole due to error amplifier PEA could lie too close together below the cross over frequency thereby leading to instability under some loading conditions.

[0008] Another compensation strategy is to make Pout as the dominant pole. The non dominant pole PKA must therefore lie beyond the bandwidth. This can lead to high operating currents and often very low loop gain to ensure that PEA is positioned beyond the loop bandwidth. Also the increase of the output capacitor value to guarantee that Pout is at low frequencies for all loading conditions, can lead to high cost and large solution size. Hence there is a strange constraint on the maximum output capacitor value and the minimum load current. These constraints are unrealistic when the linear regulators are used in cellular phones and in medical applications where flexibility in cost and solution size is limited and stability over wide range of loading conditions is required.

[0009] Hence a pole tracking zero is required to track the output pole Pout depending on the loading conditions to cancel the pole. This essentially provides the LDO loop with a single pole system so that the error amplifier pole PEA can be made dominant with a simple Miller compensation technique. Also there is a stability concern due to the ESR zero. If the ESR of the output capacitor is low, the zero which is equal to 1/ (2*II*RISR*COIJT) is well beyond the bandwidth. This still creates a single pole system thereby ensuring the stability of the system. However if the ESR is high and is in the order of 1 to 10 ohms, it creates an additional zero well within the bandwidth. This could essentially lie too close to the error amplifier pole thereby rendering a large bandwidth for the LDO loop. In such cases the stability is very much uncertain and could be implemented in specific applications only.

[0010] FlG.l shows the basic structure of an LDO using NMOS as the pass element. The regulator consists of a charge pump to overdrive the NMOS transistor above power supply, a voltage reference, an error amplifier which includes the gate driver and a feedback resistors divider.

[0011] The choice of the pass element is very important to realize the EDO's when a high efficiency along with a low drop-out voltage is required for the LDOs. Bipolar NPN and PNP transistors can be used as pass elements. However, they do not satisfy the requirements of low drop-out or low quiescent bias conditions.

[0012] P-MOS devices having a low drop-out voltage for current up to 500mA have been developed with performance levels exceeding most bipolar devices. The N-MOS pass element is more advantageous due to its lower on chip resistance values. However they need a gate voltage which is higher than the power supply itself and which can be achieved only with a charge pump that drives the gate of pass element.

[0013] Several other embodiments of this core architecture are developed in BCD process technologies which use N-channel lateral DMOS transistors as pass elements. This architecture can deliver an output current up to 5A with an unregulated supply voltage down to 2V with only 150 mV of drop-out voltage.

[0014] However, there are certain constraints attached to the embodiments of such architecture. The frequency compensation of such a regulator becomes complicated in a way that the regulator has to be stable over a wide range of output capacitor values and its ESR values along with widely varying current loading conditions.

[0015] The stability issue in such architecture is very difficult to achieve without any constraints on the variations in load current. There is an acute constraint on the maximum output capacitor value as well as the stable minimum load current supported. These constraints are unrealistic when linear regulators are used in most applications where flexibility in cost and solution size is limited and stability over a wide range of loading conditions is required.

[0016] The currently available LDO regulators are provided with an architecture having minimum constraint on the load current and maximum constraint on the output capacitor to achieve stability across a wide range of load conditions.

[0017] Hence a novel frequency compensation technique is needed for low loading conditions to counter all these stability issues. In the realm of growing market, there is a strong need to achieve the stability without constraining any parameter in the design. Thus there is a need to develop frequency compensation system for ultra low dropout regulators across a wide range of load current conditions.

C) OBJECTS OF THE INVENTION

[0018] The primary object of the present invention is to provide a frequency compensation system for ULDO linear regulators to supply stable output across wide range of load currents ranging from micro ampere level to ampere level.

[0019] Another object of the present invention is to provide a frequency compensation system including a Gm -enhancement block to improve the stability of the ULDO regulators over a wide range of loading conditions, output capacitor values and its Equivalent Series Resistance (ESR) values.

[0020] Yet another object of the present invention is to provide a frequency compensation system for ULDO regulators to provide a single dominant error amplifier pole to provide a stable output.

[0021] Yet another object of the present invention is to provide a frequency compensation system for ULDO regulators with a circuit to split the output pole and the error amplifier pole without using any miller compensating capacitor.

[0022] Yet another object of the present invention is to provide a frequency compensation system for ULDO regulators with a pole tracking zero to provide a single dominant error amplifier pole to provide a stable output.

[0023] These and other objects and advantages of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings.

D) SUMMARY OF THE INVENTION

[0024] The abovementioned shortcomings, disadvantages and problems are addressed herein and which will be understood by reading and studying the following specification.

[0025] The various embodiments of the present invention provide a frequency compensation system and a method for ultra drop out regulator to provide a stable power output over a wide range of loading conditions, output capacitor values and its ESR values.
The present invention provides a Gm enhancement block to improve the stability of the ULDO regulators over a wide range of load current ranging from microamperes to few amperes. A pole tracking zero is added to stabilize the system with a single dominant error amplifier pole.

[0026] According to one embodiment of the present invention, a Gm enhancement block is added between the error amplifier and the output load circuit. The system has an error amplifier with the inputs connected to a reference voltage and to a feedback circuit. The output of the error amplifier is connected to the Gm enhancement block comprising three MOSFETS and two current sinks. The output of the Gm enhancement block is fed to a level shifter provided in the form of a PMOS buffer connected to the gate of an NMOSFET. The PMOS buffer drives the gate of the NMOSFET at a level higher than the power supply voltage VDD. The PMOS buffer is driven by the charge pump which is a boosted voltage regulator. The drain of the NMOSFET is connected to a voltage source VDD- The source of the NMOSFET is connected to a feedback circuit in which the feedback resistors R1 and R2 connected in series. The output of the NMOSFET is connected to an end load device. An output capacitor is connected in parallel to the feedback resistors circuit. A load resistance is connected to the output of the NMOSFET in parallel to the feedback resistor circuit and the output capacitor. The resistances R1 and R2 form the feedback circuit to generate a feedback voltage Vn,. The Gm enhancement block also drives a differential small signal current into the feedback resistors which create a pole tracking zero Zik.

[0027] The error amplifier generates a small signal VEA The Gm enhancement block produces a small signal gate voltage VgppEi at the gate of the Power-FET (NMOSFET) based on the generated error amplifier signal VEA. The gate voltage VgpiHTis proportional to the generated error amplifier signal VEA and is a level shifted version of error amplifier output voltage VEA- The Gm enhancement block also generates a differential current im based on the error amplifier output voltage VEA- The generated differential current signal in which modifies ESR zero in the loop transfer function to generate a pole tracking zero Ztk.. Thus the Gm enhancement block along with level shifted version of error amplifier output voltage VEA provides a differential small signal current in which modifies the zero Zik due to ESR of the output capacitor in a way that, the modified zero Z,k tracks the pole Pout and nullifies it.

[0028] Thus the various embodiments of the present invention provide a Gm enhancement block to improve the stability of the ULDO regulators over a wide range of load current ranging from microamperes to few amperes. A pole tracking zero is added to stabilize the system with a single dominant error amplifier pole.

[0029] These and other objects and advantages of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings.

E) BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The other objects, features and advantages will occur to those skilled in the art from the following description of the preferred embodiment and the accompanying drawings in which:

[0031] FIG. 1 is a block circuit diagram of LDO system according to a prior art.

[0032] FIG. 2 is a block circuit diagram of ULDO system according to one embodiment of the present invention.

[0033] FIG. 3 is a block circuit diagram of ULDO system provided with frequency compensation system according to one embodiment of the present invention.

[0034] FIG. 4 is an equivalent circuit diagram of the ULDO system provided with frequency compensation system according to one embodiment of the present invention.

[0035] FIG. 5 shows the stability curve for a given loading condition in ULDO system provided with frequency compensation system according to one embodiment of the present invention, when the zero has tracked the output pole.

[0036] FIG. 6 shows the shows the stability curve before and after the introduction of Gm enhancement block, for a given loading condition in ULDO system provided with frequency compensation system according to one embodiment of the present invention, in which the output pole is pushed to higher frequencies.

[0037] Although specific features of the present invention are shown in some drawings and not in others, this is done for convenience only as each feature may be combined with any or all of the other features in accordance with the present invention.

F) DETAILED DESCRIPTION OF THE INVENTION

[0038] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which the specific embodiments that may be practiced is shown by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to pracfice the embodiments and it is to be understood that the logical, mechanical and other changes may be made without departing from the scope of the embodiments. The following detailed description is therefore not to be taken in a limiting sense.

[0039] The various embodiments of the present invention provide a frequency compensation system for ultra drop out regulator to provide a stable power output over a wide range of loading conditions, output capacitor values and its ESR values. The present invention provides a Gm enhancement block to improve the stability of the ULDO regulators over a wide range of load current ranging from microamperes to few amperes. A pole tracking zero is added to stabilize the system with a single dominant error amplifier pole.

[0040] According to one embodiment of the present invention, a Gm enhancement block is added between the error amplifier and the output load circuit. The system has an error amplifier with the inputs connected to a reference voltage and to a potential divider circuit respectively. The output of the error amplifier is connected to the Gm enhancement block comprising three MOSFETS and two current sinks. The output of the Gm enhancement block is fed to a level shifter provided in the form of a PMOS buffer connected to the gate of an NMOSFET. The PMOS buffer is driven by the charge pump which is a boosted voltage regulator. For example the PMOS buffer is a PMOSFET device. A current source is connected to the PMOSFET device to bias the PMOSFET device. The drain of the NMOSFET is connected to a voltage source VDD-The PMOS buffer drives the gate of the NMOSFET at a level higher than the power supply voltage Vnp. The source of the NMOSFET is connected to a potential divider circuit including the resistors Ri and R2 connected in series. The output of the NMOSFET is connected to an end load device. An output capacitor is connected in parallel to the potential divider circuit. A resistance load is connected to the output of the NMOSFET in parallel to the potential divider circuit and the output capacitor. The resistances R| and R2 form a feedback circuit to generate a feedback voltage Vn,. The Gm enhancement block also drives a differential small signal current into the feedback resistors which create a pole tracking zero Ztk-

[0041] The error amplifier generates a small signal VEA The Gm enhancement block produces a small signal gate voltage VgPKHi at the gate of the Power-FET CNMOSFET) based on the generated error amplifier signal VHA. The gate voltage VgPFET is proportional to the generated error amplifier signal VKA and is a level shifted version of error amplifier output voltage VEA- The Gm enhancement block also generates a differential current im based on the error amplifier output voltage VEA. The generated differential current signal i^ which modifies the ESR zero in the loop transfer function to generate a pole tracking zero Z|k.. Thus the Gm enhancement block along with level shifted version of the error amplifier output voltage VHA provides a differential small signal current i,,, which modifies the zero Z,k due to ESR of the output capacitor in a way that the modified zero Ztk tracks the pole Pout and nullifies it.

[0042] Thus the various embodiments of the present invention provide a Gm enhancement block to improve the stability of the ULDO regulators over a wide range of load currents ranging from microamperes to few amperes. A pole tracking zero is added to stabilize the system with a single dominant error amplifier pole.

[0043] For the purpose of analysis, the feedback loop can be broken at SW as shown in FIG. 3. It is readily apparent that the system must have unity gain stable considering Vret and Vn, to be the input and output voltage respectively. However it is clear from the diagram that VgPFEi and im are responsive to small signal changes in feedback voltage Vfb. Vef controls the load and line regulation to the LDO system by influencing upon appropriate values to VgPFEi and im. The error amplifier generates a small signal VEA- The Gm Enhancement block generates a proportional voltage VgppET at the gate of the NMOS pass element based on the output error amplifier signal VEA.

It also generates a differential current ^ in response to VEA to modify the ESR zero in the loop transfer function to generate a pole tracking zero Zik. Hence the open loop gain at SW can be described as

where |Av| is the open loop gain under the given conditions.

[0044] When im (small signal differential current) is zero, the open loop gain be expressed as

Where gma and gmPKET refer to the transconductance of the amplifier and the pass element respectively, Roa is the output resistance of the amplifier, Coa refers to the parasitic capacitor introduced by the pass element, Road is the load, RSR is the ESR resistance of output capacitor Cout and R1 and R2 are the feedback resistors.

[0045] When PFET is dc biased, vgPFET=0, the circuit in the FIG.3 can be modeled as shown in the fig.4

From FIG.3, we can express im as im=m.i1.

Where m is the mirror ratio in the Gm enhancement block.

[0046] The Gm-Enhancement block acts as a small signal buffer and hence,

Where rjs is a small signal MOSFET resistance in the Gm enhancement block and Gm is the transconductance of the Gm-Enhancement block. It generates a small signal current in response to error amplifier signal VHA,

[0047]

Therefore,

case (2): At low current loads, Rioad » RhR2

It is clear that |Av| (VgPFEi = 0 ) is given by

Using equations A and equation-set B, equation I can be simplified into two sub bands of load circuit conditions.

Case (1) At low load current, when Road R1, R2

[0048] It can be seen that at high load currents, the pole Pout is at most loading conditions beyond the crossover frequency. In such a case the pole tracking zero is not necessary and accordingly equation D suggests the zero due to ESR is unmodified.

[0049] Fig. 5 shows the stability curves for a particular loading condition when the zero has tracked the output pole thus rendering the loop a single pole system. 90 degree phase margin is ensured under such a condition.

[0050] Referring back to figure 3, the pole due to output Pout swings several decades depending on the load current. At very low load current (luA), the output pole position could easily be less than l00Hz and hence could lie too close to error amplifier pole.

[0051] The gm enhancement block provides a multiplying factor M to gmPPET thus pushing Pout away from error amplifier pole. The shifted pole frequency is given by

Where G mpi-iii = g mprei M From FIG. 3, it can be seen that:

[0052] This multiplying factor M pushes the output pole away from the error amplifier pole. This pole is eventually cancelled by the pole tracking zero Z,k, thereby restoring the single pole system to the LDO loop regulation. The effect of M can be seen in FIG. 6. The output pole is shifted to a higher frequency determined by M.

[0053] Thus the Gm enhancement block along with level shifted version of error amplifier output voltage VEA provides a differential small signal current im which modifies the zero Zik due to ESR of the output capacitor in a way that, the modified zero Zik tracks the pole Pout and nulHfies it.

[0054] FIG. 2 is a block circuit diagram of ULDO system according to one embodiment of the present invention. With respect to FIG.2, Gm enhancement block 2 is added between error amplifier 1 and output load circuit. The system has error amplifier 1 with the inputs connected to a reference voltage and to a potential divider circuit respectively. The output of error amplifier 1 is connected to Gm enhancement block 2 comprising three MOSFETS 9, 10, 11 and two current sinks. The output of Gm enhancement block 2 is fed to a level shifter provided in the form of PMOS buffer 3 connected to the gate of NMOSFET 4. PMOS buffer 3 is driven by charge pump 12 which is a boosted voltage regulator. The drain of NMOSFET 4 is connected to a voltage source VDD- PMOS buffer 3 drives the gate of NMOSFET 4 at a level higher than the power supply voltage VDD- The source of NMOSFET 4 is connected to a potential divider circuit including resistors R] 5 and R2 6 connected in series. The output of NMOSFET 4 is connected to end load device 8. Output capacitor 7 is connected in parallel to the potential divider circuit. Resistance load 8 is connected to the output of NMOSFET 4 in parallel to the potential divider circuit and output capacitor 7. Resistances R| 4 and R2 5 form a feedback circuit to generate a feedback voltage Vji,. Gm enhancement block 2 also drives a differential small signal current into the feedback resistors 5, 6 which create a pole tracking zero Z ik.

[0055] Error amplifier 1 generates a small signal VEA. Gm enhancement block 2 produces a small signal gate voltage VgppET at the gate of Power-FET (NMOSFET) 4 based on the generated error amplifier signal VEA The gate voltage VgppET is proportional to the generated error amplifier signal VEA and is a level shifted version of error amplifier output voltage VEA- Gm enhancement block 2 also generates a differential current !„, based on the error amplifier output voltage VHA- The generated differential current signal im which modifies ESR zero in the loop transfer function to generate a pole tracking zero Z,k.. Thus Gm enhancement block 2 along with level shifted version of error amplifier output voltage VEA provides a differential small signal current !„, which modifies the zero Ztk due to the ESR of output capacitor 7 in a way that, the modified zero Z,k tracks the pole Pout and nullifies it.

[0056] FIG. 3 is a block circuit diagram of ULDO system provided with frequency compensation system according to one embodiment of the present invention, while FIG. 4 is an equivalent circuit diagram of the ULDO system provided with frequency compensation system according to one embodiment of the present invention. With respect to FIG.3 and F1G.4, Gm enhancement block 2 is added between error amplifier 1 and the output load circuit. The system has error amplifier 1 with the inputs connected to a reference voltage and to a feedback circuit. The output of the error amplifier 1 is connected to the Gm enhancement block 2 comprising three MOSFETS 9, 10, II and two current sinks. The output of Gm enhancement block 2 is fed to a level shifter provided in the form of PMOS buffer 3 connected to the gate of NMOSFE'f 4. PMOS buffer 3 drives the gate of NMOSFET 4 at a level higher than the power supply voltage VDD. PMOS buffer 3 is driven by charge pump 12 which is a boosted voltage regulator. The drain of NMOSFET 4 is connected to a voltage source Ypp. The source of NMOSFET 4 is connected to a feedback circuit in which feedback resistors R] 5 and R2 6 are connected in series. The output of NMOSFET 4 is connected to end load device 8. Output capacitor 7 is connected in parallel to the feedback resistors circuit. Load resistance 8 is connected to the output of NMOSFET 4 in parallel to the feedback resistor circuit and output capacitor 7. Resistances R| 5 and R2 6 form a feedback circuit to generate a feedback voltage Vn,. Gm enhancement block 2 also drives a differential small signal current into feedback resistors 5, 6 which create a pole tracking zero Z ,k.

[0057] Error amplifier 1 generates a small signal VEA. Gm enhancement block 2 produces a small signal gate voltage VgPFEi at the gate of Power-FET (NMOSFET) 4 based on the generated error amplifier signal VEA The gate voltage VgppET is proportional to the generated error amplifier signal V^A and is a level shifted version of error amplifier output voltage VIA- Gm enhancement block 2 also generates a differential current i^ based on the error amplifier output voltage VEA- The generated differential current signal im which modifies ESR zero in the loop transfer function to generate a pole tracking zero Z,k. Thus Gm enhancement block 2 along with level shifted version of error amplifier output voltage VKA provides a differential small signal current im which modifies the zero Z||< due to ESR of output capacitor 7 in a way that, the modified zero Z,|4 tracks the pole Pout and nullifies it.

[0058] FIG. 5 shows the stability curves for a particular loading condition when the zero has tracked the output pole thus rendering the loop a single pole system. 90 degree phase margin is ensured under such a condition.

[0059] FIG. 6 shows the shows the stability curves before and the after the introduction of Gm enhancement block for a given loading condition in ULDO system provided with frequency compensation system according to one embodiment of the present invention, in which the output pole is pushed to higher frequencies. The gm enhancement block provides a multiplying factor M to gmpFET thereby pushing Pout away from error amplitler pole. The multiplying factor pushes the output pole away from error amplifier pole. This pole is eventually cancelled by pole tracking zero Z,k, thereby restoring the single pole system to the LDO loop regulation. The effect of M can be seen in FIG.6. The output pole is shifted to a higher frequency determined by M.

G) ADVANTAGES OF THE INVENTION
[0060] Thus the various embodiments of the present invention provide a Gm enhancement block to improve the stability of the ULDO regulators over a wide range of load current ranging from microamperes to few amperes. The Gm enhancement block improves the stability of LDO regulators over a wide range of loading conditions, output capacitor values and its ESR values. A pole tracking zero is added to stabilize the system with a single dominant error amplifier pole. The two dominant poles such as the error amplifier pole and the output pole are split apart without using any miller compensating capacitor.

[0061] Although the invention is described with various specific embodiments, it will be obvious for a person skilled in the art to practice the invention with modifications. However, all such modifications are deemed to be within the scope of the claims.

[0062] It is also to be understood that the following claims are intended to cover all of the generic and specific features of the present invention described herein and all the statements of the scope of the invention which as a matter of language might be said to fall there between.

What is claimed is:

1. A frequency compensated device for ultra low drop out regulator comprising:

a reference voltage source;

an error amplifier connected to the reference voltage source;

a Gm enhancement block connected to the error amplifier;

a PMOS buffer connected to the Gm enhancement block;

a NMOSFET connected to the PMOS buffer;

a feedback resistor circuit connected to the NMOSFET;

an output capacitor connected in parallel to the feedback resistor circuit;

a differential small signal current path circuit connected to the Gm enhancement block and to the feedback resistor circuit; and

an end load device connected to the NMOSFET.

2. The device according to claim 1, wherein the Gm enhancement block comprises three MOSFETS and two current sinks.

3. The device according to claim 1, wherein the Gm enhancement block drives the differential small signal current into the feedback resistors circuit to create a pole tracking zero.

4. The device according to claim 1, wherein the Gm enhancement block level shifts the output voltage of the error amplifier and generates a differential current signal in proportion to the output voltage of the error amplifier to modify the zero due to ESR of the output capacitor to obtain a pole tracking zero so that the pole tracking zero tracks the output pole due to the output capacitor and nullifies the output pole.

5. The device according to claim 1, wherein the Gm enhancement block increases the output pole frequency by a multiplication factor so that the output pole is pushed away from the system bandwidth.

6. The device according to claim 1, wherein the PMOS buffer is a PMOSFET device.

7. The device according to claim 1, further comprises a current source connected to the PMOSFET device to bias the PMOSFET device.

8. The device according to claim 1, wherein the PMOSFET is connected to the gate of the NMOSFET to drive the gate of the NMOSFET at a voltage level which is higher than the power supply voltage level.

9. The device according to claim 1, wherein the drain of the NMOSFET is connected to the power supply voltage.

10. The device according to claim 1, wherein feedback resistors are connected to the source of the NMOSFET.

11. The device according to claim 1, wherein the feedback resistors includes two resistors that are connected in series.

12. The device according to claim 1, wherein the feedback circuit generates a feedback voltage which is fed to the error amplifier.

13. The device according to claim 1, wherein the error amplifier is an operational amplifier.

14. The device according to claim 1, wherein the end load device is connected to the source of the NMOSFET.

15. The device according to claim 1, further comprises a charge pump connected to the Gm enhancement block to drive the PMOS buffer.

16. The device according to claim 13, wherein the charge pump is a boosted voltage regulator.

17. The device according to claim 2, wherein the Gm enhancement block includes the first MOSFET connected to the output of the error amplifier.

18. The device according to claim 2, wherein the Gm enhancement block includes the second MOSFET connected to drain of the first MOSFET.

19. The device according to claim 2, wherein the Gm enhancement block includes the third MOSFET connected to the second MOSFET in a current mirror configuration and to the PMOS buffer.

20. The device according to claim 2, wherein the Gm enhancement block includes a first current sink connected to the first MOSFET.

21. The device according to claim 2, wherein the Gm enhancement block includes a second current sink connected to the third MOSFET.

22. The device according to claim 13, wherein the charge pump is connected to the second and the third MOSFETs in the Gm enhancement block.