Description:Field of Invention
The present invention relates to the design of full adder for low power consuming, energy efficient arithmetic and logical unit (ALU) applications. The full adder circuit require exclusive OR gate and carry circuits to produce Sum and carry outputs. In multi-bit adder applications, full adder circuit’s delay mainly depends on the delay of exclusive OR gate and carry circuit. Moreover, the exclusive OR gate consume more amount of power and delay than the other circuits in the full adder design. Hence, improving the delay performance of the exclusive OR gate and carry circuit will improve the overall performance of the full adder.
The objectives of this invention
The objective of this invention is designing of an low power consuming energy efficient full adder for ALU applications.
Background of the invention
The continuous growth in signal processing, mobile communications, microprocessors, and computing devices required portable electronic devices with low power consuming integrated circuits and systems. Many applications in portable electronic devices require longer battery life, high speed and small silicon area. The power available for these portable devices or wearable electronic devices is very limited, and the microelectronics technology has grown faster than the advanced battery technologies. The designers are restricted to design circuits with small silicon area, low-power consumption and high-speed (M. Hasan et al. [2002], IEEE Trans. Circuits Syst. II, 49, pp. 25-30). Due to the rapid growth in today’s VLSI technology, the IC designers are busy in making high performance systems with low power dissipation. 1-bit full adder circuits are mainly used in fundamental arithmetic operations like address calculation, subtraction, multiplication, division, etc. exclusive OR gate place a key role in producing Sum output and Carry output of full adder (H. T. Bui et al. [2002], IEEE Trans. Circuits Syst. II, 49, pp. 25-30).
These operations extensively used in various digital applications such as microprocessors and Digital Signal Processing (DSP) architecture. 1-bit full adder is the important building block of many other useful operations of the systems. In multi-bit adder applications, the overall performance depends on the performance of 1-bit carry cell (S. Goel et al. [2006], IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 14, pp. 1309-1321). The hybrid full adder is designed using exclusive OR gate, exclusive NOR gate along with the carry circuit. Therefore, improving the delay performance of the exclusive OR gate is a main objective in multi-bit adder applications (H. Naseri et al. [2006], IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 26, pp. 1481–1493).In chain structured adder applications such as arithmetic and logical unit, carry cells generate carry-out, which acts as carry-in to the next stage. It is important to generate the signal with the least amount of delay. The delayed signal not only affects the overall propagation delay, but also creates glitches and dissipates more power in multi bit adders. The exclusive OR gate also place an important role in producing the sum and carry outputs in full adder. There are multiple ways to design the exclusive OR gate and exclusive NOR gate. One way is design an exclusive OR gate and add inverter to the exclusive OR gate for exclusive NOR gate output. Another way is to design simultaneous exclusive OR-NOR gate which is capable for both exclusive OR gate and exclusive NOR gate outputs (Jyoti Kandpal et al. [2020], IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 28, pp. 1413 – 1422).
Description of Prior Art
Hybrid full adders are designed by including two input exclusive OR gate, exclusive NOR gate and carry circuit (EP0122946A1, US6700405B1, US7185042B1). The exclusive OR gate and exclusive NOR gates are the major circuits in hybrid full adder, which consume high amount of power and also produce high amount of delay (US4592007A, US 2004/0153490 A1). Hence, the total power consumption and overall delay of full adder cell can be decreased by improving the delay and power consuming performance of the exclusive OR gate, exclusive NOR gate and carry circuit. The exclusive OR/NOR gate circuits has been designed in the literature using eleven transistors (US8653857B2), complementary field effect transistor(US4575648), CMOS logic gate (US7285986B2, US5576637, US5523707) Transmission Gate (TG) logic (US6356112B1), Cross Coupled Transistor (US4713790), Complementary Pass Transistor Logic (CPL). The main problem of DPL logic is NOT gate in the critical path of the circuit. Due to the presence of not gate in critical path, the delay is more in DPL based exclusive OR gate. In TG logic also, the short circuit power will increase the total power consumption of the circuit. In full adder designs, the exclusive OR gate along and inverter are used to create the exclusive NOR gate function which is used to produce the sum output. Hybrid logic full adder (US4559609A, US4592007A, EP0187698A2, US5905667 and US6700405B1) uses different logic design styles for designing exclusive OR gate, exclusive NOR gate and carry circuits.

Summary of the invention
In the present innovative invention, is addressed the high amount of delay and power consumption in full adder circuits applications. The delay and power consumption problem is eliminated by designing an energy efficient exclusive OR gate, exclusive OR gate and carry generator circuit. Only three transistors are used in the design of exclusive OR gate. Moreover, there is no direct path between the ground and power supply, short-circuit current has been reduced. Based on the above stated advantages, the exclusive OR gate can able to reduce the delay and total power consumption of full adder circuit. The exclusive NOR gate is also required to generate sum output of the full adder. The exclusive NOR gate is designed by placing the inverter at the output of exclusive OR gate, which is used to produce the sum output. The carry output is separately produced by using carry generator circuit. The carry generator circuit significantly reduces the overall delay of the full adder in multi-bit adder applications. The carry generator circuit uses only three transistors to generate the output. Low amount of delay is achieved in carry generator circuit with less number of interconnect and only three transistors in the critical path. The full adder circuit constructed with five PMOS and six NMOS transistors.
Detailed description of the invention
The full adder circuit is divided into three sub-modules Module-1 is a exclusive OR gate/ exclusive NOR gate circuit, which produces outputs Y and Y’. These outputs act as inputs to module-2 and module-3. The sum circuit and carry circuit are placed in module-2 and module-3 respectively. The module-2 and module-3 produce sum and carry outputs. Full adder circuit is one of the essential circuits in computing systems with three 1-bit inputs and two 1-bit outputs. The terminal relationship between the inputs and the outputs is expressed as
(1)
(2)
(3)

In hybrid logic, the exclusive OR gate output signal available as the input signal for module-2 and module-3. These exclusive OR gate circuit output signal along with carry input are available for the input of modules-2 and module-3. The equation in (2), can also write as
(4)
Form eq. (4), the sum circuit output is similar to exclusive OR gate logic output. Therefore the sum circuit in module-2 can also act as an exclusive OR gate circuit in module-1.
The full adder circuit is shown in Fig. 1. In Fig.1, when A is at logic ‘1’ transistor N2 is ON and pass the signal B’ to the Sum output. When A is at logic ‘0’, the transistors (P1 & N1) are ON and output terminal is connected to input B. When B is at logic ‘1’, the output signal also ‘1’ and when B is at logic ‘0’ output is also at logic ‘0’. The transistors P1 & N1 are in OFF state when A is at logic ‘1’. Thus, there will be no voltage drop problem in P1 & N1 transmission gate, whether logic ‘1’ or logic ‘0’ is passed through it. The transmission gate provides a full voltage swing. When we consider A is at logic ‘0’ the output is same as the input B and when A is ‘1’ then the output is same as inverted B. Hence, the circuit with transistors P1, N1 and N2 act as an exclusive OR gate. Similarly, transistors P2, N3 and N4 are also act as an exclusive OR gate to produce Sum output of full adder circuit. Transistors P3, P4 and N5 are used for generating the carry output of full adder circuit. The carry circuit shown in Fig. 1 uses the output of exclusive OR gate, exclusive NOR gate, and the input signal Cin of full adder circuit to produce the carry output.
The proposed circuit is designed and simulated using Cadence tools with 45 nm complementary metal oxide semiconductor transistor technology. The proposed circuit supplied with 1 V supply voltage during the simulation and the maximum frequency of inputs was 1 GHz. A practical simulation test bench is used to explore the advantages of the proposed circuits. To enable a real environment, inverters are added to the terminals of the test bench. A minimum of 1 fF capacitance output load is added at the output of each inverter.
The output load of four inverters is used, which results in 4 fF output load for the delay and power measurements. The transistor sizes of inverters are selected to produce a sufficient distraction as in practical circuit. The proposed circuit’s performance is examined in terms of worst-case delay, total power consumption and power delay product for the supply voltages range from 0.4V-1.8V. The load of the test circuit is also varied from 1 fF to 10 fF to evaluate the performance. In rise transition and fall transition of the output, the delay is measured from 50% of the input to 50% of the output signal voltage level. The power delay product is calculated by choosing a worst case delay among the two outputs and it is multiplied with the test circuit’s average power consumption.
The overall delay of the proposed carry generator circuits and full adders can be reduced by optimizing the transistor sizes without a significant increase in power consumption. In all the proposed circuits, transistor sizes are selected to achieve the minimum power delay product. Initially, all the proposed circuits designed with minimum transistor sizes, and an iterative process of re-designing is carried out to achieve minimum power delay product. As mentioned in the above Eqs. 1-4, the full adder circuit is designed and it is shown in the Fig.1. The designed full adder circuit can be used all the arithmetic and logical operations.
3 Claims & 1 Figure
Brief description of Drawing
In the figures which are illustrated exemplary embodiments of the invention.
Figure 1 Full Adder Circuit
Detailed description of the drawing
As described above the present invention relates to copyright fetching.
Figure 1 gives the view about the design of an full adder circuit. The full adder circuit shown in Fig. 1 is used for the multi-bit arithmetic and logical operations. The exclusive OR gate in Figure 1 will produce less amount of delay and also consume low amount of power. Similarly, the carry circuit with only three transistors also consume low amount of power and dely. Hence, the proposed full adder circuit consume low amount of power and delay in multi-bit adder applications. , Claims:The scope of the invention is defined by the following claims:

Claims:
1. The full adder circuit comprises:
a) A simulation test bench with 0.8V supply voltage it achieved 278.5 ns amount of delay.
b) A set of three transistors including one TG gate and one pass transistor is used to achieve 278.5 ns delay.
c) The designed full adder circuit can be used for all the arithmetic and logical operations.
2. As mentioned in claim 1, the total power consumption achieved 2.32 nW by removing the direct path between the supply and ground.

3. As mentioned in claim 1, the exclusive OR gate will produce less amount of delay and also consume low amount of power.