1. A data transmission circuit comprising:
a driver having a positive terminal, a negative terminal, an output terminal, one or more pull-up transistors coupled to the positive terminal and the output terminal, and one or more pull-down transistors coupled to the output terminal and the negative terminal;
a reference voltage generation circuit for selecting, based at least upon activation of a first supply voltage, a reference voltage based on the first supply voltage or based on a predetermined fraction of a second supply voltage; and
a pre-driver circuit comprising:
a first drive signal generation circuit for creating a first drive signal based on a data signal and feeding the first drive signal to a gate of one of the one or more pull-up transistors, including circuitry operable to shift a voltage level of the data signal to the second supply voltage as a digital high of the first drive signal and the reference voltage as a digital low of the first drive signal; and a second drive signal generation circuit for creating a second drive signal based on the data signal and feeding the second drive signal to a gate of one of the one or more pull-down transistors, including circuitry operable to create the second drive signal as a level-shifted version of the data signal with zero volts as a digital low value and the second supply voltage minus the reference voltage as a digital high value.
2. The data transmission circuit of claim 1 in which the one or more pull-up transistors
include a first transistor and a second transistor coupled in series between the positive
terminal and the output terminal, and the one or more pull-down transistors include a
third and fourth transistor coupled in series between the output terminal and the
negative terminal.

3. The data transmission circuit of claim 2, wherein a gate of the second transistor is configured to receive the reference voltage.
4. The data transmission circuit of claim 2, wherein the gate of the third transistor is configured to receive the second supply voltage minus the reference voltage.
5. The data transmission circuit of claim 1, wherein the first and second drive signal generation circuits are operable to maintain a gate-source voltage of the pull-up transistor during its activation equal to a gate-source voltage of the pull-down transistor during its activation.
6. The data transmission circuit of claim 5, wherein the first and second drive signal generation circuits are further operable to maintain the equal gate-source voltages across process, voltage, or temperature (PVT) variations in which the first and second supply voltages vary independently.
7. The data transmission circuit of claim 1, wherein the second drive signal generation circuit further comprises a voltage subtractor circuit receiving the second supply voltage and the reference voltage as inputs, and having an output of the second supply voltage minus the reference voltage.
8. The data transmission circuit of claim 7, wherein the second drive signal generation circuit further comprises an AND gate having inputs configured to receive the data signal and the reference voltage, the AND gate driven with a supply voltage of the second supply voltage minus the reference voltage.
9. The data transmission circuit of claim 1, in which the one or more pull-up transistors are PMOS transistors and the one or more pull-down transistors are NMOS transistors, the PMOS transistors and NMOS transistors having a maximum operating voltage higher than the first supply voltage and lower than the second supply voltage.

10. A method of operating a driver in an integrated circuit with multiple supply voltages,
the method comprising:
based on a presence of a first supply voltage and an absence of a second supply voltage, creating a reference voltage based on the first supply voltage;
based on a presence of the second supply voltage and an absence of the first supply voltage, creating the reference voltage as a predetermined fraction of the second supply voltage;
based on a presence of both the first supply voltage and the second supply voltage, creating the reference voltage from the first supply voltage;
receiving a data signal;
driving a gate of a pull-up transistor of the driver with a first drive signal based on the data signal shifted with the second supply voltage as a digital high and the reference voltage as a digital low; and
driving a gate of a pull-down transistor of the driver with a second drive signal based on the data signal shifted with the second supply voltage minus the reference voltage as a digital high and zero volts as a digital low.
11. The method of claim 10, in which driving the gate of the pull-up transistor and driving the gate of the pull down transistor further comprises maintaining a gate-source voltage of the pull-up transistor during its activation equal to a gate-source voltage of the pull-down transistor during its activation.
12. The method of claim 11, in which driving the gate of the pull-up transistor and driving the gate of the pull down transistor further comprises maintaining the equal gate-source voltages across process, voltage, or temperature (PVT) variations in which the first and second supply voltages vary independently.
13. The method of claim 10, further comprising applying the reference voltage to a gate of a second pull-up transistor of the driver.

14. The method of claim 10, further comprising applying the second supply voltage minus the reference voltage to a gate of a second pull-down transistor of the driver.
15. The method of claim 10, further comprising providing the second supply voltage minus the reference voltage with a voltage subtractor.
16. The method of claim 10, in which driving the gate of the pull-down transistor comprises performing an AND operation with the data signal and the reference voltage with an AND gate supplied with the second supply voltage minus the reference voltage.
17. The method of claim 10, in which creating the reference voltage based on the first supply voltage includes making the reference voltage equal to the first supply voltage, and in which creating the reference voltage as the predetermined fraction of the second supply voltage includes making the reference voltage equal to the second supply voltage divided by two.
18. A circuit comprising:
a reference voltage generation circuit operable to receive a first supply voltage and a second supply voltage having a supply voltage level higher than that of a device breakdown voltage on a host integrated circuit, and operable to respond to varying voltage supply conditions in which a driver may be subject to over voltage effects based on the second supply voltage by generating a reference voltage based the first supply voltage when the second supply voltage is not available, and based on the second supply voltage when the first supply voltage is not available;
a first drive signal generation circuit operable to generate a first gate voltage signal for a first pull-up transistor of the driver based on a data signal, the first gate voltage signal comprising digital high values at the second supply voltage, and digital low values at the reference voltage; and

a second drive signal generation circuit operable to generate a second gate voltage signal for a first pull-down transistor of the driver based on the data signal, the second gate voltage signal comprising digital high values at the second supply voltage minus the reference voltage, and digital low values at zero volts.
19. The circuit of claim 18, in which the first drive signal generating circuit further comprises circuitry coupling the reference voltage to a gate of a second pull-up transistor of the driver.
20. The circuit of claim 18, in which the second drive signal generating circuit further comprises circuitry connecting the second supply voltage minus the reference voltage to a gate of a second pull-down transistor of the driver.
21. The circuit of claim 18, which the first and second drive signal generation circuits are operable to maintain a gate-source voltage of the pull-up transistor during its activation equal to a gate-source voltage of the pull-down transistor during its activation.
22. The circuit of claim 21, wherein the first and second drive signal generation circuits are further operable to maintain the equal gate-source voltages across process, voltage or temperature (PVT) variations in which the first and second supply voltages vary independently.
23. The circuit of claim 18, in which the varying voltage supply conditions comprise a first condition including availability of the first supply voltage and unavailability of the second supply voltage, the reference voltage generation circuit further operable to respond to the first condition by making the reference voltage to be equal to the first supply voltage.

24. The circuit of claim 23, in which the varying voltage supply conditions comprise a second condition in which the first supply voltage is unavailable and the second supply voltage is available, the reference voltage generation circuit further operable to respond to the second condition by generating the reference voltage based on a predetermined fraction of the second supply voltage.
25. The circuit of claim 24, in which the varying voltage supply conditions comprise a third condition including availability of the first supply voltage and the second supply voltage, the reference voltage generation circuit further operable to respond to the third condition by making the reference voltage equal to the first supply voltage.
26. The circuit of claim 18, wherein the second drive signal generating circuit further comprises a voltage subtractor circuit having the second supply voltage and the reference voltage coupled as inputs and an output of the second supply voltage minus the reference voltage.
27. The circuit of claim 18, wherein the second drive signal generating circuit further comprises an AND gate having inputs configured to receive the data signal and the reference voltage, and an output providing second gate voltage signal, the AND gate supplied with the second supply voltage minus the reference voltage.
28. A method of operating a driver in semiconductor circuit having a first supply voltage and a second supply voltage, the method comprising:
in response to a first condition in which the driver may be subject to over voltage conditions based on the second supply voltage having a supply voltage level higher than that of a device breakdown voltage on the semiconductor circuit, generating a reference voltage based on a predetermined fraction of the second supply voltage;
receiving a data signal;

in response the first condition, generating a first gate voltage signal for a first pull-up transistor of the driver based on the data signal, the first gate voltage signal comprising digital high values at the high supply voltage, and digital low values at the reference voltage; and
in response the first condition, generating a second gate voltage signal for a first pull-down transistor of the driver based on the data signal, the second gate voltage signal comprising digital high values at the high supply voltage minus the reference voltage, and digital low values at zero volts.
29. The method of claim 28, further comprising applying the reference voltage to a gate of a second pull-up transistor of the driver.
30. The method of claim 28, further comprising applying the high supply voltage minus the reference voltage to a gate of a second pull-down transistor of the driver.
31. The method of claim 28, further comprising maintaining a gate-source voltage of the first pull-up transistor during its activation equal to a gate-source voltage of the first pull-down transistor during its activation.
32. The method of claim 31, further comprising maintaining the equal gate-source voltages across process, voltage, or temperature (PVT) variations in which the first and second supply voltages vary independently.
33. The method of claim 28, further comprising:
in response to a second condition in which the driver may be subject to over voltage conditions based on the second supply voltage, the second condition including enablement of the first supply voltage the second condition, generating the reference voltage at a new value based on the first supply voltage;

after generating the reference voltage based on the first supply voltage, generating the first gate voltage signal based on the data signal, the first gate voltage signal comprising digital high values at the second supply voltage, and digital low values at the reference voltage; and
after generating the reference voltage based on the first supply voltage, generating the second gate voltage signal, the second gate voltage signal comprising digital high values at the second supply voltage minus the reference voltage, and digital low values at zero volts.
34. The method of claim 33, further comprising, after generating the reference voltage based on the first supply voltage, applying the reference voltage to a gate of a second pull-up transistor of the driver.
35. The method of claim 33, further comprising, after generating the reference voltage based on the first supply voltage, applying the second supply voltage minus the reference voltage to a gate of a second pull-down transistor of the driver.