FIELD OF THE INVENTION
The purpose of this invention is to present the algorithm for architecture design of
hardcoded watchdog timer for resetting the nonfunctioning or trapped SSFDR in case
of Firmware malfunctioning.
BACKGROUND OF THE INVENTION
During the time of flight, it is required to record the critical parameters of aircraft.
Various parameters in aircraft have sensors which generate different voltages
equivalent to Engineering values of Line Replaceable Unit. The generated voltage is
processed through various modules and acquired in SSFDR. SSFDR stored these
values in memory module after processing the data and adding some internal
information of the SSFDR. After completion of flight, these data is downloaded from
memory and analyzed using ground equipment. To carry out proper functioning of
the SSFDR, it is necessary for the Boards to work their functionality properly and not
to malfunction due to a hardware malfunction or software trapping. For proper
functioning of the CPU, the CPU is equipped with some form of internal breakout
from the trapping of the software, the purpose of which is detection and subsequent
breaking of the software loop.
In prior data recording systems, if the CPU locks up during execution of the particular
intended task, the user has to ascertain by looking at the fault displays of the system
that the problem has occurred and the user has to manually reset the system by
means of a dedicated hardware reset. Accordingly, the prior data recorders fail to
provide a means by which a locked up system can be resetted without user
intervention.
SUMMARY OF PRESENT INVENTION
In accordance with one aspect of present invention is to provide a technique
according to which SSFDR trapped or malfunctioning due to software can be
hardware resetted when the watchdog timeout has been occurred.
In accordance with another aspect of present invention is to provide a method to
continuously monitor the CPU for any loop that is being occurred in the system apart
from the intended work of the system.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1: it shows the block diagram of SSFDR system.
Figure2: Flow Chart of Watchdog timer functioning
DETAILED DESCRIPTION
Figure 1 illustrates the block diagram of a SSFDR system within which the present
invention can operate. Since the present invention is not limited to only this kind of
SSFDR and hence this invention can also be used in similar type of SSFDR’s and also
to future SSFDR’s. The processor module in this diagram is equipped with a high end
processor which is the core of the SSFDR.
Figure 2 illustrate the block diagram of the present invention. The programmable
interrupt controller (PIC) in the CPU (processor of the board) is responsible for
receiving maskable and non maskable interrupts destined for the CPU of the
processor module of figure 1.
In the present invention the watchdog timer is hardcoded with a pre‐defined value
of time into Periodic interrupt timer register which represent a value of time
sufficient to allow the CPU to execute the intended purpose of the CPU so that the
CPU don’t reset itself during the long execution of itself. The PIC is adapted to
produce a non maskable interrupt that triggers hardware reset of the CPU. A
watchdog timer coupled to CPU within the processor module to enable the
watchdog timer to receive a start signal from the CPU indicating that the CPU is
beginning to measure the preselected period of time upon expiration of the
preselected period of time and a reset signal, capable of receiving the timeout signal
from the watchdog timer and providing, in response thereby allow the reset of the
CPU when the SSFDR is nonfunctioning.

WE CLAIMS:-
Accordingly, the description of the present invention is to be considered as illustrative only and is for the purpose of teaching those skilled in the art of the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and exclusive use of all modifications which are within the scope of the appended claims is reserved. We Claim

1. This procedure is for resetting a nonfunctioning or trapped SSFDR.
2. This procedure is based around a dedicated hardware circuitry and its corresponding Firmware.
3. This procedure can be used for existing and future data recording system or in any other areas where signals are acquired and stored.
4. This procedure is for a watchdog timer which is a real time clock coupled to the CPU of the SSFDR.
5. This procedure is for a system in which the preselected time period of Watchdog is a period of time sufficient to allow the processor to execute its task. ,TagSPECI:As per Annexure-II