TITLE: Hardware Based Lock Protection for reset control register.
FIELD OF THE INVENTION:
The present invention relates to a hardware based lock protection for reset control register and more particularly to hardware based lock protection for reset control register in multi processor environment.
BACKGROUND OF THE INVENTION :
Generally, embedded system design incorporates many peripherals/slaves like UART (universal asynchronous receiver transmitter). These peripherals need reset signals to avoid deadlock and work properly. Device like watchdog timer is used to provide reset signal to the peripherals. The process of resetting of the peripherals by the watchdog timer is called 'ticking action' of the watchdog timer. To keep a watchdog timer from unnecessary ticking/resetting the system, it is required to kick watchdog timer regularly. The process of restarting the watchdog timer's counter is called 'kicking of the watchdog timer'. The software directly controls the reset signal and kicking of the watchdog timer. However, there are possibilities of bugs/malfunctioning in the software. The watchdog timer and other software controlled resetting devices may reset its peripherals unconditionally due to software bugs. Therefore, in software controlled reset of peripherals, reset takes place without verifying whether the reset signal is genuine or not.
US Patent document 4686526 claims a remote reset circuit controller which fixes any bug before reset by clocking in each character sent by a terminal to a computer and comparing it to a given reference character. When match occurs,

the remote reset circuit activates the system's hardware reset line. However, it may deal with a system where the reset is external/ remote and not a part of the whole system.
Another US Patent document 6061810 claims a computer system, which includes error handling hardware and software that logs the source of application program or system software errors before a reset occurs. Upon a catastrophic error, a retriggerable timer, which is periodically retriggered during normal system operation, instead times out causing a hardware reset. A predetermined time before this retriggerable timer times out, however, the microprocessor in the computer system is interrupted. The interrupted microprocessor executes an interrupt routine in which it determines that the retriggerable timer is about to timeout, and logs the currently executing applications program or currently executing point in system software, as well as the actual location within the applications program or the system software. The reset subsequently occurs, but not before this information valuable for debugging and diagnosis is logged. In the cited invention valuable information for debugging and diagnosis is required to be logged before reset occurs. Therefore, this system is complex and not effective in providing protection against wrong reset.
Therefore, in a system where high level of safety is required with respect to functioning of the unit, especially in patient critical monitoring equipment, an effective protection is required against wrong resetting of the peripherals due to software bugs or any other problem.

SUMMARY OF THE INVENTION:
An object of the present invention is to provide an effective protection against wrong resetting of the peripheral due to software bugs or any other malfunction.
Further object of the present invention is to provide said protection in the hardware level itself.
According to one embodiment of the present invention a hardware based lock protection for reset control registers, comprises a peripheral performing a particular task, a high capacity programmable logic device (HCPLD) for resetting the peripheral after being incited and a controller for inciting the HCPLD to reset the respective peripherals.
According to the present invention the HCPLD includes number of lock register depending on the number of peripherals. The controller accesses the lock registers via an address bus, a chip select and a data bus. Said accessing takes place in a particular coded sequence. The coded sequence is compared with a predetermined sequence coded inside the HCPLD (80). If match occurs, the HCPLD (80) resets the respective peripheral.
Details of the instant invention and further objects thereof will become evident as the description proceeds and from an examination of the accompanying drawings, which illustrate preferred embodiment of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS:
Fig 1 shows the diagrammatic representation of the hardware based lock
protection for reset control register.
Fig 2 illustrates the generation of the wrong coding sequence due to one of the
types of the software bug created while executing multithreaded application.
Fig 3 illustrates the generation of wrong coding sequence due to a type of the
software bug created while executing single application for a peripheral.
Fig 4 illustrates the possible paths generating wrong coded sequence due to
noise or the like problems.
DETAILED DESCRIPTION OF THE INVENTION:
The present invention describes in conjunction with the accompanying drawing a hardware based lock protection for reset control register in multi processor environment. The system provides an effective protection against wrong resetting of the peripherals due to software bugs or other malfunction like corruption in the memory.
As per the present invention, the protection against wrong resetting is provided in the hardware level.
According to one embodiment of the present invention and as represented in figure 1 block diagram of a hardware based lock protection for reset control register is shown.
The hardware based lock protection for reset control register comprises a controller (10), a high capacity programmable logic device (HCPLD) (80) and a peripheral to perform a particular task. The peripheral may be a UART, a

watchdog timer, a NIBP (Non Invasive Blood Pressure) system and the like. Each peripheral performs a specified task and is concerned with some data. For example, the NIBP (Non Invasive Blood Pressure) system provides the BP (Blood Pressure) data. Each peripheral is connected to the HCPLD (80). The HCPLD (80) includes lock registers (50, 60 and 70). The number of lock register depends upon the number of connected peripherals. For example if three peripherals (100, 110 and 120) are connected to the HCPLD (80), there will be three lock registers (50, 60 and 70) inside the HCPLD (80). The lock registers (50, 60 and 70) of the HCPLD (80) are accessed by the controller (10) via an address bus (40), a data bus (30) and a chip select (20) in a particular coded sequence. The coded sequence is matched against a predetermined sequence, which is coded inside the HCPLD (80) in the Very High Speed IC Hardware Description Language (VHDL) or the like. If the predetermined sequence matches the coded sequence, the HCPLD (80) reset the respective peripherals (100, 110 and 120). Therefore, the HCPLD (80) controls the reset of the peripherals (100, 110 and 120) and avoid wrong resetting.
Figure 2 illustrates the generation of the wrong coding sequence due to one of the types of the software bug created while executing multithreaded application. The figure shows in multiprocessing environment, the application (a1 and a2) meant for the peripherals (100 and 110) respectively. For controlling the peripheral (100), the application (a1) is running. As the application (a1) is being executed, the value of the chip select (20) and the data bus (30) is set. Said value is based on the application (a1). The application (a1) may get interrupted due to some bug or other malfunction. The bug may switches the application (a1) to a reset function of the application (a2). Now, the reset function of the

application (a2) is being executed. The executed function of the application (a2) generates the reset signal (90) for the peripheral (110). Based on the peripheral (110), the value of the address bus (40) is set. Now, the value of the address bus (40) is of the peripheral (110) while the value of the chip select (20) and the data bus (30) is of the peripheral (100). Therefore, a wrong coded sequence is generated by these values. The generated coded sequence does not match any of the predetermined sequence, stored inside the HCPLD (80). The HCPLD (80) matches the coded sequence with the predetermined sequence. The match does not occur; hence, neither of the peripherals (100 and 110) is reset by the HCPLD (80). The HCPLD (80), therefore, avoids wrong resetting of any of the peripherals (100 and 110).
Figure 3 illustrates the generation of wrong coding sequence due to another type of the software bug created while executing single application for a peripheral. The figure shows an application (a3) being executed for the peripheral (120). The application (a3) provides a condition for resetting the peripheral (120). When the condition is checked, the value of the chip select (20) and the data bus (30) is set. If the condition is satisfied, a reset function of the application (a3) is executed. Based on the reset function of the application (a3), the value of the address bus (40) is set. The value of the address bus (40) is set while the reset function of the application (a3) is executed. It may be possible that the reset function is executed unconditionally (without checking the condition) due to some software bug or other malfunction. But, due to unconditional execution (without checking the condition) the value of the chip select (20) and the data bus (30) is not set to the desired value. Therefore, a wrong coded sequence is formed by these values. The formed coded sequence does not match the predetermined

sequence, stored inside the HCPLD (80). The HCPLD (80) matches the coded sequence with the predetermined sequence. The match does not occur; hence, the HCPLD (80) avoids the wrong resetting of the peripherals (120).
Fig 4 and 4a illustrates the possible paths generating wrong coded sequence due to noise or the like problems. The figure shows the application (a1) executing for the peripheral (100). For the peripheral (100), the required value of the chip select (20), the data bus (30) and the address bus (40) has been set. Said value may get corrupted due to noise signal or the like malfunction. The noise signal or the other unwanted signal may corrupt the value of the chip select (20), the data bus (30), the address bus (40) or all of them. Due to said corruption a wrong coded sequence is generated. The generated coded sequence does not match any of the predetermined sequence, stored inside the HCPLD (80). The HCPLD (80) matches the coded sequence with the predetermined sequence. The match does not occur; hence, the peripheral (100) is not reset by the HCPLD (80). The HCPLD (80), therefore, avoids wrong resetting of the peripheral (100).
The present invention therefore, provides the logical device like HCPLD to reset the peripherals. The HCPLD issues the reset signal to the respective peripherals only after verifying if the reset signal is genuine and meant for the peripheral. The reset signal may get corrupted due to noise or other unwanted signals. The corrupted signal may provide wrong information and required to be verified. The reset signal is verified in the hardware level for any corruption/ bug. Therefore, the invention provides a simplified and an effective method of protection against any bugs or corruption in the memory especially protection against wrong

resetting of peripherals due to noise etc. Moreover, said method of protection is provided in the hardware level itself.
The invention provides a high degree of protection where an effective safety/security is required against wrong resetting of the peripheral especially in patient critical monitoring equipment;
The foregoing description of the invention has been set for merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the appended claims and equivalents thereof.

WE CLAIM :
1.) A hardware based lock protection for reset control register, comprising:
a peripheral performing a particular task;
a high capacity programmable logic device (HCPLD) for resetting the peripheral
after being incited; and
a controller for inciting the high capacity programmable logic device (HCPLD).
2.) A hardware based lock protection for reset control registers as claimed in claim 1, wherein said peripheral is a watchdog timer, a NIBP (Non Invasive Blood Pressure) module, a UART and the like.
3.) A hardware based lock protection for reset control registers as claimed in claim 1, wherein said HCPLD is a complex programmable logic device (CPLD), a field programmable gate array (FPGA) and the like.
4.) A hardware based lock protection for reset control registers as claimed in claim 1, wherein said HCPLD comprises n lock register and wherein n is the number of peripherals.
5.) A hardware based lock protection for reset control registers as claimed in claim 4, wherein said controller accesses the lock register via an address bus, a data bus and a chip select in a particular coded sequence.
6.) A hardware based lock protection for reset control registers as claimed in claim 5, wherein said incitation occurs when coded sequence matches a predetermined sequence.

7.) A hardware based lock protection for reset control registers as claimed in claim 6, wherein said predetermined sequence is coded inside HCPLD.
8.) A hardware based lock protection for reset control registers as claimed in claim 7, wherein said coding is in very high speed IC hardware description language (VHDL).