DESCRIPTION OF INVENTION:
The present invention provides hardware for interfacing big endian and little endian system through a programmable logic device.
In various embodiments of the invention, the big endian system may include a Power Personal computer herein referred to as (PPC) having the bytes stored in big endian byte order. The PPC having the big endian system include various buses that help in data transfer. The programmable logic device may include a Complex Programmable Logic Device (CPLD). The Complex Programmable Logic Device (CPLD) may have macro cell as its building block. These macro cells may contain logic implementing disjunctive normal form expressions and more specialized logic operations. The CPLD generally comprises an in-built non-volatile memory and does not require any an external non-volatile memory enabling the CPLD to function immediately on system start-up. The CPLD contains large number of gates. Typically of thousands to tens of thousands of logic gates, allowing implementation of moderately complicated data processing devices.
CPLD provides various busses, which are the conducting lines, used for the data transfer within a computer system. These data transfer lines comprises address lines, data lines, control lines these lines may also include transfer size lines that indicate the size of the bits being transferred.
Figure 1 shows the hardware interface for facilitating communication between big endian system (10) and little endian system (30). The interface comprises a set of address lines (11) for transmitting a desired address location from said big endian system (10) to said little endian system (30). The programmable device (20) or the CPLD (20) provides a first set of data lines (12) for receiving data signals from big endian system (10) and a second set of data lines (12A) for sending the received data signals to said little endian system (30). The CPLD (20) also provides a first set of byte select lines (13) for receiving byte select signals from big endian system (10) and a second set of data lines (13A) for sending the received byte select signals to said little endian system (30).
A set of transfer_size lines (14) for receiving transfer_size signal from the big endian system (10) is provided. The address location 'n' of the big endian system (10) is mapped to address location 'n' of the little endian system (30) and the byte order of received data signal is reversed and the data signal in reversed order is then transmitted to said little endian system (30).
As per the present invention, the data lines (12 and 12A) and the byte select lines (13 and 13A) of big endian (10) are routed through the Complex Programmable Logic Device (CPLD) (20) to the little endian system (30). Internal to the CPLD (20), address invariant method is used wherein an address location in Big Endian System (10) is mapped to corresponding address location in Little Endian System (30) through the address lines (11). For example address location 1001 of the BIG endian system may be mapped to the corresponding address 1001 of the little endian system.
Further, for half-word and word accesses; byte swapping is done in the CPLD (20) wherein words are determined by transfer size signals (14) termed as TSIZ0 and TSIZ1 signals of the PowerPC Processor (10) as shown in the figure 1.
Figure 2 is a flowchart illustrating the method for facilitating communication between big endian system and little endian system. The method comprises the steps of transmitting a desired address location from said big endian system to said little endian system over a set of address lines (40); configuring a programmable device for receiving from said big endian system a plurality of data signals, byte select signals and transfer size signals corresponding to said data signals (42); mapping the address location 'n' of the big endian system to address location 'n' of the little endian system (44); reversing the byte order of received data signal (46); transmitting the data signal in reversed order to said little endian system (48).
Thus the CPLD receives the data from big endian system as MSB (Most Significant Byte) first and LSB (Least Significant Byte) last. However, after processing the received data the CPLD sends the data to little endian system as MSB (Most Significant Byte) last and LSB (Least Significant Byte) first.
Similarly, The CPLD receives the data from little endian system as MSB (Most Significant Byte) last and LSB (Least Significant Byte) first. However, after processing the received data the CPLD sends the data to big endian system as MSB (Most Significant Byte) first and LSB (Least Significant Byte) last.
Hence both big endian and little endian systems send and receiveis the data in their respective byte orders through the interface solution as per the described invention.

WE CLAIM:
1. A hardware interface for facilitating communication between big endian system and little endian system, the interface comprising:
a set of address lines for transmitting a desired address location from said big endian system to said little endian system;
a programmable device having:
a first set of data lines for receiving data signals from big endian system and a second set of data lines for sending the received data signals to said little endian system;
a first set of byte select lines for receiving byte select signals from big endian system and a second set of data lines for sending the received byte select signals to said little endian system;
a set of transfer_size lines for receiving transfer_size signal from the big endian system;
wherein the address location 'n' of the big endian system is mapped to address location 'n' of the little endian system and the byte order of received data signal is reversed and the data signal in reversed order is then transmitted to said little endian system;
2. The hardware interface as in claim 1 wherein the programmable device is a complex programming logic device (CPLD).
3. The hardware interface as in claim 1 wherein the programmable device maps the address location 'n' of the big endian system to address location 'n' of the little endian system through address invariant method.
4. The hardware interface as in claim 1 wherein the set of transfer_size lines carry TSIZO and TSIZ1 signals for determining the size of the data being communicated between the big endian system and little endian system.
5. The hardware interface as in claim 1 wherein the programmable device performs byte swapping for half-word and word accesses.
6. A method for interfacing between big endian system and little endian system, the method comprising the steps of:
transmitting a desired address location from said big endian system to said little endian system over a set of address lines;
configuring a programmable device for:
receiving from said big endian system a plurality of data signals, byte select signals and transfer_size signals corresponding to said data signals;
mapping the address location 'n' of the big endian system to address location 'n' of the little endian system;
reversing the byte order of received data signal;
transmitting the data signal in reversed order to said little endian system;
7. The method as claimed in claim 6, wherein the programmable device is a complex programming logic device (CPLD).
8. The method as claimed in claim 6, wherein the programmable device maps the address location 'n' of the big endian system to address location 'n' of the little endian system through address invariant method.
9. The method as claimed in claim 6, wherein the wherein the set of transfer_size lines carry TSIZO and TSIZ1 signals for determining the size of the data being communicated between the big endian system and little endian system.
10. The method as claimed in claim 6, wherein the programmable device reversing the byte order of received data signal by performing byte swapping.
Dated this ^(iay of 'fdoawl,
FOR LARSEN & TOUBRO LIMITED By their Agent
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