1. A harmonic cancelation unit for harmonic cancelation in power based device, comprising: a processor; and a memory communicatively coupled to the processor, wherein the memory stores processor-executable instructions, which, on execution, causes the processor to: determine a dominant harmonic with highest magnitude of plurality of harmonics in waveform from power grid when first Total Harmonic Distortion (THD) in grid current of the power based device is greater than a predefined value; perform Phased Locked Loop (PLL) based correction in the waveform to obtain PLL corrected waveform; determine second THD in the PLL corrected waveform; and perform iterative based correction on the plurality of harmonics other than the dominant harmonic when the second THD is greater than the predefined value to obtain iterative based corrected waveform for harmonic cancelation in the power based device.

2. The harmonic cancelation unit as claimed in claim 1, wherein the iterative based correction comprises: determining third THD in the iterative based corrected waveform; and performing the iterative correction to the iterative based corrected waveform until the third THD is greater than the predefined value.

3. The harmonic cancelation unit as claimed in claim 1, wherein the iterative based correction is performed for a predefined correction value.

4. The harmonic cancelation unit as claimed in claim 3, wherein the iterative based correction further comprises: determining previous third THD in the iterative based corrected waveform; incrementing the predefined correction value by a predefined increment value when the third THD is greater than the previous third THD; and decrementing the predefined correction value by the predefined decrement value when the third THD is lesser than the previous third THD.

5. The harmonic cancelation unit as claimed in claim 1, wherein the waveform from the power grid is voltage waveform.

6. The harmonic cancelation unit as claimed in claim 1, wherein the PLL based correction performs synchronisation of internal reference associated with the power based device with the dominant harmonic with highest magnitude.

7. A system for harmonic cancelation in power based device, comprising: a current based control unit to provide modulating waveform based on the grid current of the power based device; a harmonic cancelation unit comprising: a processor; and a memory communicatively coupled to the processor, wherein the memory stores processor-executable instructions, which, on execution, causes the processor to: determine a dominant harmonic with highest magnitude of plurality of harmonics in waveform from power grid when first Total Harmonic Distortion (THD) in the grid current is greater than a predefined value; perform Phased Locked Loop (PLL) based correction in the waveform to obtain PLL corrected waveform; determine second THD in the PLL corrected waveform; and perform iterative based correction on the plurality of harmonics other than the dominant harmonic when the second THD is greater than the predefined value to obtain iterative based corrected waveform for harmonic cancelation in the power based device; and a Pulse Width Modulation (PWM) generator to provide modulated waveform based on the modulating waveform and one of PLL corrected waveform and iterative based corrected waveform, wherein the modulated waveform is provided to the power based device for harmonic cancelation.

8. The system as claimed in claim 7, wherein the iterative based correction comprises: determining third THD in the iterative based corrected waveform; and performing the iterative correction to the iterative based corrected waveform until the third THD is greater than the predefined value.

9. The harmonic cancelation unit as claimed in claim 7, wherein the iterative based correction is performed for a predefined correction value.

10. The harmonic cancelation unit as claimed in claim 9, wherein the iterative based correction further comprises: determining previous third THD in the iterative based corrected waveform; incrementing the predefined correction value by a predefined increment value when the third THD is greater than the previous third THD; and decrementing the predefined correction value by the predefined decrement value when the third THD is lesser than the previous third THD.

11. A method for harmonic cancelation in power based device, comprising: determining, by a harmonic cancelation unit, a dominant harmonic with highest magnitude of plurality of harmonics in waveform from power grid when first Total Harmonic Distortion (THD) in grid current of the power based device is greater than a predefined value; performing, by the harmonic cancelation unit, Phased Locked Loop (PLL) based correction in the waveform to obtain PLL corrected waveform; determining, by the harmonic cancelation unit, second THD in the PLL corrected waveform; and performing, by the harmonic cancelation unit, iterative based correction on the plurality of harmonics other than the dominant harmonic when the second THD is greater than the predefined value to obtain iterative based corrected waveform for harmonic cancelation in the power based device. Dated this 29th day of September, 2015 R Ramya Rao Of K&S Partners Agent for the Applicant , Description:FORM 2 THE PATENTS ACT 1970 [39 OF 1970] & THE PATENTS RULES, 2003 COMPLETE SPECIFICATION [See section 10 and Rule 13] TITLE: “HARMONIC CANCELATION UNIT AND A METHOD THEREOF” Name and Address of the Applicant: HITACHI, LTD., 6-6, Marunouchi 1-chome, Chiyoda-ku, Tokyo, Japan. Nationality: Japan The following specification particularly describes the invention and the manner in which it is to be performed. TECHNICAL FIELD The present subject matter generally relates to harmonic cancelation. More particularly, but not exclusively, the present disclosure discloses a system and a method for harmonic cancelation in power based devices. BACKGROUND Figure 1 illustrates a system implementing a conventional harmonic cancelation unit. The system as shown in Figure 1 implementing a conventional harmonic cancelation unit comprises a power based device 101, power grid 102, current based control unit 103 and a conventional harmonic cancelation unit 104. The power based device 101 may be one of converter (AC to AC and DC to DC), rectifier (AC to DC) and inverter (DC to AC). Waveform from the power based device 101 is supplied to the power grid 102 and there may be harmonics in the power waveform which is caused due to non-linear electric loads. Elimination or reduction of the harmonics is performed by implementing a conventional harmonic cancelation unit 104 along with the current based control unit 103. Grid injected current from the power based device 101 is provided to the current based control unit 103 as a reference to obtain modulating waveform. Further, the conventional harmonic cancelation unit 104 performs the required correction by obtaining the grid injected current from the power based devices 101 for reduction or elimination of the harmonics and to obtain corrected waveform. The corrected waveform is further modulated with the modulating waveform to obtain corrected grid current and supplied to the power based device 101. Figure 2 illustrates a flow diagram showing steps performed by a conventional harmonic cancelation unit. At block 201, grid injected current is obtained. At block 202, modulating waveform is obtained by providing grid injected current to the current based control unit 103. At block 203, harmonics in the grid injected current by Fast Fourier Transform (FFT) analysis is determined. At block 204, proportional integration correction on the determined harmonics is performed to obtain proportional integration corrected waveform. At block 205, corrected modulated waveform is obtained which is based on the modulating waveform and the proportional integration corrected waveform. In the conventional harmonic cancelation unit 104, harmonic cancelation requires information of magnitude and phase of individual harmonic determined in waveform from the power based devices. Desired correction in the waveform is obtained based on the information. In some embodiments, the said correction is a time consuming process. Further real-time information of the magnitude and the phase of the harmonics should be obtained to eliminate harmonics. Mismatches in the real-time information obtained, due to delay in calculation, can cause adverse effect on performance of the power based devices. Also, real-time phase correction to nullify the harmonics in the power based devices is difficult. In a highly distorted grid, magnitude and phase of harmonics will be varying in nature with respect to time and when obtained in real-time, the magnitude and phase may not be accurate. Hence, a technique to calculate magnitude and phase information of harmonics is required for harmonic correction. Further, a method to reduce the calculated time and have a desired result is required. SUMMARY One or more shortcomings of the prior art are overcome and additional advantages are provided through the present disclosure. Additional features and advantages are realized through the techniques of the present disclosure. Other embodiments and aspects of the disclosure are described in detail herein and are considered a part of the claimed disclosure. Accordingly, a harmonic cancelation unit for harmonic cancelation in power based device which is disclosed in the present invention. The harmonic cancelation unit comprises a processor and a memory. The memory is communicatively coupled to the processor where the memory stores processor-executable instructions which on execution cause the processor to determine a dominant harmonic with highest magnitude of plurality of harmonics in waveform from power grid when first THD in grid current of the power based device is greater than a predefined value. Upon the determination, the processor performs PLL based correction in the waveform to obtain PLL corrected waveform and determines second THD in the PLL corrected waveform. Also, the processor performs iterative based correction on the plurality of harmonics other than the dominant harmonic when the second THD is greater than the predefined value to obtain iterative based corrected waveform for harmonic cancelation in the power based device. Further, the present disclosure discloses a system for harmonic cancelation in power based device. The system comprises a current based control unit, harmonic cancelation unit and a Pulse Width Modulation (PWM) generator. The current based control unit provides modulating waveform based on the grid current of the power based device. The harmonic cancelation unit is configured to function as described above. The PWM generator provides modulated waveform based on the modulating waveform and one of PLL corrected waveform and iterative based corrected waveform wherein the modulated waveform is provided to the power based device for harmonic cancelation. Further, the present disclosure discloses a method for harmonic cancelation which comprises a harmonic cancelation unit which performs determining a dominant harmonic with highest magnitude of plurality of harmonics in waveform from power grid when first Total Harmonic Distortion (THD) in grid current of the power based device is greater than a predefined value, performing Phased Locked Loop (PLL) based correction in the waveform to obtain PLL corrected waveform, determining second THD in the PLL corrected waveform and performing iterative based correction on the plurality of harmonics other than the dominant harmonic when the second THD is greater than the predefined value to obtain iterative based corrected waveform for harmonic cancelation in the power based device. The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects and features described above, further aspects, and features will become apparent by reference to the drawings and the following detailed description. BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, serve to explain the disclosed principles. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the figures to reference like features and components. Some embodiments of system and/or methods in accordance with embodiments of the present subject matter are now described, by way of example only, and with reference to the accompanying figures, in which: Figure 1 illustrates a system implementing a conventional harmonic cancelation unit; Figure 2 illustrates a flow diagram showing steps performed by a conventional harmonic cancelation unit; Figure 3 illustrates an exemplary embodiment of a system implementing a harmonic cancelation unit in accordance with one embodiment of the present disclosure; Figure 4 illustrates a detailed block diagram of an exemplary harmonic cancelation unit with various data and modules for harmonic cancelation in a power based device in accordance with some embodiments of the present disclosure; Figure 5 illustrates a flow diagram showing steps performed by a harmonic cancelation unit in accordance with some embodiments of the present disclosure; Figure 6 illustrates a flow diagram showing steps performed by an iterative based correction module in accordance with some embodiments of the present disclosure; and Figure 7 illustrates a block diagram of an exemplary computer system for implementing some embodiments consistent with the present disclosure. It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative systems embodying the principles of the present subject matter. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudo code, and the like represent various processes which may be substantially represented in computer readable medium and executed by a computer or processor, whether or not such computer or processor is explicitly shown. DETAILED DESCRIPTION The foregoing has broadly outlined the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific aspect disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. In the present document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example in the drawings and will be described in detail below. It should be understood, however that it is not intended to limit the disclosure to the particular forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternative falling within the spirit and the scope of the disclosure. The terms “comprises”, “comprising”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by “comprises… a” does not, without more constraints, preclude the existence of other elements or additional elements in the system or apparatus. The present disclosure relates to a harmonic cancelation unit and method for harmonic cancelation in power based device. Harmonic cancelation is performed by determining a dominant harmonic with highest magnitude of plurality of harmonics in waveform from power grid when first Total Harmonic Distortion (THD) in grid current of the power based device is greater than a predefined value. Further, Phased Locked Loop (PLL) based correction is performed in the waveform to obtain PLL corrected waveform and second THD in the PLL corrected waveform is determined. When the second THD is greater than the predefined value, iterative based correction for a predefined correction value is performed on the plurality of harmonics other than the dominant harmonic to obtain iterative based corrected waveform for harmonic cancelation in the power based device. In the following detailed description of the embodiments of the disclosure, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure, and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the present disclosure. The following description is, therefore, not to be taken in a limiting sense. Figure 3 illustrates an exemplary embodiment of a system implementing a harmonic cancelation unit in accordance with some embodiments of the present disclosure. The system as shown in Figure 3 for harmonic cancelation in a power based devices comprises a power based device 301, power grid 302, current based control unit 303, a harmonic cancelation unit 304 and a PWM generator 305. The power based device 301 may include, but is not limited to, AC to AC converter, rectifier and inverter. Waveform from the power based device 301 is one of supplied to and received from the power grid 302 and there may be harmonics in the waveform which is caused due to non-linear electric loads. In one embodiment of the present disclosure, the waveform may be grid voltage waveform obtained from the power based device 301 for extraction of harmonic information and harmonic cancelation. In another embodiment, the waveform may be grid current used for extraction and harmonic cancelation. Further, in the present disclosure, elimination or reduction of these harmonics is performed by implementing the harmonic cancelation unit 304 along with the current based control unit 303. Grid injected current from the power based device 301 is provided to the current based control unit 303 as a reference to obtain modulating waveform. Further, the harmonic cancelation unit 304 performs required correction by obtaining the grid injected current from the power based devices 301 and one of reduction and elimination of the harmonics is performed to obtain corrected waveform. The corrected waveform is further modulated with the modulating waveform by implementing the PWM generator 305 to obtain modulated waveform and supplied to the power based device 301. The modulated waveform may be one of harmonics eliminated waveform or harmonics reduced waveform. Figure 4 illustrates a detailed block diagram of an exemplary harmonic cancelation unit with various data and modules for harmonic cancelation in a power based device in accordance with some embodiments of the present disclosure. The harmonic cancelation unit 304 comprises of I/O interface 401, processor 402 and memory 403. In one implementation, the harmonic cancelation unit 304 may be implemented in a variety of computing systems, such as a laptop computer, a desktop computer, a Personal Computer (PC), a notebook, a smartphone, a tablet, e-book readers (e.g., Kindles and Nooks), a server, a network server, and the like. In one embodiment, the harmonic cancelation unit 304 receives the waveform from the power grid 302 through I/O interface 401. Also, the I/O interface 401 may provide output of the harmonic cancelation unit 304 in a form of the corrected waveform. In one embodiment, the result may be provided on a display unit (not shown in Figure). Further, the I/O interface 401 is coupled with the processor 402 of the harmonic cancelation unit 304. The memory 403 in the harmonic cancelation unit 304 is communicatively coupled to the processor 402. The memory 403 stores processor executable instructions which on execution help the harmonic cancelation unit 304 to cancel the harmonics in the power waveform. The processor 402 may comprise at least one data processor comprising modules 404 and data 410 for determining a dominant harmonic with highest magnitude of plurality of harmonics in waveform from power grid 302 when first THD in grid current of the power based device 301 is greater than a predefined value. Upon the determination, the processor 402 performs PLL based correction in the waveform to obtain PLL corrected waveform and determines second THD in the PLL corrected waveform. Also, the processor 402 performs iterative based correction on the plurality of harmonics other than the dominant harmonic when the second THD is greater than the predefined value to obtain iterative based corrected waveform for harmonic cancelation in the power based device. In one embodiment the first THD and second THD value are same. In the illustrated Figure 4, the data 410 and the modules 404 stored in the memory 403 are described herein in detail. In an embodiment, the data 410 in the memory 403 are processed by the one or more modules 404 of the harmonic cancelation unit 304. The modules 404 may be stored within the memory 403 as shown in Figure 4. In an example, the one or more modules 404, communicatively coupled to the processor 402, may also be present outside the memory 403 and implemented as hardware. As used herein, the term module refers to an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. In one embodiment, the data 410 may include, for example, waveform from power grid 411, PLL corrected waveform 412, iterative corrected waveform 413, THD 414, predefined value 415, predefined correction value 416, predefined increment value 417, predefined decrement value 418 and other data 419. The waveform from the power grid 411 is used to extract harmonic information in the power based device 301 and for harmonic cancelation. In the present disclosure, the waveform is grid voltage waveform obtained from the power grid 302. In one embodiment, the waveform may be grid current. The PLL corrected waveform 412 is obtained upon performing PLL based correction to the waveform 411 in the harmonic cancelation unit 304. The PLL corrected waveform 412 is further corrected using iterative based correction when the second THD in the PLL based corrected waveform is greater than the predefined value. When the predefined value is lesser than the predefined value, then the iterative based correction is not required and the PLL corrected waveform is considered as the corrected waveform. The iterative corrected waveform 413 is obtained upon performing iterative based correction to the PLL corrected waveform 412. Further, iterative based correction is performed to the iterative corrected waveform until the third THD is lesser than the predefined value. Upon performing the iterative based correction, the iterative corrected waveform is considered as the corrected waveform. The THD 414 in the harmonic cancelation unit 304 comprises at least one of the first THD, the second THD, the third THD and the previous THD. The THD is determined by the THD determination module 407 and stored in the memory 403 of the harmonic cancelation unit 304. In one embodiment the first THD, the second THD and the third THD values are same. The predefined correction value 416 is value by which the iterative correction in the harmonic cancelation unit 304 is performed. In one embodiment, the determined predefined correction value depends upon at least one of the first THD, the second THD and the third THD. Further, in one embodiment, the predefined correction value may also depend upon amount of unbalance in the power grid 302. In one embodiment, dynamic correction value may be determined which depends upon the predefined correction value and is based on one or more predefined fixed values and previous predefined correction values which may be variable and is given by as in equation 1. X=A+X^'*B …………….. 1 where X is dynamic correction value; A is predefined correction value; B are predefined fixed values; and X^' is previous dynamic correction value. The predefined increment value 417 and the predefined decrement value 418 are used for performing at least one of incrementing or decrementing of the predefined correction value 416. The predefined increment value 417 and the predefined decrement value 418 may be determined by the harmonic cancelation unit 304. In one embodiment, the predefined increment value 417 and the predefined decrement value 418 are selected by a user. . In one embodiment, the predefined increment value 417 and the predefined decrement value 418 are based on the THD 414. The other data 419 may refer to such data which can be referred for harmonic cancelation in the power based device 301. In one implementation, the modules 404 may include, for example, harmonic determination module 405, PLL based correction module 406, iterative based correction module 407, THD determination module 408 and other modules 409. Upon determining that the first THD in grid current is greater than a predefined value 415, the waveform from the power grid 411 is received and a dominant harmonic with highest magnitude of plurality of harmonics is determined in the waveform 411 by the harmonic determination module 405. In one embodiment, phase of the dominant harmonic is also determined by the harmonic determination module 405. In a non-limiting embodiment of the present disclosure, the harmonic determination module 405 is implemented using a direct-quadrature (d-q) based harmonic magnitude detector. The harmonic determination module 405 may also implemented using one of a FFT system and any other associated systems. The PLL based correction module 406 in the harmonic cancelation unit 304 performs the PLL based correction to obtain PLL corrected waveform 412. The PLL based correction is carried out on the dominant harmonic with highest magnitude in the plurality of harmonics in the waveform 411 which is determined by the harmonic determination module 405. In one embodiment, the PLL based correction is achieved by performing synchronisation of internal reference associated with the power based device 301 with dominant harmonic with highest magnitude. The synchronisation eliminates computational delay in the PLL based correction module 406 and also varying nature of phase in the waveform 411 is grasped immediately. In one embodiment, the PLL based correction module 406 may be implemented with a Digital Signal Processor (DSP) eliminating high speed costly processors. However, the PLL based correction module 406 may be implemented using any other known processor. The iterative based correction module 407, upon determination that second THD in the PLL corrected waveform 416 is greater than the predefined value 415, performs iterative based correction on the PLL corrected waveform 416. The iterative based correction is performed based on percentage correction method and maintains the THD 414 in the power based device 301 within a predefined limit. The iterative based correction is performed on the plurality of harmonics other than the dominant harmonic. In one embodiment, a switch case may be implemented to determine requirement of iterative based correction to the PLL corrected waveform. The switch case is configured to check if the PLL based correction module 406 alone is able to maintain the THD 414 in the power based device 301. If the PLL based correction module 406 is unable to maintain the THD 414 in the power based device 301, the iterative based correction is performed until the THD 414 is maintained within limits. The iterative based correction is performed by an iterative based correction module 407 for a predefined correction value 416 to the PLL corrected waveform to obtain the iterative based corrected waveform. The iterative based correction is performed to plurality of harmonics other than the dominate harmonic with highest magnitude. Further, third THD is determined in the iterative based corrected waveform by the THD determination module 408. When the third THD is greater than the predefined value 415, then the iterative based correction is performed on the iterative based corrected waveform to reduce the third THD. Also, previous third THD value is also determined which is compared with the third THD value. When the third THD is greater than the previous third THD, the predefined correction value 416 is incremented by a predefined increment value 417 and when the third THD is lesser than the previous third THD, the predefined correction value 416 is decremented by a predefined decrement value 418. Further, upon one of incrementing and decrementing the predefined correction value 416, the iterative based correction is performed on the iterative based corrected waveform 413, until the third THD is lesser than the predefined value 415 by the iterative based correction module 407. The THD determination module 407 is used to determine at least one of the first THD, the second THD and the third THD in the harmonic cancelation unit 304. The THD determination module 407 may be a THD analyzer. The other modules 409 may refer to such modules which can be referred for harmonic cancelation in the power based device 301. Figure 5 illustrates a flow diagram showing steps performed by a harmonic cancelation unit in accordance with some embodiments of the present disclosure. As illustrated in Figure 5, the method comprises one or more blocks for harmonic cancelation in the power based device 301. The method may be described in the general context of computer executable instructions. Generally, computer executable instructions can include routines, programs, objects, components, data structures, procedures, modules, and functions, which perform particular functions or implement particular abstract data types. The order in which the method is described is not intended to be construed as a limitation, and any number of the described method blocks can be combined in any order to implement the method. Additionally, individual blocks may be deleted from the methods without departing from the scope of the subject matter described herein. Furthermore, the method can be implemented in any suitable hardware, software, firmware, or combination thereof. At block 501, the first THD in the grid current of the power grid 302 is determined by the THD determination module 407. At block 502, checking of condition for the first THD greater than the predefined value 415 is performed. If the first THD is greater than the predefined value 415, block 504 is performed and if the first THD lesser than the predefined value 415 block 503 is performed. At block 503, when the first THD is lesser than the predefined value 415, then the harmonic cancelation is not performed by the harmonic cancelation unit 304. At block 504, when the first THD is greater than the predefined value 415, then waveform from the power grid 302 is obtained by the harmonic cancelation unit for harmonic cancelation. At block 505, the dominant harmonic with highest magnitude in the grid voltage is determined by the harmonic determination module 405. At block 505, PLL based correction is performed to the waveform by PLL based correction module 406. At block 507, second THD in the PLL corrected waveform is determined by the THD determination module 407. At block 508, checking of condition for the second THD greater than the predefined value 415 is performed. If the second THD is greater than the predefined value 415 block 509 is performed and if the second THD is lesser than the predefined value 415 block 510 is performed.. At block 509, when the second THD is greater than the predefined value 415, then iterative based correction is performed by the iterative based correction module 408. At block 510, when the second THD is lesser than the predefined value 415, then iterative based correction is not performed. Figure 6 illustrates a flow diagram showing steps performed by an iterative based correction module in accordance with some embodiments of the present disclosure. As illustrated in Figure 6, the method comprises one or more blocks for performing an iterative based correction by an iterative based correction module 407. The method may be described in the general context of computer executable instructions. Generally, computer executable instructions can include routines, programs, objects, components, data structures, procedures, modules, and functions, which perform particular functions or implement particular abstract data types. The order in which the method is described is not intended to be construed as a limitation, and any number of the described method blocks can be combined in any order to implement the method. Additionally, individual blocks may be deleted from the methods without departing from the scope of the subject matter described herein. Furthermore, the method can be implemented in any suitable hardware, software, firmware, or combination thereof. At block 601, iterative based correction by a predefined value is performed by the iterative based correction module 408. At block 602, determination of third THD and the previous third THD in the iterative based corrected waveform is performed by the THD determination module 407. At block 603, checking of condition for the third THD greater than the predefined value 415 is performed, if the third THD greater than the predefined value 415, block 605 is performed and if the third THD greater than the predefined value 415, block 604 is performed. At block 604, iterative based correction is not performed. At block 605, checking of condition for the third THD is greater than the previous THD is performed. If the third THD is greater than the previous THD block 606 is performed and if the third THD is lesser than the previous THD block 607 is performed. At block 606, when the third THD is greater than the previous THD, the predefined correction value 416 is incremented by the predefined increment value 417 and further iterative based correction is performed to the iterative based corrected waveform by the iterative based correction module 408. At block 607, when the third THD is lesser than the previous THD, the predefined correction value 416 is decremented by the predefined decrement value 417 and further iterative based correction is performed to the iterative based corrected waveform by the iterative based correction module 408. The iterative based correction as illustrated above is performed until the third THD is lesser than the predefined value 415. Figure 7 illustrates a block diagram of an exemplary computer system for implementing some embodiments consistent with the present disclosure. Variations of computer system 701 may be used for implementing all the computing systems that may be utilized to implement the features of the present disclosure. Computer system 701 may comprise a central processing unit (“CPU” or “processor”) 703. Processor 703 may comprise at least one data processor for executing program components for executing user- or system-generated requests. The processor may include specialized processing units such as integrated system (bus) controllers, memory management control units, floating point units, graphics processing units, digital signal processing units, etc. The processor 703 may include a microprocessor, such as AMD Athlon, Duron or Opteron, ARM’s application, embedded or secure processors, IBM PowerPC, Intel’s Core, Itanium, Xeon, Celeron or other line of processors, etc. The processor 703 may be implemented using mainframe, distributed processor, multi-core, parallel, grid, or other architectures. Some embodiments may utilize embedded technologies like application-specific integrated circuits (ASICs), digital signal processors (DSPs), Field Programmable Gate Arrays (FPGAs), etc. Processor 703 may be disposed in communication with one or more input/output (I/O) devices via I/O interface 702. The I/O interface 702 may employ communication protocols/methods such as, without limitation, audio, analog, digital, monoaural, RCA, stereo, IEEE-1394, serial bus, universal serial bus (USB), infrared, PS/2, BNC, coaxial, component, composite, digital visual interface (DVI), high-definition multimedia interface (HDMI), RF antennas, S-Video, VGA, IEEE 802.n /b/g/n/x, Bluetooth, cellular (e.g., code-division multiple access (CDMA), high-speed packet access (HSPA+), global system for mobile communications (GSM), long-term evolution (LTE), WiMax, or the like), etc. Using the I/O interface 702, the computer system 701 may communicate with one or more I/O devices. For example, the input device 704 may be an antenna, keyboard, mouse, joystick, (infrared) remote control, camera, card reader, fax machine, dongle, biometric reader, microphone, touch screen, touchpad, trackball, sensor (e.g., accelerometer, light sensor, GPS, gyroscope, proximity sensor, or the like), stylus, scanner, storage device, transceiver, video device/source, visors, etc. Output device 705 may be a printer, fax machine, video display (e.g., cathode ray tube (CRT), liquid crystal display (LCD), light-emitting diode (LED), plasma, or the like), audio speaker, etc. In some embodiments, a transceiver 705 and 704 may be disposed in connection with the processor 703. The transceiver may facilitate various types of wireless transmission or reception. For example, the transceiver may include an antenna operatively connected to a transceiver chip (e.g., Texas Instruments WiLink WL1283, Broadcom BCM4750IUB8, Infineon Technologies X-Gold 618-PMB9800, or the like), providing IEEE 802.11a/b/g/n, Bluetooth, FM, global positioning system (GPS), 2G/3G HSDPA/HSUPA communications, etc. In one embodiment, the communication may be achieved by using one of Control Area Network (CAN) communication, Synchronous Peripheral Interface (SPI)/ Serial Connect Interface (SCI) communication and Modbus communication. In some embodiments, the processor 703 may be disposed in communication with a communication network 718 via a network interface 707. The network interface 707 may communicate with the communication network 718. The network interface 707 may employ connection protocols including, without limitation, direct connect, Ethernet (e.g., twisted pair 10/40/400 Base T), transmission control protocol/internet protocol (TCP/IP), token ring, IEEE 802.11a/b/g/n/x, etc. The communication network 718 may include, without limitation, a direct interconnection, local area network (LAN), wide area network (WAN), wireless network (e.g., using Wireless Application Protocol), the Internet, etc. Using the network interface 707 and the communication network 718, the computer system 701 may communicate with power based devices 719 and power grid 720. These devices may include, without limitation, personal computer(s), server(s), fax machines, printers, scanners, various mobile devices such as cellular telephones, smartphones (e.g., Apple iPhone, Blackberry, Android-based phones, etc.), tablet computers, eBook readers (Amazon Kindle, Nook, etc.), laptop computers, notebooks, gaming consoles (Microsoft Xbox, Nintendo DS, Sony PlayStation, etc.), or the like. In some embodiments, the computer system 701 may itself embody one or more of these devices. In some embodiments, the processor 703 may be disposed in communication with one or more memory devices (e.g., RAM 710, ROM 709, etc.) via a storage interface 708. The storage interface may connect to memory devices including, without limitation, memory drives, removable disc drives, etc., employing connection protocols such as serial advanced technology attachment (SATA), integrated drive electronics (IDE), IEEE-1394, universal serial bus (USB), fiber channel, small computer systems interface (SCSI), etc. The memory drives may further include a drum, magnetic disc drive, magneto-optical drive, optical drive, redundant array of independent discs (RAID), solid-state memory devices, solid-state drives, etc. The memory 711 may store a collection of program or database components, including, without limitation, an operating system 717, user interface application 716, web browser 715, mail server 714, mail client 713, user/application data 712 (e.g., any data variables or data records discussed in this disclosure), etc. The operating system 717 may facilitate resource management and operation of the computer system 701. Examples of operating systems include, without limitation, Apple Macintosh OS X, UNIX, Unix-like system distributions (e.g., Berkeley Software Distribution (BSD), FreeBSD, NetBSD, OpenBSD, etc.), Linux distributions (e.g., Red Hat, Ubuntu, Kubuntu, etc.), IBM OS/2, Microsoft Windows (XP, Vista/7/8, etc.), Apple iOS, Google Android, Blackberry OS, or the like. User interface 716 may facilitate display, execution, interaction, manipulation, or operation of program components through textual or graphical facilities. For example, user interfaces may provide computer interaction interface elements on a display system operatively connected to the computer system 701, such as cursors, icons, check boxes, menus, scrollers, windows, widgets, etc. Graphical user interfaces (GUIs) may be employed, including, without limitation, Apple Macintosh operating systems’ Aqua, IBM OS/2, Microsoft Windows (e.g., Aero, Metro, etc.), Unix X-Windows, web interface libraries (e.g., ActiveX, Java, Javascript, AJAX, HTML, Adobe Flash, etc.), or the like. In some embodiments, the computer system 701 may implement a web browser 715 stored program component. The web browser may be a hypertext viewing application, such as Microsoft Internet Explorer, Google Chrome, Mozilla Firefox, Apple Safari, etc. Secure web browsing may be provided using HTTPS (secure hypertext transport protocol), secure sockets layer (SSL), Transport Layer Security (TLS), etc. Web browsers may utilize facilities such as AJAX, DHTML, Adobe Flash, JavaScript, Java, application programming interfaces (APIs), etc. In some embodiments, the computer system 701 may implement a mail server 714 stored program component. The mail server may be an Internet mail server such as Microsoft Exchange, or the like. The mail server may utilize facilities such as ASP, ActiveX, ANSI C++/C#, Microsoft .NET, CGI scripts, Java, JavaScript, PERL, PHP, Python, WebObjects, etc. The mail server may utilize communication protocols such as internet message access protocol (IMAP), messaging application programming interface (MAPI), Microsoft Exchange, post office protocol (POP), simple mail transfer protocol (SMTP), or the like. In some embodiments, the computer system 701 may implement a mail client 713 stored program component. The mail client may be a mail viewing application, such as Apple Mail, Microsoft Entourage, Microsoft Outlook, Mozilla Thunderbird, etc. In some embodiments, computer system 701 may store user/application data 712, such as the data, variables, records, etc. as described in this disclosure. Such databases may be implemented as fault-tolerant, relational, scalable, secure databases such as Oracle or Sybase. Alternatively, such databases may be implemented using standardized data structures, such as an array, hash, linked list, struct, structured text file (e.g., XML), table, or as object-oriented databases (e.g., using ObjectStore, Poet, Zope, etc.). Such databases may be consolidated or distributed, sometimes among the various computer systems discussed above in this disclosure. It is to be understood that the structure and operation of the any computer or database component may be combined, consolidated, or distributed in any working combination. In one embodiment of the present disclosure, one of elimination or reduction of the THD is achieved with lesser computational delay. In one embodiment of the present disclosure, higher stability of the system is achieved because of using grid voltage as reference for harmonic cancelation. In one embodiment of the present disclosure, implementation of costly high speed processors is eliminated. In one embodiment of the present disclosure, problem of mismatch between calculated phase value and real time phase value of harmonic is overcome. However a person skilled in art can envisage other application in medical field in which the current disclosure can be used. Further, the instant disclosure can be readily adopted in similar application with minor modification without departing from the scope of the present disclosure. The terms "an embodiment", "embodiment", "embodiments", "the embodiment", "the embodiments", "one or more embodiments", "some embodiments", and "one embodiment" mean "one or more (but not all) embodiments of the disclosure(s)" unless expressly specified otherwise. The terms "including", "comprising", “having” and variations thereof mean "including but not limited to", unless expressly specified otherwise. The terms "a", "an" and "the" mean "one or more", unless expressly specified otherwise. When a single device or article is described herein, it will be readily apparent that more than one device/article (whether or not they cooperate) may be used in place of a single device/article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device/article may be used in place of the more than one device or article or a different number of devices/articles may be used instead of the shown number of devices or programs. The functionality and/or the features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality/features. Thus, other embodiments of the disclosure need not include the device itself. The foregoing description of various embodiments of the disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the disclosure be limited not by this detailed description, but rather by the claims appended hereto. The above specification, examples and data provide a complete description of the manufacture and use of the composition of the disclosure. Since many embodiments of the disclosure can be made without departing from the spirit and scope of the disclosure, the disclosure resides in the claims hereinafter appended. Finally, the language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the disclosure be limited not by this detailed description, but rather by any claims that issue on an application based here on. Accordingly, the disclosure of the embodiments of the disclosure is intended to be illustrative, but not limiting, of the scope of the disclosure, which is set forth in the following claims. With respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity. In addition, where features or aspects of the disclosure are described in terms of Markush groups, those skilled in the art will recognize that the disclosure is also thereby described in terms of any individual member or subgroup of members of the Markush group. While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims. Referral Numerals: Reference Number Description 101 power based device 102 power grid 103 current based control unit 104 conventional harmonic cancelation unit 301 power based device 302 power grid 303 current based control unit 304 harmonic cancelation unit 305 PWM generator 401 I/O interface 402 processor 403 memory 404 modules 405 harmonic determination module 406 PLL based correction module 407 THD determination module 408 iterative based correction module 409 other modules 410 data 411 waveform from power grid 412 PLL corrected waveform 413 iterative corrected waveform 414 THD 415 predefined value 416 predefined correction value 417 predefined increment value 418 predefined decrement value 419 other data 701 computer system 702 I/O interface 703 processor 704 input devices 705 output devices 706 transceivers 707 network interface 708 storage interface 709 ROM 710 RAM 711 memory 712 user/application data 73 mail client 714 mail server 715 web browser 716 user interface 717 operating system 718 network 719 power based device 720 power grid

Claims:We claim:
1. A harmonic cancelation unit for harmonic cancelation in power based device, comprising:
a processor; and
a memory communicatively coupled to the processor, wherein the memory stores processor-executable instructions, which, on execution, causes the processor to:
determine a dominant harmonic with highest magnitude of plurality of harmonics in waveform from power grid when first Total Harmonic Distortion (THD) in grid current of the power based device is greater than a predefined value;
perform Phased Locked Loop (PLL) based correction in the waveform to obtain PLL corrected waveform;
determine second THD in the PLL corrected waveform; and
perform iterative based correction on the plurality of harmonics other than the dominant harmonic when the second THD is greater than the predefined value to obtain iterative based corrected waveform for harmonic cancelation in the power based device.

2. The harmonic cancelation unit as claimed in claim 1, wherein the iterative based correction comprises:
determining third THD in the iterative based corrected waveform; and
performing the iterative correction to the iterative based corrected waveform until the third THD is greater than the predefined value.

3. The harmonic cancelation unit as claimed in claim 1, wherein the iterative based correction is performed for a predefined correction value.

4. The harmonic cancelation unit as claimed in claim 3, wherein the iterative based correction further comprises:
determining previous third THD in the iterative based corrected waveform;
incrementing the predefined correction value by a predefined increment value when the third THD is greater than the previous third THD; and
decrementing the predefined correction value by the predefined decrement value when the third THD is lesser than the previous third THD.

5. The harmonic cancelation unit as claimed in claim 1, wherein the waveform from the power grid is voltage waveform.

6. The harmonic cancelation unit as claimed in claim 1, wherein the PLL based correction performs synchronisation of internal reference associated with the power based device with the dominant harmonic with highest magnitude.

7. A system for harmonic cancelation in power based device, comprising:
a current based control unit to provide modulating waveform based on the grid current of the power based device;
a harmonic cancelation unit comprising:
a processor; and
a memory communicatively coupled to the processor, wherein the memory stores processor-executable instructions, which, on execution, causes the processor to:
determine a dominant harmonic with highest magnitude of plurality of harmonics in waveform from power grid when first Total Harmonic Distortion (THD) in the grid current is greater than a predefined value;
perform Phased Locked Loop (PLL) based correction in the waveform to obtain PLL corrected waveform;
determine second THD in the PLL corrected waveform; and
perform iterative based correction on the plurality of harmonics other than the dominant harmonic when the second THD is greater than the predefined value to obtain iterative based corrected waveform for harmonic cancelation in the power based device; and
a Pulse Width Modulation (PWM) generator to provide modulated waveform based on the modulating waveform and one of PLL corrected waveform and iterative based corrected waveform, wherein the modulated waveform is provided to the power based device for harmonic cancelation.

8. The system as claimed in claim 7, wherein the iterative based correction comprises: determining third THD in the iterative based corrected waveform; and
performing the iterative correction to the iterative based corrected waveform until the third THD is greater than the predefined value.

9. The harmonic cancelation unit as claimed in claim 7, wherein the iterative based correction is performed for a predefined correction value.

10. The harmonic cancelation unit as claimed in claim 9, wherein the iterative based correction further comprises:
determining previous third THD in the iterative based corrected waveform;
incrementing the predefined correction value by a predefined increment value when the third THD is greater than the previous third THD; and
decrementing the predefined correction value by the predefined decrement value when the third THD is lesser than the previous third THD.

11. A method for harmonic cancelation in power based device, comprising:
determining, by a harmonic cancelation unit, a dominant harmonic with highest magnitude of plurality of harmonics in waveform from power grid when first Total Harmonic Distortion (THD) in grid current of the power based device is greater than a predefined value;
performing, by the harmonic cancelation unit, Phased Locked Loop (PLL) based correction in the waveform to obtain PLL corrected waveform;
determining, by the harmonic cancelation unit, second THD in the PLL corrected waveform; and
performing, by the harmonic cancelation unit, iterative based correction on the plurality of harmonics other than the dominant harmonic when the second THD is greater than the predefined value to obtain iterative based corrected waveform for harmonic cancelation in the power based device.

Dated this 29th day of September, 2015
R Ramya Rao
Of K&S Partners
Agent for the Applicant

, Description:FORM 2
THE PATENTS ACT 1970
[39 OF 1970]
&
THE PATENTS RULES, 2003

COMPLETE SPECIFICATION
[See section 10 and Rule 13]

TITLE: “HARMONIC CANCELATION UNIT AND A METHOD THEREOF”

Name and Address of the Applicant:

HITACHI, LTD., 6-6, Marunouchi 1-chome, Chiyoda-ku, Tokyo, Japan.

Nationality: Japan

The following specification particularly describes the invention and the manner in which it is to be performed.
TECHNICAL FIELD
The present subject matter generally relates to harmonic cancelation. More particularly, but not exclusively, the present disclosure discloses a system and a method for harmonic cancelation in power based devices.

BACKGROUND
Figure 1 illustrates a system implementing a conventional harmonic cancelation unit.

The system as shown in Figure 1 implementing a conventional harmonic cancelation unit comprises a power based device 101, power grid 102, current based control unit 103 and a conventional harmonic cancelation unit 104. The power based device 101 may be one of converter (AC to AC and DC to DC), rectifier (AC to DC) and inverter (DC to AC). Waveform from the power based device 101 is supplied to the power grid 102 and there may be harmonics in the power waveform which is caused due to non-linear electric loads. Elimination or reduction of the harmonics is performed by implementing a conventional harmonic cancelation unit 104 along with the current based control unit 103. Grid injected current from the power based device 101 is provided to the current based control unit 103 as a reference to obtain modulating waveform. Further, the conventional harmonic cancelation unit 104 performs the required correction by obtaining the grid injected current from the power based devices 101 for reduction or elimination of the harmonics and to obtain corrected waveform. The corrected waveform is further modulated with the modulating waveform to obtain corrected grid current and supplied to the power based device 101.

Figure 2 illustrates a flow diagram showing steps performed by a conventional harmonic cancelation unit.

At block 201, grid injected current is obtained. At block 202, modulating waveform is obtained by providing grid injected current to the current based control unit 103. At block 203, harmonics in the grid injected current by Fast Fourier Transform (FFT) analysis is determined. At block 204, proportional integration correction on the determined harmonics is performed to obtain proportional integration corrected waveform. At block 205, corrected modulated waveform is obtained which is based on the modulating waveform and the proportional integration corrected waveform.

In the conventional harmonic cancelation unit 104, harmonic cancelation requires information of magnitude and phase of individual harmonic determined in waveform from the power based devices. Desired correction in the waveform is obtained based on the information. In some embodiments, the said correction is a time consuming process. Further real-time information of the magnitude and the phase of the harmonics should be obtained to eliminate harmonics. Mismatches in the real-time information obtained, due to delay in calculation, can cause adverse effect on performance of the power based devices. Also, real-time phase correction to nullify the harmonics in the power based devices is difficult.

In a highly distorted grid, magnitude and phase of harmonics will be varying in nature with respect to time and when obtained in real-time, the magnitude and phase may not be accurate. Hence, a technique to calculate magnitude and phase information of harmonics is required for harmonic correction. Further, a method to reduce the calculated time and have a desired result is required.

SUMMARY
One or more shortcomings of the prior art are overcome and additional advantages are provided through the present disclosure. Additional features and advantages are realized through the techniques of the present disclosure. Other embodiments and aspects of the disclosure are described in detail herein and are considered a part of the claimed disclosure.

Accordingly, a harmonic cancelation unit for harmonic cancelation in power based device which is disclosed in the present invention. The harmonic cancelation unit comprises a processor and a memory. The memory is communicatively coupled to the processor where the memory stores processor-executable instructions which on execution cause the processor to determine a dominant harmonic with highest magnitude of plurality of harmonics in waveform from power grid when first THD in grid current of the power based device is greater than a predefined value. Upon the determination, the processor performs PLL based correction in the waveform to obtain PLL corrected waveform and determines second THD in the PLL corrected waveform. Also, the processor performs iterative based correction on the plurality of harmonics other than the dominant harmonic when the second THD is greater than the predefined value to obtain iterative based corrected waveform for harmonic cancelation in the power based device.

Further, the present disclosure discloses a system for harmonic cancelation in power based device. The system comprises a current based control unit, harmonic cancelation unit and a Pulse Width Modulation (PWM) generator. The current based control unit provides modulating waveform based on the grid current of the power based device. The harmonic cancelation unit is configured to function as described above. The PWM generator provides modulated waveform based on the modulating waveform and one of PLL corrected waveform and iterative based corrected waveform wherein the modulated waveform is provided to the power based device for harmonic cancelation.

Further, the present disclosure discloses a method for harmonic cancelation which comprises a harmonic cancelation unit which performs determining a dominant harmonic with highest magnitude of plurality of harmonics in waveform from power grid when first Total Harmonic Distortion (THD) in grid current of the power based device is greater than a predefined value, performing Phased Locked Loop (PLL) based correction in the waveform to obtain PLL corrected waveform, determining second THD in the PLL corrected waveform and performing iterative based correction on the plurality of harmonics other than the dominant harmonic when the second THD is greater than the predefined value to obtain iterative based corrected waveform for harmonic cancelation in the power based device.

The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects and features described above, further aspects, and features will become apparent by reference to the drawings and the following detailed description.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, serve to explain the disclosed principles. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the figures to reference like features and components. Some embodiments of system and/or methods in accordance with embodiments of the present subject matter are now described, by way of example only, and with reference to the accompanying figures, in which:

Figure 1 illustrates a system implementing a conventional harmonic cancelation unit;

Figure 2 illustrates a flow diagram showing steps performed by a conventional harmonic cancelation unit;

Figure 3 illustrates an exemplary embodiment of a system implementing a harmonic cancelation unit in accordance with one embodiment of the present disclosure;

Figure 4 illustrates a detailed block diagram of an exemplary harmonic cancelation unit with various data and modules for harmonic cancelation in a power based device in accordance with some embodiments of the present disclosure;

Figure 5 illustrates a flow diagram showing steps performed by a harmonic cancelation unit in accordance with some embodiments of the present disclosure;

Figure 6 illustrates a flow diagram showing steps performed by an iterative based correction module in accordance with some embodiments of the present disclosure; and

Figure 7 illustrates a block diagram of an exemplary computer system for implementing some embodiments consistent with the present disclosure.

It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative systems embodying the principles of the present subject matter. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudo code, and the like represent various processes which may be substantially represented in computer readable medium and executed by a computer or processor, whether or not such computer or processor is explicitly shown.

DETAILED DESCRIPTION
The foregoing has broadly outlined the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific aspect disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure.

In the present document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example in the drawings and will be described in detail below. It should be understood, however that it is not intended to limit the disclosure to the particular forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternative falling within the spirit and the scope of the disclosure.

The terms “comprises”, “comprising”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by “comprises… a” does not, without more constraints, preclude the existence of other elements or additional elements in the system or apparatus.

The present disclosure relates to a harmonic cancelation unit and method for harmonic cancelation in power based device. Harmonic cancelation is performed by determining a dominant harmonic with highest magnitude of plurality of harmonics in waveform from power grid when first Total Harmonic Distortion (THD) in grid current of the power based device is greater than a predefined value. Further, Phased Locked Loop (PLL) based correction is performed in the waveform to obtain PLL corrected waveform and second THD in the PLL corrected waveform is determined. When the second THD is greater than the predefined value, iterative based correction for a predefined correction value is performed on the plurality of harmonics other than the dominant harmonic to obtain iterative based corrected waveform for harmonic cancelation in the power based device.

In the following detailed description of the embodiments of the disclosure, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure, and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the present disclosure. The following description is, therefore, not to be taken in a limiting sense.

Figure 3 illustrates an exemplary embodiment of a system implementing a harmonic cancelation unit in accordance with some embodiments of the present disclosure.

The system as shown in Figure 3 for harmonic cancelation in a power based devices comprises a power based device 301, power grid 302, current based control unit 303, a harmonic cancelation unit 304 and a PWM generator 305. The power based device 301 may include, but is not limited to, AC to AC converter, rectifier and inverter. Waveform from the power based device 301 is one of supplied to and received from the power grid 302 and there may be harmonics in the waveform which is caused due to non-linear electric loads. In one embodiment of the present disclosure, the waveform may be grid voltage waveform obtained from the power based device 301 for extraction of harmonic information and harmonic cancelation. In another embodiment, the waveform may be grid current used for extraction and harmonic cancelation.

Further, in the present disclosure, elimination or reduction of these harmonics is performed by implementing the harmonic cancelation unit 304 along with the current based control unit 303. Grid injected current from the power based device 301 is provided to the current based control unit 303 as a reference to obtain modulating waveform. Further, the harmonic cancelation unit 304 performs required correction by obtaining the grid injected current from the power based devices 301 and one of reduction and elimination of the harmonics is performed to obtain corrected waveform. The corrected waveform is further modulated with the modulating waveform by implementing the PWM generator 305 to obtain modulated waveform and supplied to the power based device 301. The modulated waveform may be one of harmonics eliminated waveform or harmonics reduced waveform.

Figure 4 illustrates a detailed block diagram of an exemplary harmonic cancelation unit with various data and modules for harmonic cancelation in a power based device in accordance with some embodiments of the present disclosure.

The harmonic cancelation unit 304 comprises of I/O interface 401, processor 402 and memory 403. In one implementation, the harmonic cancelation unit 304 may be implemented in a variety of computing systems, such as a laptop computer, a desktop computer, a Personal Computer (PC), a notebook, a smartphone, a tablet, e-book readers (e.g., Kindles and Nooks), a server, a network server, and the like.

In one embodiment, the harmonic cancelation unit 304 receives the waveform from the power grid 302 through I/O interface 401. Also, the I/O interface 401 may provide output of the harmonic cancelation unit 304 in a form of the corrected waveform. In one embodiment, the result may be provided on a display unit (not shown in Figure). Further, the I/O interface 401 is coupled with the processor 402 of the harmonic cancelation unit 304.

The memory 403 in the harmonic cancelation unit 304 is communicatively coupled to the processor 402. The memory 403 stores processor executable instructions which on execution help the harmonic cancelation unit 304 to cancel the harmonics in the power waveform. The processor 402 may comprise at least one data processor comprising modules 404 and data 410 for determining a dominant harmonic with highest magnitude of plurality of harmonics in waveform from power grid 302 when first THD in grid current of the power based device 301 is greater than a predefined value. Upon the determination, the processor 402 performs PLL based correction in the waveform to obtain PLL corrected waveform and determines second THD in the PLL corrected waveform. Also, the processor 402 performs iterative based correction on the plurality of harmonics other than the dominant harmonic when the second THD is greater than the predefined value to obtain iterative based corrected waveform for harmonic cancelation in the power based device. In one embodiment the first THD and second THD value are same.

In the illustrated Figure 4, the data 410 and the modules 404 stored in the memory 403 are described herein in detail.

In an embodiment, the data 410 in the memory 403 are processed by the one or more modules 404 of the harmonic cancelation unit 304. The modules 404 may be stored within the memory 403 as shown in Figure 4. In an example, the one or more modules 404, communicatively coupled to the processor 402, may also be present outside the memory 403 and implemented as hardware. As used herein, the term module refers to an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.

In one embodiment, the data 410 may include, for example, waveform from power grid 411, PLL corrected waveform 412, iterative corrected waveform 413, THD 414, predefined value 415, predefined correction value 416, predefined increment value 417, predefined decrement value 418 and other data 419.

The waveform from the power grid 411 is used to extract harmonic information in the power based device 301 and for harmonic cancelation. In the present disclosure, the waveform is grid voltage waveform obtained from the power grid 302. In one embodiment, the waveform may be grid current.

The PLL corrected waveform 412 is obtained upon performing PLL based correction to the waveform 411 in the harmonic cancelation unit 304. The PLL corrected waveform 412 is further corrected using iterative based correction when the second THD in the PLL based corrected waveform is greater than the predefined value. When the predefined value is lesser than the predefined value, then the iterative based correction is not required and the PLL corrected waveform is considered as the corrected waveform.

The iterative corrected waveform 413 is obtained upon performing iterative based correction to the PLL corrected waveform 412. Further, iterative based correction is performed to the iterative corrected waveform until the third THD is lesser than the predefined value. Upon performing the iterative based correction, the iterative corrected waveform is considered as the corrected waveform.

The THD 414 in the harmonic cancelation unit 304 comprises at least one of the first THD, the second THD, the third THD and the previous THD. The THD is determined by the THD determination module 407 and stored in the memory 403 of the harmonic cancelation unit 304. In one embodiment the first THD, the second THD and the third THD values are same.

The predefined correction value 416 is value by which the iterative correction in the harmonic cancelation unit 304 is performed.

In one embodiment, the determined predefined correction value depends upon at least one of the first THD, the second THD and the third THD. Further, in one embodiment, the predefined correction value may also depend upon amount of unbalance in the power grid 302. In one embodiment, dynamic correction value may be determined which depends upon the predefined correction value and is based on one or more predefined fixed values and previous predefined correction values which may be variable and is given by as in equation 1.

X=A+X^'*B …………….. 1
where X is dynamic correction value;
A is predefined correction value;
B are predefined fixed values; and
X^' is previous dynamic correction value.

The predefined increment value 417 and the predefined decrement value 418 are used for performing at least one of incrementing or decrementing of the predefined correction value 416. The predefined increment value 417 and the predefined decrement value 418 may be determined by the harmonic cancelation unit 304. In one embodiment, the predefined increment value 417 and the predefined decrement value 418 are selected by a user. . In one embodiment, the predefined increment value 417 and the predefined decrement value 418 are based on the THD 414.

The other data 419 may refer to such data which can be referred for harmonic cancelation in the power based device 301.

In one implementation, the modules 404 may include, for example, harmonic determination module 405, PLL based correction module 406, iterative based correction module 407, THD determination module 408 and other modules 409.

Upon determining that the first THD in grid current is greater than a predefined value 415, the waveform from the power grid 411 is received and a dominant harmonic with highest magnitude of plurality of harmonics is determined in the waveform 411 by the harmonic determination module 405. In one embodiment, phase of the dominant harmonic is also determined by the harmonic determination module 405. In a non-limiting embodiment of the present disclosure, the harmonic determination module 405 is implemented using a direct-quadrature (d-q) based harmonic magnitude detector. The harmonic determination module 405 may also implemented using one of a FFT system and any other associated systems.

The PLL based correction module 406 in the harmonic cancelation unit 304 performs the PLL based correction to obtain PLL corrected waveform 412. The PLL based correction is carried out on the dominant harmonic with highest magnitude in the plurality of harmonics in the waveform 411 which is determined by the harmonic determination module 405. In one embodiment, the PLL based correction is achieved by performing synchronisation of internal reference associated with the power based device 301 with dominant harmonic with highest magnitude. The synchronisation eliminates computational delay in the PLL based correction module 406 and also varying nature of phase in the waveform 411 is grasped immediately. In one embodiment, the PLL based correction module 406 may be implemented with a Digital Signal Processor (DSP) eliminating high speed costly processors. However, the PLL based correction module 406 may be implemented using any other known processor.

The iterative based correction module 407, upon determination that second THD in the PLL corrected waveform 416 is greater than the predefined value 415, performs iterative based correction on the PLL corrected waveform 416. The iterative based correction is performed based on percentage correction method and maintains the THD 414 in the power based device 301 within a predefined limit. The iterative based correction is performed on the plurality of harmonics other than the dominant harmonic. In one embodiment, a switch case may be implemented to determine requirement of iterative based correction to the PLL corrected waveform. The switch case is configured to check if the PLL based correction module 406 alone is able to maintain the THD 414 in the power based device 301. If the PLL based correction module 406 is unable to maintain the THD 414 in the power based device 301, the iterative based correction is performed until the THD 414 is maintained within limits.

The iterative based correction is performed by an iterative based correction module 407 for a predefined correction value 416 to the PLL corrected waveform to obtain the iterative based corrected waveform. The iterative based correction is performed to plurality of harmonics other than the dominate harmonic with highest magnitude. Further, third THD is determined in the iterative based corrected waveform by the THD determination module 408. When the third THD is greater than the predefined value 415, then the iterative based correction is performed on the iterative based corrected waveform to reduce the third THD. Also, previous third THD value is also determined which is compared with the third THD value. When the third THD is greater than the previous third THD, the predefined correction value 416 is incremented by a predefined increment value 417 and when the third THD is lesser than the previous third THD, the predefined correction value 416 is decremented by a predefined decrement value 418. Further, upon one of incrementing and decrementing the predefined correction value 416, the iterative based correction is performed on the iterative based corrected waveform 413, until the third THD is lesser than the predefined value 415 by the iterative based correction module 407.

The THD determination module 407 is used to determine at least one of the first THD, the second THD and the third THD in the harmonic cancelation unit 304. The THD determination module 407 may be a THD analyzer.

The other modules 409 may refer to such modules which can be referred for harmonic cancelation in the power based device 301.

Figure 5 illustrates a flow diagram showing steps performed by a harmonic cancelation unit in accordance with some embodiments of the present disclosure.

As illustrated in Figure 5, the method comprises one or more blocks for harmonic cancelation in the power based device 301. The method may be described in the general context of computer executable instructions. Generally, computer executable instructions can include routines, programs, objects, components, data structures, procedures, modules, and functions, which perform particular functions or implement particular abstract data types.

The order in which the method is described is not intended to be construed as a limitation, and any number of the described method blocks can be combined in any order to implement the method. Additionally, individual blocks may be deleted from the methods without departing from the scope of the subject matter described herein. Furthermore, the method can be implemented in any suitable hardware, software, firmware, or combination thereof.

At block 501, the first THD in the grid current of the power grid 302 is determined by the THD determination module 407.

At block 502, checking of condition for the first THD greater than the predefined value 415 is performed. If the first THD is greater than the predefined value 415, block 504 is performed and if the first THD lesser than the predefined value 415 block 503 is performed.

At block 503, when the first THD is lesser than the predefined value 415, then the harmonic cancelation is not performed by the harmonic cancelation unit 304.

At block 504, when the first THD is greater than the predefined value 415, then waveform from the power grid 302 is obtained by the harmonic cancelation unit for harmonic cancelation.

At block 505, the dominant harmonic with highest magnitude in the grid voltage is determined by the harmonic determination module 405.

At block 505, PLL based correction is performed to the waveform by PLL based correction module 406.

At block 507, second THD in the PLL corrected waveform is determined by the THD determination module 407.

At block 508, checking of condition for the second THD greater than the predefined value 415 is performed. If the second THD is greater than the predefined value 415 block 509 is performed and if the second THD is lesser than the predefined value 415 block 510 is performed..

At block 509, when the second THD is greater than the predefined value 415, then iterative based correction is performed by the iterative based correction module 408.

At block 510, when the second THD is lesser than the predefined value 415, then iterative based correction is not performed.

Figure 6 illustrates a flow diagram showing steps performed by an iterative based correction module in accordance with some embodiments of the present disclosure.

As illustrated in Figure 6, the method comprises one or more blocks for performing an iterative based correction by an iterative based correction module 407. The method may be described in the general context of computer executable instructions. Generally, computer executable instructions can include routines, programs, objects, components, data structures, procedures, modules, and functions, which perform particular functions or implement particular abstract data types.

The order in which the method is described is not intended to be construed as a limitation, and any number of the described method blocks can be combined in any order to implement the method. Additionally, individual blocks may be deleted from the methods without departing from the scope of the subject matter described herein. Furthermore, the method can be implemented in any suitable hardware, software, firmware, or combination thereof.

At block 601, iterative based correction by a predefined value is performed by the iterative based correction module 408.

At block 602, determination of third THD and the previous third THD in the iterative based corrected waveform is performed by the THD determination module 407.

At block 603, checking of condition for the third THD greater than the predefined value 415 is performed, if the third THD greater than the predefined value 415, block 605 is performed and if the third THD greater than the predefined value 415, block 604 is performed.

At block 604, iterative based correction is not performed.

At block 605, checking of condition for the third THD is greater than the previous THD is performed. If the third THD is greater than the previous THD block 606 is performed and if the third THD is lesser than the previous THD block 607 is performed.

At block 606, when the third THD is greater than the previous THD, the predefined correction value 416 is incremented by the predefined increment value 417 and further iterative based correction is performed to the iterative based corrected waveform by the iterative based correction module 408.

At block 607, when the third THD is lesser than the previous THD, the predefined correction value 416 is decremented by the predefined decrement value 417 and further iterative based correction is performed to the iterative based corrected waveform by the iterative based correction module 408.

The iterative based correction as illustrated above is performed until the third THD is lesser than the predefined value 415.

Figure 7 illustrates a block diagram of an exemplary computer system for implementing some embodiments consistent with the present disclosure.

Variations of computer system 701 may be used for implementing all the computing systems that may be utilized to implement the features of the present disclosure. Computer system 701 may comprise a central processing unit (“CPU” or “processor”) 703. Processor 703 may comprise at least one data processor for executing program components for executing user- or system-generated requests. The processor may include specialized processing units such as integrated system (bus) controllers, memory management control units, floating point units, graphics processing units, digital signal processing units, etc. The processor 703 may include a microprocessor, such as AMD Athlon, Duron or Opteron, ARM’s application, embedded or secure processors, IBM PowerPC, Intel’s Core, Itanium, Xeon, Celeron or other line of processors, etc. The processor 703 may be implemented using mainframe, distributed processor, multi-core, parallel, grid, or other architectures. Some embodiments may utilize embedded technologies like application-specific integrated circuits (ASICs), digital signal processors (DSPs), Field Programmable Gate Arrays (FPGAs), etc.

Processor 703 may be disposed in communication with one or more input/output (I/O) devices via I/O interface 702. The I/O interface 702 may employ communication protocols/methods such as, without limitation, audio, analog, digital, monoaural, RCA, stereo, IEEE-1394, serial bus, universal serial bus (USB), infrared, PS/2, BNC, coaxial, component, composite, digital visual interface (DVI), high-definition multimedia interface (HDMI), RF antennas, S-Video, VGA, IEEE 802.n /b/g/n/x, Bluetooth, cellular (e.g., code-division multiple access (CDMA), high-speed packet access (HSPA+), global system for mobile communications (GSM), long-term evolution (LTE), WiMax, or the like), etc.

Using the I/O interface 702, the computer system 701 may communicate with one or more I/O devices. For example, the input device 704 may be an antenna, keyboard, mouse, joystick, (infrared) remote control, camera, card reader, fax machine, dongle, biometric reader, microphone, touch screen, touchpad, trackball, sensor (e.g., accelerometer, light sensor, GPS, gyroscope, proximity sensor, or the like), stylus, scanner, storage device, transceiver, video device/source, visors, etc. Output device 705 may be a printer, fax machine, video display (e.g., cathode ray tube (CRT), liquid crystal display (LCD), light-emitting diode (LED), plasma, or the like), audio speaker, etc. In some embodiments, a transceiver 705 and 704 may be disposed in connection with the processor 703. The transceiver may facilitate various types of wireless transmission or reception. For example, the transceiver may include an antenna operatively connected to a transceiver chip (e.g., Texas Instruments WiLink WL1283, Broadcom BCM4750IUB8, Infineon Technologies X-Gold 618-PMB9800, or the like), providing IEEE 802.11a/b/g/n, Bluetooth, FM, global positioning system (GPS), 2G/3G HSDPA/HSUPA communications, etc. In one embodiment, the communication may be achieved by using one of Control Area Network (CAN) communication, Synchronous Peripheral Interface (SPI)/ Serial Connect Interface (SCI) communication and Modbus communication.

In some embodiments, the processor 703 may be disposed in communication with a communication network 718 via a network interface 707. The network interface 707 may communicate with the communication network 718. The network interface 707 may employ connection protocols including, without limitation, direct connect, Ethernet (e.g., twisted pair 10/40/400 Base T), transmission control protocol/internet protocol (TCP/IP), token ring, IEEE 802.11a/b/g/n/x, etc. The communication network 718 may include, without limitation, a direct interconnection, local area network (LAN), wide area network (WAN), wireless network (e.g., using Wireless Application Protocol), the Internet, etc. Using the network interface 707 and the communication network 718, the computer system 701 may communicate with power based devices 719 and power grid 720. These devices may include, without limitation, personal computer(s), server(s), fax machines, printers, scanners, various mobile devices such as cellular telephones, smartphones (e.g., Apple iPhone, Blackberry, Android-based phones, etc.), tablet computers, eBook readers (Amazon Kindle, Nook, etc.), laptop computers, notebooks, gaming consoles (Microsoft Xbox, Nintendo DS, Sony PlayStation, etc.), or the like. In some embodiments, the computer system 701 may itself embody one or more of these devices.

In some embodiments, the processor 703 may be disposed in communication with one or more memory devices (e.g., RAM 710, ROM 709, etc.) via a storage interface 708. The storage interface may connect to memory devices including, without limitation, memory drives, removable disc drives, etc., employing connection protocols such as serial advanced technology attachment (SATA), integrated drive electronics (IDE), IEEE-1394, universal serial bus (USB), fiber channel, small computer systems interface (SCSI), etc. The memory drives may further include a drum, magnetic disc drive, magneto-optical drive, optical drive, redundant array of independent discs (RAID), solid-state memory devices, solid-state drives, etc.

The memory 711 may store a collection of program or database components, including, without limitation, an operating system 717, user interface application 716, web browser 715, mail server 714, mail client 713, user/application data 712 (e.g., any data variables or data records discussed in this disclosure), etc. The operating system 717 may facilitate resource management and operation of the computer system 701. Examples of operating systems include, without limitation, Apple Macintosh OS X, UNIX, Unix-like system distributions (e.g., Berkeley Software Distribution (BSD), FreeBSD, NetBSD, OpenBSD, etc.), Linux distributions (e.g., Red Hat, Ubuntu, Kubuntu, etc.), IBM OS/2, Microsoft Windows (XP, Vista/7/8, etc.), Apple iOS, Google Android, Blackberry OS, or the like. User interface 716 may facilitate display, execution, interaction, manipulation, or operation of program components through textual or graphical facilities. For example, user interfaces may provide computer interaction interface elements on a display system operatively connected to the computer system 701, such as cursors, icons, check boxes, menus, scrollers, windows, widgets, etc. Graphical user interfaces (GUIs) may be employed, including, without limitation, Apple Macintosh operating systems’ Aqua, IBM OS/2, Microsoft Windows (e.g., Aero, Metro, etc.), Unix X-Windows, web interface libraries (e.g., ActiveX, Java, Javascript, AJAX, HTML, Adobe Flash, etc.), or the like.

In some embodiments, the computer system 701 may implement a web browser 715 stored program component. The web browser may be a hypertext viewing application, such as Microsoft Internet Explorer, Google Chrome, Mozilla Firefox, Apple Safari, etc. Secure web browsing may be provided using HTTPS (secure hypertext transport protocol), secure sockets layer (SSL), Transport Layer Security (TLS), etc. Web browsers may utilize facilities such as AJAX, DHTML, Adobe Flash, JavaScript, Java, application programming interfaces (APIs), etc. In some embodiments, the computer system 701 may implement a mail server 714 stored program component. The mail server may be an Internet mail server such as Microsoft Exchange, or the like. The mail server may utilize facilities such as ASP, ActiveX, ANSI C++/C#, Microsoft .NET, CGI scripts, Java, JavaScript, PERL, PHP, Python, WebObjects, etc. The mail server may utilize communication protocols such as internet message access protocol (IMAP), messaging application programming interface (MAPI), Microsoft Exchange, post office protocol (POP), simple mail transfer protocol (SMTP), or the like. In some embodiments, the computer system 701 may implement a mail client 713 stored program component. The mail client may be a mail viewing application, such as Apple Mail, Microsoft Entourage, Microsoft Outlook, Mozilla Thunderbird, etc.

In some embodiments, computer system 701 may store user/application data 712, such as the data, variables, records, etc. as described in this disclosure. Such databases may be implemented as fault-tolerant, relational, scalable, secure databases such as Oracle or Sybase. Alternatively, such databases may be implemented using standardized data structures, such as an array, hash, linked list, struct, structured text file (e.g., XML), table, or as object-oriented databases (e.g., using ObjectStore, Poet, Zope, etc.). Such databases may be consolidated or distributed, sometimes among the various computer systems discussed above in this disclosure. It is to be understood that the structure and operation of the any computer or database component may be combined, consolidated, or distributed in any working combination.

In one embodiment of the present disclosure, one of elimination or reduction of the THD is achieved with lesser computational delay.

In one embodiment of the present disclosure, higher stability of the system is achieved because of using grid voltage as reference for harmonic cancelation.

In one embodiment of the present disclosure, implementation of costly high speed processors is eliminated.

In one embodiment of the present disclosure, problem of mismatch between calculated phase value and real time phase value of harmonic is overcome.

However a person skilled in art can envisage other application in medical field in which the current disclosure can be used. Further, the instant disclosure can be readily adopted in similar application with minor modification without departing from the scope of the present disclosure.

The terms "an embodiment", "embodiment", "embodiments", "the embodiment", "the embodiments", "one or more embodiments", "some embodiments", and "one embodiment" mean "one or more (but not all) embodiments of the disclosure(s)" unless expressly specified otherwise.

The terms "including", "comprising", “having” and variations thereof mean "including but not limited to", unless expressly specified otherwise.

The terms "a", "an" and "the" mean "one or more", unless expressly specified otherwise.

When a single device or article is described herein, it will be readily apparent that more than one device/article (whether or not they cooperate) may be used in place of a single device/article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device/article may be used in place of the more than one device or article or a different number of devices/articles may be used instead of the shown number of devices or programs. The functionality and/or the features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality/features. Thus, other embodiments of the disclosure need not include the device itself.

The foregoing description of various embodiments of the disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the disclosure be limited not by this detailed description, but rather by the claims appended hereto. The above specification, examples and data provide a complete description of the manufacture and use of the composition of the disclosure. Since many embodiments of the disclosure can be made without departing from the spirit and scope of the disclosure, the disclosure resides in the claims hereinafter appended.

Finally, the language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the disclosure be limited not by this detailed description, but rather by any claims that issue on an application based here on. Accordingly, the disclosure of the embodiments of the disclosure is intended to be illustrative, but not limiting, of the scope of the disclosure, which is set forth in the following claims.

With respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity.

In addition, where features or aspects of the disclosure are described in terms of Markush groups, those skilled in the art will recognize that the disclosure is also thereby described in terms of any individual member or subgroup of members of the Markush group.

While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.

Referral Numerals:

Reference Number Description
101 power based device
102 power grid
103 current based control unit
104 conventional harmonic cancelation unit
301 power based device
302 power grid
303 current based control unit
304 harmonic cancelation unit
305 PWM generator
401 I/O interface
402 processor
403 memory
404 modules
405 harmonic determination module
406 PLL based correction module
407 THD determination module
408 iterative based correction module
409 other modules
410 data
411 waveform from power grid
412 PLL corrected waveform
413 iterative corrected waveform
414 THD
415 predefined value
416 predefined correction value
417 predefined increment value
418 predefined decrement value
419 other data
701 computer system
702 I/O interface
703 processor
704 input devices
705 output devices
706 transceivers
707 network interface
708 storage interface
709 ROM
710 RAM
711 memory
712 user/application data
73 mail client
714 mail server
715 web browser
716 user interface
717 operating system
718 network
719 power based device
720 power grid