DESC:TECHNICAL FIELD
[0001] The present disclosure generally relates to a high electron mobility transistor (HEMT) device. In particular, the present disclosure relates to an HEMT device with a limiting layer including an oxide material.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] In device fabrication of high electron mobility transistors (HEMTs), it may be often necessary to retain AlGaN (or p-GaN) layer at an appropriate position, particularly, for normally off HEMTs with a p-GaN gate. A p-GaN cap layer is grown on an AlGaN barrier layer to deplete the two-dimensional electron gas (2DEG) in the GaN channel layer beneath the AlGaN barrier. In order to prepare a p-GaN gate and restore the 2DEG in the access region, the p-GaN cap layer in the access region may be required to be removed completely and precisely.
[0004] In some cases, a combination of plasma oxidation and wet etching with hydrochloric acid (HCl) have been employed to minimize ion damage to underlying layers. Other earlier works have also used chemistries including BCl3/Cl2, BCl3/SF6, Cl2/Ar/O2, Cl2/N2, N2/Cl2/O2, and Cl2/Ar. However, these recipes have high etching rates due to uncontrollable and unstable plasma. Further, by adding inductively coupled plasma (ICP) in the recipe, AlGaN becomes more prone to surface damage, which can degrade 2DEG density and may also cause reliability issues.
[0005] There is, therefore, a requirement in the art for a technique or method to precisely and selectively remove the p-GaN cap layer in normally off HEMTs with a p-GaN gate.

OBJECTS OF INVENTION
[0006] An object of the present invention is to provide a high electron mobility transistor (HEMT) device configured with a limiting layer.
[0007] Another object of the present invention is to provide an HEMT device where the limiting layer may be obtained due to a self-terminating etching process.
[0008] Another object of the present invention is to provide an HEMT device with improved dynamic performance.

SUMMARY
[0009] The present disclosure generally relates to a high electron mobility transistor (HEMT) device. In particular, the present disclosure relates to an HEMT device with a limiting layer including an oxide material.
[0010] In an aspect, the present disclosure provides a high-electron mobility transistor (HEMT) device. The HEMT device includes a substrate. The HEMT device further includes a first layer including a first material and disposed on the substrate. The HEMT device further includes a second layer including a second material and disposed on the first layer. The HEMT device further includes a limiting layer disposed on at least a first portion of the second layer. The limiting layer is formed by selectively removing a portion of a cap layer predisposed on the second layer. the cap layer includes a third material. The limiting layer includes a fourth material formed based on the third material.
[0011] In some embodiments, the limiting layer is formed by pre-disposing, on the second layer, the cap layer. The limiting layer is further formed by selectively removing a portion of the cap layer corresponding to the at least first portion of the second layer. The limiting layer is formed proximate the second layer.
[0012] In some embodiments, the portion of the cap layer is selectively removed using a chemical etching process including oxygen and chlorine-based plasma.
[0013] In some embodiments, a portion of the cap layer corresponding to a second portion of the second layer is not removed to form a third layer of the HEMT device. The third layer includes the third material and is disposed on the second layer.
[0014] In some embodiments, the HEMT device further includes a source and a drain. The source and the drain are disposed on the first layer, and separated from each other by a predefined first distance, defining a channel therebetween. The second, and limiting layers are further disposed in the channel.
[0015] In some embodiments, the HEMT device further includes a gate disposed on the second layer.
[0016] In some embodiments, the first material includes gallium nitride (GaN). The second material includes aluminum gallium nitride (AlGaN). The third material includes GaN.
[0017] In some embodiments, the fourth material includes a complex oxide of aluminum and gallium.
[0018] In some embodiments, the HEMT device further includes any one or a combination of a passivation layer, a field plate, a spacer, and a drain deep field plate.

BRIEF DESCRIPTION OF DRAWINGS
[0019] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0020] FIG. 1 illustrates a schematic representation of an architecture of a high electron mobility transistor (HEMT) device, according to an embodiment of the present disclosure;
[0021] FIG. 2 illustrates a schematic graphical representation of an etching process to fabricate a limiting layer of the HEMT device, according to an embodiment of the present disclosure;
[0022] FIG. 3A illustrates a schematic representation of an architecture of an HEMT device, according to another embodiment of the present disclosure;
[0023] FIG. 3B illustrates a schematic representation of an architecture of an HEMT device, according to another embodiment of the present disclosure;
[0024] FIG. 3C illustrates a schematic representation of an architecture of an HEMT device, according to another embodiment of the present disclosure;
[0025] FIG. 3D illustrates a schematic representation of an architecture of an HEMT device, according to another embodiment of the present disclosure;
[0026] FIG. 4A illustrates a schematic representation of an architecture of an HEMT device, according to another embodiment of the present disclosure;
[0027] FIG. 4B illustrates a schematic representation of an architecture of an HEMT device, according to another embodiment of the present disclosure;
[0028] FIG. 4C illustrates a schematic representation of an architecture of an HEMT device, according to another embodiment of the present disclosure;
[0029] FIG. 4D illustrates a schematic representation of an architecture of an HEMT device, according to another embodiment of the present disclosure;
[0030] FIG. 5A illustrates an exemplary plot depicting a variation in etch depth of the p-GaN with etch depth;
[0031] FIG. 5B illustrates an exemplary plot depicting variation of channel sheet resistance as a function of residual p-GaN;
[0032] FIGs. 6A – 6D illustrate exemplary x-ray photoelectron spectroscopy (XPS) data plots depicting a sample of the device without the limiting layer;
[0033] FIGs. 7A – 7D illustrate exemplary XPS data plots depicting a sample of the device with the limiting layer;
[0034] FIGs. 8A – 8D illustrate exemplary XPS data plots depicting a direct exposure of AlGaN to plasma, showing formation of Al-Ga-O in the limiting layer;
[0035] FIG. 9A illustrates an exemplary electroluminescence (EL) image overlapped with device in case of a sample of the device without the limiting layer;
[0036] FIG. 9B illustrates an exemplary EL image overlapped with device in case of a sample of the device with the limiting layer;
[0037] FIG. 9C illustrates an exemplary plot depicting electroluminescence/electric field intensities of the HEMT device; and
[0038] FIGs. 10A and 10B illustrate exemplary plots depicting dynamic RON degradation as a function of pulse width.

DETAILED DESCRIPTION
[0039] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such details as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0040] In HEMTs with a p-GaN gate, in order to prepare a p-GaN gate and restore the 2DEG in the access region, the p-GaN cap layer in the access region may be required to be removed completely and precisely. In other words, any etching process used may be required to stop smoothly at the surface of the AlGaN barrier layer. Further, it may be advantageous, for the purposes of scaling the manufacturing of such HEMTs if the etching process is a reproducible and easily manufacturable.
[0041] While there are multiple chemistries, wet and dry, that will readily etch GaN, dry chemistries may be employed to quickly develop a highly controlled selective anisotropic etch for p-GaN over thin AlGaN. The present disclosure provides an optimized and controllable p-GaN etch recipe with AlGaN acting as complete stoppant layer, using oxygen (O2) plasma for bond making (GaOx) and a chlorine (Cl2) plasma for bond breaking and forming volatile GaClx radicals during reactive ion etching (RIE). AlOx formation as plasma reaches AlGaN surface is found to passivate AlGaN surface and redistribute electric field uniformly in the channel region. This advantageous passivation can play important role in minimising reliability issues associated with filed peaking in the channel region under semi-ON and OFF state stress conditions.
[0042] In an aspect, the present disclosure provides a high-electron mobility transistor (HEMT) device. The HEMT device includes a substrate. The HEMT device further includes a first layer including a first material and disposed on the substrate. The HEMT device further includes a second layer including a second material and disposed on the first layer. The HEMT device further includes a limiting layer disposed on at least a first portion of the second layer. The limiting layer is formed by selectively removing a portion of a cap layer predisposed on the second layer. The cap layer includes a third material. The limiting layer includes a fourth material formed based on the third material.
[0043] In some embodiments, the limiting layer is formed by pre-disposing, on the second layer, the cap layer. The limiting layer is further formed by selectively removing a portion of the cap layer corresponding to the at least first portion of the second layer. The limiting layer is formed proximate the second layer.
[0044] In some embodiments, the portion of the cap layer is selectively removed using a chemical etching process including oxygen and chlorine-based plasma.
[0045] In some embodiments, a portion of the cap layer corresponding to a second portion of the second layer is not removed to form a third layer of the HEMT device. The third layer includes the third material and is disposed on the second layer.
[0046] In some embodiments, the HEMT device further includes a source and a drain. The source and the drain are disposed on the first layer, and separated from each other by a predefined first distance, defining a channel therebetween. The second, and limiting layers are further disposed in the channel.
[0047] In some embodiments, the HEMT device further includes a gate disposed on the second layer.
[0048] In some embodiments, the first material includes gallium nitride (GaN). The second material includes aluminum gallium nitride (AlGaN). The third material includes GaN.
[0049] In some embodiments, the fourth material includes a complex oxide of aluminum and gallium.
[0050] In some embodiments, the HEMT device further includes any one or a combination of a passivation layer, a field plate, a spacer, and a drain deep field plate.
[0051] FIG. 1 illustrates a schematic representation of an architecture of a high electron mobility transistor (HEMT) device 100, according to an embodiment of the present disclosure. The HEMT device 100 may interchangeably be referred to as “the device 100”. The device 100 includes a substrate 102 including silicon. The device 100 further includes a first layer 104 including a first material. In some embodiments the first material includes gallium nitride (GaN). The device 100 further includes a second layer 106 including a second material. The second layer 106 is disposed on the first layer 104. In some embodiments, the second material includes aluminum gallium nitride (AlGaN). In some embodiments, the third material include GaN. The device 100 further includes a limiting layer 110 disposed on at least a first portion of the second layer 106. The limiting layer 110 is formed by selectively removing a portion of a cap layer 112 predisposed on the second layer 106. The cap layer 112 includes a third material. In some embodiments, the third material include GaN. In some embodiments, the third material may include a p-doped GaN. The limiting layer 110 includes a fourth material formed based on the third material. In some embodiments, the fourth material includes a complex oxide of aluminum and gallium.
[0052] In some embodiments, the device 100 further includes a source 114 and a drain 116. The source 114 and the drain 116 are disposed on the first layer 104. The source 114 and drain 116 are further separated from each other by a predefined first distance d1, defining a channel therebetween. In some embodiments, the second, third and limiting layers 106, 108, 110 are further disposed in the channel. In some embodiments, the device 100 further includes a gate 120 disposed on the third layer 108. The gate 120 may include materials selected from any one or a combination of titanium, titanium nitride, aluminum, gold, scandium and tungsten.
[0053] In some embodiments, AlGaN/GaN heterostructure is grown on Si using a metalorganic chemical vapour deposition (MOCVD), with 80+/-8nm of p-GaN cap. AlGaN barrier layer thickness in the epitaxial stack is about 14 nanometres (nm).
[0054] FIG. 2 illustrates a schematic graphical representation of an etching process to fabricate the limiting layer 110 of the device 100, according to an embodiment of the present disclosure. As shown in step 202, the device 100 is initially provided with a cap layer 112 disposed on top of the second layer 106. The cap layer 112 includes GaN. Referring to step 204, a portion of the cap layer 112 is selectively removed. The portion removed corresponds to the second portion on the second layer 106. The remaining portion corresponds to the first portion on the second layer 106. The remaining portion forms the third layer 108 including the p-doped GaN. The material removal process at the second portion stops proximate the second layer 106 to provide the limiting layer 110.
[0055] In some embodiments, the p-GaN layer is selectively etched using an O2/BCl3 etch recipe in which the O2 flow regulates the etch rate. Further, the recipe is such that, as it reaches the AlGaN layer after etching the p-GaN, the AlGaN layer is passivated due to the formation of AlOx, which limits further etching of the AlGaN layer. As a result, the proposed method is highly selective and self-terminating once it reaches the AlGaN surface.
[0056] To simplify the number of etching experiments possible, known recipes for etching, namely, (O2/BCl3) and (Cl2/BCl3) were used initially. O2/BCl3 recipe is an atomic level etching cyclic etching technique usually preferred for etching thin barrier GaN/AlGaN layers. However, for long run etch processes BCl3 plasma may lead to the reduction of Cl radical density, which may decrease the DC bias and reactive etch rate. Furthermore, BCl3 adds a physical component to the etching process, which may damage the AlGaN surface and result in surface related reliability challenges, such as Dynamic Ron, etc.
[0057] On the other hand, Cl2/BCl3 has a higher etch rate (~16nm/min) compared to O2/BCl3 and is used for etching AlGaN. Therefore, it may not be a suitable choice for p-GaN etching. Thus, Cl2 plasma was used for etching GaN, while O2 plasma was used as a limiting agent to form AlGaOx complexes, which, with proper selection of Cl2 flow rate, RIE power, and chamber pressure, acts as a suitable stopping layer to the developed dry etching chemistry. Exemplary parameters used for dry etching of the p-GaN are given in Table – 1 below.
Parameter Range
ICP (W) 0
RIE (W) 15
Cl2 (sccm) 10
O2 (sccm) 1-5
N2 (sccm) 0-10
Pressure (mTorr) 10
Table – 1: Process parameters for dry etching of p-GaN
[0058] In some embodiments, the highly selective GaN anisotropic etch was investigated using an Oxford ICP 380 RIE-Cl dry etching system. AFM was used to check etch rates and surface morphologies. 2DEG sheet resistance measurement approach was used to characterise any damage to the AlGaN surface during p-GaN etching process. Sheet resistance was measured by fabricating TLM structures post p-GaN etching step, with standard Ti/Al/Ni/Au stack at 800 ?C for 30s annealing conditions in N2 ambient.
[0059] FIGs. 3A – 3D illustrate schematic representations of an architecture of HEMT devices 300, 320, 340, 360 according to different embodiment of the present disclosure. The devices 300, 320, 340, 360 may be substantially similar to the device 100 of FIG. 1. Common components between the devices 300, 320, 340, 360 and 100 may be referenced using the same reference numerals.
[0060] Referring to FIGs. 1 and 3A, the device 300 may further include a passivation layer 302 disposed on the limiting layer 110, and the gate 120. The passivation layer 302 may include an oxide of aluminum. The device 300 may further include a field plate 304. The field plate 304 may be connected the gate 120.
[0061] Referring now to FIGs. 1, 3A and 3B, the device 320 may include a recessed gate 120. The recessed gate 120 may extend into the second layer 106.
[0062] Referring now to FIGs. 1 and 3A-3C, the device 340 may include a gate 120 that is disposed on top of the limiting layer 110. Schottky gated HEMTs suffer from gate leakage issues due to surface states induced by plasma. The surface states also lead to gate instability issues such as Vth shifts. To suppress these issues, the limiting layer 110 may be present under the gate 120.
[0063] Referring now to FIGs. 1 and 3A-3D, the device 360 includes a recessed gate 120 with the limiting layer 110 further being formed under the recessed gate 120.
[0064] FIGs. 4A – 4D illustrate schematic representations of an architecture of HEMT devices 400, 420, 440, 460 according to different embodiment of the present disclosure. The devices 400, 420, 440, 460 may be substantially similar to the device 100 of FIG. 1. Common components between the devices 400, 420, 440, 460 and 100 may be referenced using the same reference numerals.
[0065] Referring to FIGs. 1 and 4A, in the device 400, a portion of the cap layer 112 corresponding to a first portion of the second layer 106 may not be removed. The portion of the cap layer 112 not removed may form a third layer 108. The gate 120 may be disposed on top of the third layer 108.
[0066] Referring to FIGs. 1, 4A and 4B, the device 420 may further include a passivation layer 402 disposed on the limiting layer 110, and the gate 120. The passivation layer 402 may include an oxide of aluminum. The device 420 may further include a field plate 404. The field plate 404 may be connected the source 114 or the gate 120.
[0067] Referring to FIGs. 1 and 4A-4C, the device 440 may include a spacer layer 442. The spacer layer 442 may be disposed proximate the third layer 108 and the gate 120, above the second layer 106.
[0068] Referring to FIGs. 1 and 4A-4D, the device 460 may further include a drain field plate 462.
[0069] FIG. 5A illustrates an exemplary plot 500 depicting a variation in etch depth of the p-GaN with etch. Specifically, the plot 500 depicts variation in etch depth with O2 having a flow rate of 1 sccm. The p-GaN etch rate initially increases with etch time, and then saturates as at a height of about 80 nm. This may demonstrate a stopping capability of the AlGaN to limit further progress of the O2/Cl2 plasma. This stopping capability may be attributed to formation of Al-Ga-O complexes at the AlGaN surface with higher binding energy thereby giving the recipe self-termination capability.
[0070] FIG. 5B illustrates an exemplary plot 550 depicting variation of sheet resistance as a function of residual p-GaN. As can be seen from the plot 550, there is an improvement in RON in the self-limiting instance.
[0071] FIGs. 6A – 6D illustrate exemplary x-ray photoelectron spectroscopy (XPS) data plots 600, 620, 640, 660 depicting a case without Al-Ga-O layer. The spectra may be calibrated using C 1s peak of about 284.8 eV. No Al 2p peaks are seen, thus suggesting that p-GaN may be without Al-Ga-O. Further, the sample shows a presence of GaOx on the surface, as indicated by presence of Ga 3d and O 1s spectra. FIG. 9A shows an exemplary image 900 depicting a device without the limiting layer 110.
[0072] FIGs. 7A – 7D illustrate exemplary XPS data plots 700, 720, 740, 760 depicting formation of the limiting layer. The presence of Al 2p peak may suggest that the p-GaN is completely etched. Further, deconvolution of O 1s reveals a presence of Al-O bonds in addition to Ga-O bonds, this implies that Al-Ga-O may be formed on the surface of the AlGaN layer. On reaching the AlGaN layer, O shows a higher affinity to Al that to Ga, as a result of which a higher proportion of AlOx may be formed compared to GaOx. Furthermore, the Al-O bonds may be stronger than the Ga-O bonds, as can be seen from the values of binding energy of O-Al (about 531.6 eV) and O-Ga (about 531 eV). From the relative intensities of Al-O and Ga-O, it may be estimated that the oxide complex of Al and Ga may be Al62.4Ga37.6O. FIG. 7B shows an exemplary image 920 depicting a device with the limiting layer 110.
[0073] FIGs. 8A – 8D illustrate exemplary XPS data plots 800, 820, 840, 860 depicting an exposure of AlGaN to plasma. The plots may indicate that the O2/Cl2 chemistry used for etching may be selective with respect to AlGaN layer due to the formation of AlOx on the surface. In this instance, the oxide complex of Al and Ga may be Al0.6Ga0.4O.
[0074] FIG. 9C illustrates an exemplary plot 940 depicting electroluminescence (EL)/Electric field intensities for the devices without and with the limiting layer 110 (refer FIGs. 9A and 9B, respectively). As can be observed, absence of Al-Ga-O (i.e., the limiting layer 110) on AlGaN surface leads to field peaking at around drain edge and in the gate source access region. As a result of these stress conditions, buffer leakage was found to increase. Field peaking may cause serious reliability concerns in terms of dynamic RON degradation and early breakdown. In contrast, in the case of the device with limiting Al-Ga-O, a uniform field redistribution is seen in the drain-gate access region. As a result, there was a minimal change in substrate leakage current. AlOx complexes on AlGaN surface can therefore be advantageous in minimising GaN HEMT reliability concerns associated with field peaking in the semi-ON and OFF-state stress conditions.
[0075] FIGs. 10A and 10B illustrate exemplary plots 1000, 1050 depicting dynamic Ron degradation as a function of pulse width for respectively, on samples and without and with Al-Ga-O 110. As can be observed, in the case of the sample with Al-Ga-O, an improvement in dynamic performance is seen. This improvement is due to the advantageous AlOx passivation of the AlGaN surface.
[0076] Thus, the present disclosure provides an O2/Cl2 plasma-based p-GaN etch recipe, with stopping capability at AlGaN surface. O2 flow may be used to control the etch rate and also increase self-termination capability at AlGaN surface. The use of the recipe improves surface morphology of the etched surface. The etched surface may show a decrease in average surface roughness from about 1.046 nm to about 0.773 nm. From TLM based electrical data, the AlGaN surface is free from plasma induced damage, with an achieved minimum sheet resistance of 598 ohm/sq and SD of 70.9. Uniform field redistribution is also shown with advantageous AlOx formation on AlGaN surface, which can minimise reliability challenges like dynamic Ron and current collapse.
[0077] It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprise” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refer to at least one of something selected from the group consisting of A, B, C ….and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc. The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims.
[0078] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions, or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF INVENTION
[0079] The present invention provides a high electron mobility transistor (HEMT) device configured with a limiting layer.
[0080] The present invention provides an HEMT device where the limiting layer may be obtained due to a self-terminating etching process.
[0081] The present invention provides an HEMT device with improved dynamic performance.
,CLAIMS:1. A high-electron mobility transistor (HEMT) device (100) comprising:
a substrate (102);
a first layer (104) comprising a first material, and disposed on the substrate (102);
a second layer (106) comprising a second material, and disposed on the first layer (104); and
a limiting layer (110) disposed on at least a first portion of the second layer (106),
wherein,
the limiting layer (110) is formed by selectively removing a portion of a cap layer (112) predisposed on the second layer (106),
the cap layer (112) comprises a third material, and
the limiting layer (110) comprises a fourth material formed based on the third material.
2. The HEMT device (100) as claimed in claim 1, wherein the limiting layer (110) is formed by:
pre-disposing, on the second layer (106), the cap layer (112); and
selectively removing a portion of the cap layer (112) corresponding to the at least the first portion of the second layer (106),
wherein, the limiting layer (110) is formed proximate the second layer (106).
3. The HEMT device (100) as claimed in claim 2, wherein the portion of the cap layer (112) is selectively removed using a chemical etching process comprising an oxygen- and chlorine-based plasma.
4. The HEMT device (100) as claimed in claim 1, wherein a portion of the cap layer (112) corresponding to a second portion of the second layer (106) is not removed to form a third layer (108) of the HEMT device (100), and wherein the third layer (108) comprises the third material and is disposed on the second layer (106).
5. The HEMT device (100) as claimed in claim 1, wherein the HEMT device (100) further comprises a source (114) and a drain (116), the source (114) and the drain (116) disposed on the first layer (104) and separated from each other by a predefined first distance (d1), defining a channel therebetween, and wherein the second, and limiting layers (106, 110) are further disposed in the channel.

6. The HEMT device (100) as claimed in claim 1, wherein the HEMT device (100) further comprises a gate (120) disposed on the second layer (106).
7. The HEMT device (100) as claimed in claim 1, wherein the first material comprises gallium nitride (GaN), wherein the second material comprises aluminum gallium nitride (AlGaN), and wherein the third material comprises GaN.
8. The HEMT device (100) as claimed in claim 1, wherein the fourth material comprises a complex oxide of aluminum and gallium.
9. The HEMT device (100) as claimed in claim 1, wherein the HEMT device (100) further comprises any one or a combination of a passivation layer (302), a field plate (304), a spacer (322) and a drain field plate (342).