DESC:TECHNICAL FIELD
[0001] The present disclosure relates generally to transistor design. In particular, the present disclosure relates to design of high electron mobility transistor for enhancing performance and linearity.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] Area of high speed electronics has been rapidly growing due to increased demand of devices that are capable of operating at mm-wave frequencies. There are numerous applications such as in 5G devices, radar and automobiles, where the device speed is of critical importance. In high speed power switches, the additional requirement of high breakdown voltage adds complexity to device design.
[0004] HEMT being a wide band gap semiconductor device, offers high breakdown voltage and GaN HEMT has started to establish itself as a potential high power robust device in the semiconductor field. Besides high band gap (3.4eV) and large critical electric field (3.3 MV/cm), one of the imperative advantage of GaN material is high saturation velocity of 2.5x107 cm/s. It allows to design RF HEMT devices that perform better than the silicon counter arts.
[0005] However, saturation velocity in GaN peaks around electric field of 150kV/cm but under normal operating conditions, the electric field in the channel is significantly higher than this value resulting in under-performance. Another factor which limits the RF performance of the HEMT is parastitic resistances and capacitance. It largely affects the unity gain frequency ft of the device. Due to the above reasons, traditional RF GaN HEMTs show huge discrepancy from the theoretical predicted limit. Also, majority of available conventional RF devices have on type switching characteristic. At one end, it provides good on state current but negative threshold voltage makes switching of the transistor difficult. To rectify this, normally off HEMT can be used as a suitable RF device. Saito et al. and Landford et al. designed a normally off HEMT by etching the AlGaN barrier region below gate, so that two dimensional electron gas (2DEG) is depleted at zero bias conditions. But there are issues associated with the design such as degraded output performance, low unity gain frequency and low breakdown voltage. Another challenge is to make RF devices more robust. Employing a filed plate design as designed by Dora et al, Kalmakar and Mishra and Saito et al. can improve the breakdown voltage but the added parasitic capacitances adversely affect the RF performance. Focusing only on RF performance matrices while designing renders the devices unusable and unreliable at higher operating voltages. Earlier work that report record high cut-off frequency have compromised in terms of breakdown voltage. In another work, Medjdoub et al. correlated 2DEG density (ns) with AlInN/GaN HEMT barrier layer scaling. Saito et al., carried out TCAD based studies to analyse the effect of contact on the breakdown voltage of AlGaN/GaN HEMT. Moreover, TCAD computations have been used to carry out RON – VBD optimization and mitigate drain-to-source punch through while Joshi et al. presented a computational modelling approach for HEMTs in general and physics of Carbon doping.
[0006] While these works independently address one or the other parameters to enhance DC or breakdown performance, there is no report on the approach for maximizing RF figures of merit parameters of HEMTs, while accounting for design - performance - nonlinearity trade-offs. At the RF front there have been only a few reports on design of RF HEMT devices and are limited to large signal analyses. There is no report on detailed small-signal design of RF HEMT devices.
[0007] There is, therefore, a requirement in the art for a methodology to optimise design of RF performance of a HEMT so as to improve RF figures of merit parameters with high cut off frequency without compromising breakdown voltage.

OBJECTS OF THE PRESENT DISCLOSURE
[0008] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are as listed herein below.
[0009] An object of the present disclosure is to provide for an approach to improve small signal RF performance.
[0010] An object of the present disclosure is to provide for an approach to enhance device linearity at high drain bias.
[0011] An object of the present disclosure is to provide for an approach to improve on-state device performance.
[0012] An object of the present disclosure is to provide for an approach to improve device transconductance.
[0013] An object of the present disclosure is to provide for an approach to facilitate high breakdown voltage and high cut-off frequency.
[0014] An object of the present disclosure is to provide design guidelines for obtaining high cut-off frequency in scaled HEMT devices.

SUMMARY
[0015] The present disclosure relates to design of high electron mobility transistor for enhancing performance and linearity.
[0016] In an aspect, the present disclosure provides a High Electron Mobility Transistor (HEMT) device for enhancing RF performance and linearity. The device may include a semiconductor barrier layer having a predefined barrier thickness, and a gate contact having a gate length. The gate contact in response to a voltage bias applied to the gate contact may be configured to modulate a conductivity of a two dimensional electron gas (2DEG) channel to control current between a source contact and a drain contact located on both sides of the gate contact respectively. The source contact and the gate contact may be separated by a first predefined distance, and the gate contact and the drain contact may be separated by a second predefined distance. The gate contact may be formed in a gate recess region that may extend through the semiconductor barrier layer such that depth of the gate recess region in the semiconductor barrier layer can be any or a combination of less than and equal to the predefined barrier thickness, and upon scaling any or a combination of the first predefined distance, the second predefined distance, the gate length and the depth of the gate recess region enable amplification of transconductance of the device and may increase cut-off frequency of the device which further can improve RF performance and linearity of the device.
[0017] In an embodiment, one or more nucleating layers may be disposed epitaxially on a semiconductor substrate layer, and one or more semiconductor buffer layers may be disposed epitaxially on the one or more nucleating layers. A semiconductor channel layer may be disposed on the one or more semiconductor buffer layers. The semiconductor forming the substrate may be any Silicon Carbide, Silicon and Sapphire semiconductors.
[0018] In an embodiment, the semiconductor barrier layer may be disposed on top of the semiconductor channel layer. The deposition of the semiconductor barrier layer on top of the semiconductor channel layer may generate a two degree electron gas sheet in the semiconductor channel layer and at the interface of the semiconductor barrier layer. The two degree electron gas sheet may be configured as the 2DEG electron gas channel to conduct current between the source contact and the drain contact formed on or in the semiconductor channel layer.
[0019] In an embodiment, the one or more semiconductor buffer layers can be formed of any or a combination of C-doped, unintentional doped and Fe-doped buffer layers.
[0020] In an embodiment, a c- doped buffer layer can be used for high voltage HEMT device sandwiched between the semiconductor channel layer and the one or more buffer layers. The semiconductor buffer layer and the semiconductor channel layer thickness can be optimized such that c-doped buffer layer can influence the 2DEG channel mobility and electron concentration, affecting the cut-off frequency of the device.
[0021] In an embodiment, a passivation film for covering at least a side surface of the semiconductor barrier layer to provide protection to the device can be disposed. The passivation film can include any GaN and any dielectric materials such as any or a combination of Al2O3, SiN, SiO2, GaO, HfO2, and SiON.
[0022] In an embodiment, a spacer layer may be disposed between the semiconductor barrier layer and the semiconductor channel layer.
[0023] In an embodiment, a highly doped GaN region may be disposed below any or a combination of source and the drain contacts for facilitating reduction of contact resistance.
[0024] In an embodiment, the source contact and the drain contact pertain to ohmic metal contacts made by using any or a combination of a plurality of layers and single layer metal with low contact resistance.
[0025] In an embodiment, the gate contact can include a top head portion and a bottom foot portion. In another embodiment, the gate contact may have a first shape and a second shape, the first shape may correspond to the top head portion being wider than the bottom foot portion to provide a ‘T’ shape to the gate contact. The second shape may correspond to the top head portion being at least equal to the bottom foot portion.
[0026] In an embodiment, a dielectric layer may be disposed surrounding the gate contact and between the gate contact and the gate recess region.
[0027] In an embodiment, the semiconductor barrier layer may be N-type doped having any or a combination of uniform, graded and Gaussian doping profile. In another embodiment, the semiconductor barrier layer may include group III-V materials which may be any AlN, AlGaN and InAlN.
[0028] In an embodiment, one or more transition layers may be disposed below the semiconductor buffer layer and above the substrate in any or a combination of step graded, linearly graded and AlN interlayer type.
[0029] In an embodiment, surface-traps up to a predefined length from gate contact can be deionized.
[0030] In an aspect, the present disclosure provides for a method for designing a HEMT device for enhancing RF performance and linearity of the HEMT device. The method is executed by a set of instructions executable at a processor, and may include the steps of: depositing a semiconductor barrier layer having a predefined barrier thickness on top of a semiconductor channel layer; etching a gate recess region through the semiconductor barrier layer such that depth of the gate recess region in the semiconductor barrier layer may be any or a combination of less than and equal to the predefined barrier thickness; depositing a gate contact having a gate length in the gate recess region. The gate contact may be configured to modulate a conductivity of a two dimensional electron gas (2DEG) channel in response to a bias voltage applied to the gate contact in order to control current between the source and the drain contact located on both sides of the gate contact respectively. The source contact and the gate contact may be separated by a first predefined distance, and the gate contact and the drain contact may be separated by a second predefined distance; and scaling any or a combination of the first predefined distance, the second predefined distance, the gate length and the depth of gate recess region to enable amplification of transconductance of the device with high cut-off frequencies to improve RF performance and linearity of the device.

BRIEF DESCRIPTION OF DRAWINGS
[0031] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain the principles of the present invention.
[0032] FIG. 1A illustrates an exemplary partially recessed gate with optimised contact, in accordance with an embodiment of the present disclosure.
[0033] FIG. 1B illustrates an exemplary flow diagram of the proposed method in accordance with an embodiment of the present disclosure.
[0034] FIGs. 2A-2D illustrate exemplary variations of the proposed device with partially recessed gate with optimised contact, in accordance with an embodiment of the present disclosure.
[0035] FIG. 3A illustrates exemplary plot of current-gain versus frequency characteristics that is experimentally extracted for the proposed HEMT device, in accordance with an embodiment of the present disclosure.
[0036] FIGs. 3B and 3C illustrate calibrated transfer and output characteristics respectively of the proposed HEMT device, in accordance with an embodiment of the present disclosure.
[0037] FIG. 3D illustrates an exemplary plot indicating effect of channel and buffer thickness on cut-off frequency of the HEMT device, in accordance with an embodiment of the present disclosure.
[0038] FIG. 3E illustrates an exemplary plot indicating distribution of 2DEG in channel as a function of channel thickness of the HEMT device, in accordance with an embodiment of the present disclosure.
[0039] FIGs. 3F and 3G illustrate exemplary plots indicating non-linearity in cut-off frequency and transconductance as a function of channel thickness respectively, in accordance with an embodiment of the present disclosure.
[0040] FIG. 4A illustrates an exemplary plot indicating effect of unintentional doping (UID) on transconductance of the HEMT device, in accordance with an embodiment of the present disclosure.
[0041] FIG. 4B illustrates an exemplary plot indicating dependence of fT roll-off with gate length as a function of UID, in accordance with an embodiment of the present disclosure.
[0042] FIG. 5A illustrates an exemplary representation of cut-off degradation with surface states up to a length LTrap from the gate edge, in accordance with an embodiment of the present disclosure.
[0043] FIG. 5B illustrates ab exemplary representation of simulated electron density in the channel as a function of trapping length LTrap, in accordance with an embodiment of the present disclosure.
[0044] FIG. 6A illustrates an exemplary representation of drop in relative cut-off frequency as a function of gate length for AlN/GaN HEMT and AlGaN/GaN HEMT, in accordance with an embodiment of the present disclosure.
[0045] FIG. 6B illustrates an exemplary representation of total gate capacitance as a function of gate length for AlN/GaN HEMT and AlGaN/GaN HEMT, in accordance with an embodiment of the present disclosure.
[0046] FIGs. 7A and 7B illustrate exemplary representations of cut-off frequency as a function of channel length and drain voltage in case of AlN/GaN HEMT and AlGaN/GaN HEMT respectively, in accordance with an embodiment of the present disclosure.
[0047] FIGs. 8A and 8B illustrate exemplary representations of cut-off frequency by simultaneous scaling of both gate length and barrier thickness for AlN barrier and AlGaN barrier respectively, in accordance with an embodiment of the present disclosure.
[0048] FIG. 8C illustrates an exemplary representation indicating optimisation of vertical and lateral electric fields in the channel to maximise cut-off frequency, in accordance with an embodiment of the present disclosure.
[0049] FIG. 9A illustrates an exemplary cross-sectional representation of a HEMT with a partially recessed barrier under the channel, in accordance with an embodiment of the present disclosure.
[0050] FIG. 9B illustrates an exemplary representation of unity-gain frequency as a function of drift/access region barrier thickness while using a partially recessed channel with a recess depth of 2nm, in accordance with an embodiment of the present disclosure.
[0051] FIGs. 10A – 10H illustrate advantage of partial recces gate stack design in terms of maximising RF performance by device scaling, in accordance with an embodiment of the present disclosure.
[0052] FIG. 11A illustrates an exemplary representation of change in transconductance with improving contact resistance in AlN barrier design with standard and partially recessed architectures, in accordance with an embodiment of the present disclosure.
[0053] FIG. 11B illustrates an exemplary representation of device output characteristics extracted at respective fT, max gate bias voltage in case of partially recessed barriers, in accordance with an embodiment of the present disclosure.
[0054] FIG. 12 illustrates exemplary depiction of RF figure of merit (FOM) parameters for standard design compared with partially recessed HEMT design, in accordance with an embodiment of the present disclosure.
DETAILED DESCRIPTION
[0055] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0056] Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. These exemplary embodiments are provided only for illustrative purposes and so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those of ordinary skill in the art.
[0057] The present invention provides solution to the above-mentioned problem in the art by providing a method for designing high electron mobility transistor (also referred to as HEMT hereinafter) design. Particularly, a HEMT device for improved performance and linearity can be designed based on scaling of the HEMT device having a partially recessed gate region and enhanced ohmic contact design. The scaled HEMT device with the recessed gate region and enhanced ohmic contact can enable reduction in ohmic contact resistance and optimization of electrostatics of a two dimensional gas (2DEG) channel between the ohmic contacts that can facilitate obtaining high cut-off frequency that can boost the device RF performance. The ohmic contacts can be any or a combination of source contact and drain contact.
[0058] FIG. 1A illustrates an exemplary partially recessed gate with optimised contact, in accordance with an embodiment of the present disclosure.
[0059] As illustrated, a HEMT device 100 (also referred to as device 100 herein after) can include a semiconductor substrate 102. In an exemplary embodiment, the semiconductor substrate can be Silicon Carbide (referred to as SiC hereinafter)) substrate but not limited to the like. In another exemplary embodiment, the semiconductor substrate can be any semiconductor such as Silicon and Sapphire semiconductors and the like.
[0060] The device 100 can include one or more nucleating layers 104 (collectively referred to as nucleating layers 104 and individually as nucleating layer 104) disposed above the semiconductor substrate 102. In an exemplary embodiment, the nucleating layer can be Aluminium Nitride (AlN). One or more semiconductor buffer layers 106 (collectively referred to as buffer layers 106 and individually as buffer layer 106) can be disposed on top of the nucleating layers 104. In an exemplary embodiment, at least a first buffer layer 106-1 can be Gallium Nitride (GaN) but not limited to the like and at least a second buffer layer 106-2 can be but not limited to Carbon doped GaN. At least the second buffer layer 106-2 can have a thickness denoted by tBuffer 136 in the exemplary illustration. Further, a semiconductor channel layer 108 can be deposited on top of the buffer layers 106. In an exemplary embodiment, the semiconductor channel layer 108 can be formed of but not limited to unintentional doping (also referred to as UID) GaN. The semiconductor channel layer 108 can have a thickness denoted by tChannel 134 in the exemplary illustration. Furthermore, the device can include a semiconductor barrier layer 110 (also referred to as barrier layer 110 herein) of predefined thickness disposed on top of the semiconductor channel layer 108. The semiconductor barrier layer 110 can be formed of group III-V materials such as any AlN, AlGaN and InAlN but not limited to the like. The deposition of the semiconductor barrier layer on top of the semiconductor channel layer can generate a two degree electron gas (also referred to as 2DEG hereinafter) sheet in the semiconductor channel layer 108 and at the interface of the semiconductor barrier layer 110 and can be configured as a 2DEG electron gas channel to conduct current between at least two ohmic contacts formed on or in the semiconductor channel layer.
[0061] In an embodiment, at least two ohmic contacts can include a source contact 116 and a drain contact 114 located on both sides of a gate contact 120 having a predefined gate length 138 (also referred to as Lg 138 herein). In yet another embodiment, the source contact 116 and the gate contact 120 can be separated by a first predefined distance 132 (also referred to as Lsg 132), and the gate contact 120 and the drain contact 114 can be separated by a second predefined distance (also referred to as Lgd 130).
[0062] In yet another embodiment, the gate contact 120 can be formed in a gate recess region that can extend through the semiconductor barrier layer 110 such that depth of the gate recess region 140 (also referred to as tRecess 140) in the barrier layer 110 can be any or a combination of less than and equal to the predefined barrier thickness.
[0063] The device 100 can also include a cap layer 112 on top of the barrier layer 110. The cap layer 112 can be formed of but not limited to GaN. In yet another embodiment, a passivation film 118 can cover at least a side surface of the semiconductor barrier layer 110 to provide protection to the device 100. The passivation film can include any GaN and any dielectric materials such as any or a combination of Al2O3, SiN, SiO2, GaO, HfO2, and SiON.
[0064] In an embodiment, the gate contact 120 can include a top head portion 124 and a bottom foot portion 122. In another embodiment, the gate contact can have a first shape corresponding to the top head portion 122 being wider than the bottom foot portion to 124 to provide a ‘T’ shape to the gate contact 120. In yet another embodiment, the gate contact 120 can have a second shape corresponding to the top head portion 122 being at least equal to the bottom foot portion 124.
[0065] FIG. 1B illustrates an exemplary flow diagram of the proposed method 150 in accordance with an embodiment of the present disclosure.
[0066] In an aspect, the present disclosure provides for a method 150 for designing a HEMT device for enhancing RF performance and linearity of the HEMT device 100. The method can be executed by a set of instructions executable at a processor, and may include at step 152, the step of depositing a semiconductor barrier layer 110 having a predefined barrier thickness on top of a semiconductor channel layer 108 and at step 154, the method may include the step of etching a gate recess region through the semiconductor barrier layer 110 such that depth of the gate recess region in the semiconductor barrier layer 110 may be any or a combination of less than and equal to the predefined barrier thickness and at step 156, depositing a gate contact 120 having a gate length 138 in the gate recess region configured to modulate a conductivity of a two dimensional electron gas (2DEG) channel 202 in response to a bias voltage applied to the gate contact 120 in order to control current between the source contact 116 and the drain 114 contact located on both sides of the gate contact 120 respectively. In an embodiment, the source contact 116 and the gate contact 120 may be separated by a first predefined distance 132, and the gate contact 120 and the drain contact 114 may be separated by a second predefined distance 130.
[0067] Further, the method can include a step 158 for scaling any or a combination of the first predefined distance 132, the second predefined distance 130, the gate length 138 and the depth 140 of gate recess region to enable amplification of transconductance of the device and increase cut-off frequency of the device in order to improve RF performance and linearity of the device 100.
[0068] FIGs. 2A-2D illustrate exemplary variations of the proposed device with partially recessed gate with optimised contact, in accordance with an embodiment of the present disclosure.
[0069] As illustrated in FIG. 2A, in an embodiment, the HEMT device 100 can include a spacer layer 204 disposed between the semiconductor barrier layer 110 and the semiconductor channel layer 108. The inclusion of the spacer layer 204 can improve the electron mobility in the 2DEG channel 202 by reducing the alloy scattering.
[0070] As illustrated in FIG. 2B, in another embodiment, the HEMT device 100 can include a highly doped GaN region 206 below any or a combination of the source contact 116 and the drain contact 114 to facilitate reduction of contact resistance.
[0071] As illustrated in FIG. 2C, in another embodiment, the HEMT device 100 can include a gate contact having a second shape 120-2 such that the top head portion 122 can be equal to the bottom foot portion 124.
[0072] In yet another embodiment, as illustrated in FIG. 2D, the HEMT device 100 can include a dielectric layer 208 surrounding the gate contact 120 and between the gate contact and the gate recess region.
[0073] Exemplary embodiments hereinafter can provide more insight to the present invention in accordance with the embodiments of the present disclosure.
[0074] In an embodiment, RF performance of the HEMT device 100 100 can be improved by increasing device 100 cut off frequency. The device 100 cut-off frequency (fT) is a measure of maximum frequency at which device 100 current can be effectively modulated by the gate contact of the device 100 and is given by

Where,
Cgs and Cgd are gate to source and gate to drain capacitances respectively;
gm is transconductance; gd is output conductance; and
Rs and Rd are source and drain resistances respectively.
[0075] The above expression represents total delay corresponding to carrier transport in the device 100. It can be classified into three components, namely, intrinsic delay, parasitic delay and extrinsic delay. The intrinsic and extrinsic delays can be governed by gm, Cgs and Cgd, and the extrinsic delay can be a function of Rs, Rd and gd. In addition to electrostatics due to the current flow in the 2DEG channel 202 between the source contact and the drain contact, non-linearity in short channel device 100s can also be affected by intrinsic resistivity of the buffer layer 106, which can be defined by unintentional doping during epi-growth. Surface states in HEMT can play significant role in determining DC and RF performance of the device 100. A co-design approach for device 100 design can facilitate in prediction of physical behaviour by analysing impact of surface traps on the cut-off frequency of the device 100. Further, the contact resistance dependency on cut-off frequency can be also affected by HEMT design.
[0076] FIG. 3A illustrates exemplary plot of current-gain versus frequency characteristics that is experimentally extracted for the proposed HEMT device 100, in accordance with an embodiment of the present disclosure.
[0077] FIGs. 3B and 3C illustrate calibrated transfer and output characteristics respectively of the proposed HEMT device 100, in accordance with an embodiment of the present disclosure.
[0078] In an exemplary implementation, a first set of details associated with a first set of instructions for small signal and DC operation can be calibrated with experimental results. Polarisation at all hetero-surfaces can be considered for accurately estimating energy band profile, 2DEG density and for accounting surface charge. The impact of surface and buffer traps can also be captured to provide precise estimation of breakdown voltage and frequency performance of the device 100 of the present disclosure. Contacts can be included as Schottky interfaces. Carrier transport can account for any or a combination of carrier and lattice heating by enabling hydrodynamic and thermodynamic transport models. Further, gate leakage due to Fowler-Nordheim tunnelling and Poole-Frenkel tunnelling can also considered. To predict breakdown voltage, C-doping induced buffer traps and resulting avalanche behaviour can be considered.
[0079] In an exemplary implementation, a second set of instructions for determining breakdown can be performed using an impact ionisation model according to Chynoweth law, with critical electric field for GaN as at least 3MV/cm but not limited to it. The breakdown voltage can be calculated by considering a drain current limit of at least 1mA/mm but not limited to it while applying off-state stress at the gate. A compensation doping profile can be considered in the buffer layer 106 to determine the impact of C-doped buffer. The acceptor and donor trap concentrations can be taken as at least 1018cm-3 and 5x1017cm-3 respectively, but not limited to the like. The carrier scattering due to presence of C-dopant atoms can be accounted for in the second set of instructions as per the Masetti Model. For the second set of instructions, the HEMT can have the following dimensions – the first predefined distance between source and gate (Lsg) of at least 40nm but not limited to it; the second predefined distance between gate and drain (Lgd) of at least 40nm but not limited to it; and gate length (Lg) of at least 20nm but not limited to it.
[0080] In an embodiment, a GaN buffer can be a key parameter for high voltage HEMT device 100 applications. Typically, C-doped buffer can be used for high voltage HEMT, which can include a carbon doped GaN layer sandwiched between the channel layer 108 and unintentional doping (UID) buffer layer 106. Carbon doping can mitigate buffer leakage current at higher drain bias voltages and can improve breakdown voltage of the device 100. For RF applications, the buffer layer and channel layer thickness can be required to be optimised as C-doping can influence the 2DEG concentration and channel mobility, affecting the cut-off frequency of the device 100. Two critical parameters can be channel thickness (tChannel) and C-doped buffer thickness (tBuffer).
[0081] FIG. 3D illustrates an exemplary plot indicating effect of channel and buffer thickness on cut-off frequency of the HEMT device 100, in accordance with an embodiment of the present disclosure. Channel layer thickness can be kept constant (at at least 150nm but not limited to it). In an implementation, the buffer thickness does not significantly affect the RF performance because lateral transport properties of the device 100 may not perturbed if C-dopants are deep in the buffer layer 106, away from the channel. The parasitic capacitances can be independent of the buffer thickness as deeply situated C-doped buffer does not participate in channel charging and discharging.
[0082] FIG. 3E illustrates an exemplary plot indicating distribution of 2DEG in channel as a function of channel thickness of the HEMT device 100, in accordance with an embodiment of the present disclosure. The channel layer 108 thickness can determine the distance of the C-doped buffer layer 106 from the 2DEG channel 202. The C-dopants can introduce acceptor type traps that can limit the spreading of hot carriers into the buffer layer 106 at high drain biases. It can lead to a reduction in output conductance, but at the same time, due to carrier trapping, can lead to reduction in effective 2DEG concentration. Further, increased carrier scattering due to C-dopants can degrade the on-state performance of the HEMT device 100.
[0083] In an exemplary implementation, improvement in fT is observed initially with increase in the channel layer 108 thickness, which can be attributed to reduced carrier scattering and channel layer 108 depletion, which, in turn, can improve the on-state characteristics of the HEMT device 100. It can be inferred that higher 2DEG concentration can be the key factor for improved cut-off frequency in HEMT. It can also be noted that increasing the channel thickness beyond 600nm ceases any improvement of fT as output conductance can start to dominate.
[0084] FIGs. 3F and 3G illustrate exemplary plots indicating non-linearity in cut-off frequency and transconductance as a function of the channel layer 108 thickness respectively, in accordance with an embodiment of the present disclosure. A desirable aspect of an RF device 100 is having a fixed cut-off frequency over a large gate swing. It can be observed that non-linearity with gate voltage increases significantly with decreasing channel layer 108 thickness, as shown in FIG. 3A.
[0085] As shown in FIG. 3F, the lower 2DEG density, as a result of carrier trapping, can degrade the device 100 transconductance. The fall in gm can be responsible for a steeper fT roll-off as a function of the gate contact 120 bias can be below a critical channel width. Hence, it is imperative to optimise channel layer 108 to achieve high breakdown voltage in conjunction with good linearity characteristics for the HEMT device 100.
[0086] FIG. 4A illustrates an exemplary plot indicating effect of unintentional doping (UID) on transconductance of the HEMT device 100, in accordance with an embodiment of the present disclosure.
[0087] FIG. 4B illustrates an exemplary plot indicating dependence of fT roll-off with gate length as a function of UID, in accordance with an embodiment of the present disclosure. High UID in GaN buffer layer 106 can result in parasitic conducting paths and can be responsible for drain source leakage current. It can lower the breakdown voltage by providing excess carriers for early impact ionisation. Leaky channel can cause hot electrons to spread out of the channel, deteriorating the carrier confinement. The increased output conductance can decrease the total drain current available for charging the channel capacitance, which can introduce an additional delay component, which is evident by the fall in transconductance at higher doping concentrations as shown in FIG. 4A. This can lead to reduction in fT, as shown in FIG. 4B. the effect of UID can be more pronounced in short channel device 100s. The increased parasitic coupling between the gate and drain can result in further degradation of fT.
[0088] FIG. 5A illustrates an exemplary representation of cut-off degradation with surface states up to a length LTrap from the gate contact contact, in accordance with an embodiment of the present disclosure. 2DEG channel in HEMT can be very sensitive to surface states. To study this effect, the virtual gate concept can be applied. The virtual gate formation can be attributed to trapping of electrons in surface states leading to a decrease in net positive charge on the surface. The charge trapping phenomenon can be particularly dominant at large signal device operation. The RF devices operate in the saturation region, resulting in depletion near the drain contact side of the gate contact to support the high drain bias. The resultant field at the gate contact can generate hot carriers that can ionise surface traps and deplete the 2DEG channel in the localized region. To emulate this behaviour, the surface traps up to the length LTrap from the gate contact 120, can be deionized.
[0089] FIG. 5B illustrates an exemplary representation of electron density in the 2DEG channel 202 as a function of trapping length LTrap obtained by a third set of instructions executed at the processor coupled to a computing device, in accordance with an embodiment of the present disclosure. Surface traps can be allowed to ionize starting from the drain contact 114 side of the gate contact 120, as a function of the drain field, which gradually can extend towards the drain contact 114 as the lateral field increased. At higher drain bias, the high energy channel electrons or hot electrons get trapped by the donor states present at the surface of the barrier layer 110. This can be enhanced by the high electric field at the gate contact 120 and can aid in virtual gate formation. Consequently, the 2DEG channel 202 in the channel layer 108 can deplete in proportion to trapping at the surface.
[0090] The rate of carrier trapping or virtual gate extension can be determined by the surface trap concentration, characteristics, and electric field in the 2DEG channel 202. Higher trapping rate at the surface can lead to extended depletion of electrons in the 2DEG channel 202 and, as a consequence, the gate contact to drain contact resistance increases. It can translate to added drain current delay, resulting in a slower device response at high frequencies. Cut-off frequency behaviour studied as a function of distance LTrap, can show substantial degradation with virtual gate length, which significantly can add to nonlinearity as a function of the drain field.
[0091] In an implementation, the characterization technique for the measurement of depletion width extension because of surface trap ionization can be by using a series of floating gates used to capture the trap ionization length as function of gate bias. However, the technique can be valid for off-state device characterization, where the surface trap ionization only due to gate injected carrier can be accounted. Whereas, in RF operation, the device can operate in saturation region, resulting in depletion near drain side of gate contact. One method to capture this can be by calculating the depletion region length as function of drain bias by employing drain delay extraction model.
[0092] In an exemplary implementation, when the method is employed on a passivated device or device under UV exposure, it can help to suppress the impact of surface traps, and the true drain delay contributed by applied drain bias can be measured. By subtracting it from the total delay time of device 100 measured without passivation or without UV exposure, the contribution of surface trap in total delay can be predicted.
[0093] FIG. 6A illustrates an exemplary representation of drop in relative cut-off frequency as a function of gate length for AlN/GaN HEMT and AlGaN/GaN HEMT, in accordance with an embodiment of the present disclosure. The barrier layer 110can control key device 100 performance parameters such as transconductance, gate leakage, 2DEG channel 202 density and device 100 linearity at high-frequency operation. AlGaN and AlN can be the barrier layer 110materials but not limited to the like that have been adopted for RF HEMT device 100s. As seen in FIG. 6A, the AlN barrier layer can offer better cut-off frequency compared to the AlGaN barrier layer device owing to higher polarization induced 2DEG electron density. In addition, the barrier thickness of at least 3.5nm but not limited to it can be used for AlN barrier layer 110in the HEMT device 100 to induce 2DEG electron channel density in excess of 1x1013cm-3 unlike the AlGaN barrier, in which case the barrier thickness of at least 25nm and not limited to it can be employed for similar 2DEG concentration. The reduced gate contact to 2DEG channel 202 distance, significantly can amplify the transconductance of the device 100, leading to high cut-off frequencies. However, the cut-off frequency rolls-off as a function of gate length, and this effect is much severe for the AlN barrier. This can be explained by examining the total gate capacitance (Cgg = Cgs + Cgd + Cchannel) for both the device 100s. The Cchannel is higher for the AlN barrier due to a relatively thin barrier. However, the remaining component of Cgg consists of the parasitic capacitances (Cgs+Cgd), which can result in lowering of the cut-off frequency.
[0094] FIG. 6B illustrates an exemplary representation of total gate capacitance as a function of gate length for AlN/GaN HEMT and AlGaN/GaN HEMT, in accordance with an embodiment of the present disclosure. As can be seen, there can be an increase in parasitic capacitance with gate length for both AlGaN and AlN barrier devices. The parasitic capacitances, however, increase at a much higher rate in the AlN barrier layer 110 with a slope of at least 0.95 compared to at least 0.35 for that of the AlGaN barrier layer. Similar to the channel capacitance, the parasitic capacitance can also be a function of barrier layer 110thickness, dielectric constant and 2DEG channel 202 electron density. Hence, the parasitic capacitance can rise at a much faster rate in the AlN barrier layer, resulting in poor frequency response for long channel devices.
[0095] FIGs. 7A and 7B illustrate exemplary representations of cut-off frequency as a function of 2DEG channel 202 length and drain voltage in case of AlN/GaN HEMT and AlGaN/GaN HEMT respectively, in accordance with an embodiment of the present disclosure.
[0096] RF performance drift with drain voltage for short channel length device 100 can depict increased nonlinearity, which can be observed for AlN as well as AlGaN barrier HEMT device 100s. As the drain field is increased, carriers drift with higher velocity, which can improve the transconductance of the device 100. It can translate to higher cut-off frequencies until velocity saturation can be reached. With further increase in drain voltage, the depletion region below the gate contact can extend towards the drain contact to support additional electric field giving rise to additional carrier transit time that can be characterized by drain delay. For short-channel device 100s, drain delay can be observed to be significantly increased at higher drain voltages, which lowers the cut-off frequency and adds to nonlinearity. Non-linearity can be a direct consequence of short-channel effects in HEMT, which can arise due to poor gate control. In an embodiment, the barrier layer 110thickness can play a decisive role in gate charge modulation.
[0097] FIGs. 8A and 8B illustrate exemplary representations of cut-off frequency by simultaneous scaling of both gate length and barrier thickness for AlN barrier and AlGaN barrier respectively, in accordance with an embodiment of the present disclosure. It can be observed that the device 100s show significantly less degradation in fT as a function of barrier layer 110thickness with the AlN barrier layer 110 compared to the AlGaN barrier layer 110device 100. In an implementation, below a critical barrier thickness, fT roll-off can be attributed to incomplete surface trap ionization that can result in low 2DEG concentration in the 2DEG channel 202. However, the critical thickness for the AlGaN barrier layer 110can be much higher compared to the AlN barrier. It can allow much larger aspect ratio (Lg/tBarrier) in AlN/GaN HEMT device 100s.
[0098] In another exemplary implementation, for a short gate length below 100 nm, the lateral electric field can become dominant and the vertical electric field component can start diminishing resulting in poor gate controllability and lower gate modulation efficiency, which collectively degrade the cut-off frequency performance for AlN barrier layer and AlGaN barrier layer respectively. To mitigate the short channel effects and nonlinearity behaviour, it can be required to enhance the vertical electric field, which can be achieved by top barrier layer 110scaling.
[0099] FIG. 8C illustrates an exemplary representation indicating optimisation of vertical and lateral electric fields in the channel to maximise cut-off frequency, in accordance with an embodiment of the present disclosure. Due to the properties of the AlN barrier layer, the barrier layer thickness can be scaled down to at least 2nm. It can allow wider design windows for AlN/GaN RF HEMT design for given specifications as evident from the fT.Lg (GHz.µm) product. For a smaller aspect ratio, the short channel effects can dominate, deteriorating the RF performance. Hence, barrier layer scaling is a critical design aspect when the gate length is shrunk to maximize the cut off frequency without compromising with device 100 linearity.
[00100] FIG. 9A illustrates an exemplary cross-sectional representation of a HEMT with a partially recessed barrier under the channel, in accordance with an embodiment of the present disclosure. To maximize cut-off frequency without compromising the linearity of the device 100, the barrier layer, and channel length should be scaled simultaneously. Barrier layer 110scaling, however, has an adverse impact on the device 100’s ON state performance due to reduced 2DEG concentration in the 2DEG channel 202. Besides, it also can amplify the virtual gate effect, which can increase the nonlinearity contributed by drain field-dependent ionization of surface states.
[00101] In the partially gate recess region design, as depicted in FIG. 9A, recovers the device 100’s ON-state performance and improves RF performance and the linearity behaviour.
[00102] FIG. 9B illustrates an exemplary representation of unity-gain frequency as a function of drift/access region barrier thickness while using a partially recessed channel with a recess depth of at least 2nm, in accordance with an embodiment of the present disclosure. Here, the AlN barrier layer 110below the gate can be etched to have a reduced thickness of at least 2nm but not limited to it, whereas the thickness of the barrier layer 110in access/drift regions can be increased. It can be seen that with increasing gm, fT can improve when the barrier layer 110thickness in the access/drift regions can be increased, owing to improved RON and ON current. The partial gate recess region can ensure better gate control and optimum electrostatics in the channel, which mitigates short channel effect induced nonlinearity. The access and drift region resistance can be determined by the 2DEG density in these regions. As the barrier layer 110thickness is well above the critical thickness, the un-etched barrier regions do not suffer from high resistivity. An improved DC performance can result in higher power density at a given frequency. The optimized design can offer both improved frequency performance and power density.
[00103] FIGs. 10A – 10H illustrate advantage of partial gate recess region design in terms of maximising RF performance by device 100 scaling, in accordance with an embodiment of the present disclosure.
[00104] Here, the partially recessed design of gate recess region can be implemented for both AlN and AlGaN barrier layer 110with recess thickness of at least 2nm (tBarrier,AlN = 3.5nm) but not limited to it and at least 10nm (tBarrier,AlGaN = 25nm) but not limited to it respectively. The performance of standard design (un-recessed) can also be evaluated while scaling the lateral design parameters.
[00105] FIGs. 10A – 10C and FIGs. 10E – 10G illustrate significant improvement in cut-off frequency for partially recessed design for gate recess region while scaling the lateral device 100 dimensions – the first predefined distance between the source contact and the gate contact (Lsg), gate length (Lg) and the second predefined distance between the gate contact and drain contact (Lgd). In an exemplary implementation, although the cut-off frequency for the AlN barrier layer is higher compared to the AlGaN barrier layer, the relative improvement in fT from standard to the partially-recessed device can be significant in AlGaN HEMT. It can be ascribed to deeper localized barrier etching below the gate contact in case of AlGaN barrier layer 110compared to the AlN barrier layer, therefore leading to higher relative increase in transconductance in AlGaN/GaN devices. In yet another implementation, the short channel effects as results of lateral scaling can be considerably suppressed in the AlN barrier layer 110and recessed device 100 designs. It corroborates with the earlier discussion on the importance of better electrostatic control in the gate region. The short channel effects can dominant in standard AlGaN barrier layer design as observed in FIGs. 10E – 10G. The recessed architecture effectively can mitigate non-uniform field distribution in the channel by improving the aspect ratio (Lg/tBarrier).
[00106] It can be desirable to minimize the ohmic contact resistance to reduce the external parasitic delay in the device. There are several parameters that have to be addressed such as, in what conditions the contact resistance can become an indispensable parameter so that the techniques such as regrowth must be used to maximize the performance and the contact resistance dependence on the barrier type or device 100 architecture have to be known.
[00107] In an exemplary implementation, both AlN and AlGaN barrier layer architectures can be analysed with varying contact resistance. In addition, the device 100 designs – both standard and partially recessed barrier can be analysed and modelled, and the cut-off frequency behaviour is shown in FIG. 10D and FIG. 10H for AlN and AlGaN barrier layer 110respectively. Following observations can be made from the results, the increase in fT for AlN barrier is higher compared to AlGaN barrier design; devices with low drift region length (Lgd = 40nm) show strong dependence on contact resistance; for high drift region length (Lgd = 1µm) devices, the cut-off frequency dependence decreases significantly; and the recessed devices show rapid improvement in cut-off frequency as contact resistance is reduced compared to standard barrier architecture.
[00108] In an embodiment, AlN barrier layer, accounting for higher polarization charges, can induce larger 2DEG channel 202 concentration as compared to the AlGaN barrier layer. It signifies, that the ratio of (Ron/Rcontact) can be considerably higher in the AlGaN barrier layer 110compared to the AlN barrier layer 110design. Any improvement in contact resistance, thus has a larger contribution in the reduction of parasitic resistance in the case of the AlN barrier layer, as observed in `FIGs. 10D and 10H respectively. Similarly, increasing the drift length (Lgd) can result in high (Ron/Rcontact) ratio. It can reduce sensitivity of the cut-off frequency on contact resistance. In the case of the recessed device 100, the impact of contact resistance can be considerable compared to the standard barrier device.
[00109] FIG. 11A illustrates an exemplary representation of change in transconductance with improving contact resistance in AlN barrier design with standard and partially recessed architectures, in accordance with an embodiment of the present disclosure. Comparing the transconductance of the at least two architectures with varying contact resistance can reveal that for partially recessed design, improvement in gm with decrease in contact resistance can be substantial compared to standard architecture.
[00110] FIG. 11B illustrates an exemplary representation of device 100 output characteristics extracted at respective fT, max gate bias voltage in case of partially recessed barriers, in accordance with an embodiment of the present disclosure. Due to a positive shift in threshold voltage, the gate bias voltage at which fT peaks, can shift to positive in case of partially recessed HEMT. At their respective fT, max bias voltages, the partially recessed device 100 can have higher drain current. It can translate to low (Ron/Rcontact) ratio for partially recessed architecture and hence, higher cut-off frequency at low contact resistance can be observed.
[00111] FIG. 12 illustrates exemplary depiction of RF figure of merit (FOM) parameters for standard design compared with partially recessed HEMT design, in accordance with an embodiment of the present disclosure. Comparing the AlN/GaN HEMT device 100’s RF figure of merit parameters of at least three device structures - partially recessed gate structure (trecess = 2nm); and standard structures with a barrier layer 110thickness of 3.5nm and 2 nm, it can be seen that the optimized partially recessed gate design outperforms the other two standard designs in terms of all the RF performance FOM parameters.
[00112] The present disclosure provides guidelines for the physical RF design of AlGaN/GaN HEMT using a physics-based instruction set executable at a processor of a computing device, which can facilitate improved performance as well as the linearity of RF HEMTs. While the GaN channel thickness can be optimized to maximize RF performance without compromising short-channel effects and device 100 linearity, it can be observed that a higher UID concentration can limit the channel layer 108 length scaling and can lower the RF performance for a given channel layer 108 length. This can be attributed to the parasitic leakage path induced through the UID GaN channel when UID concentration was increased. Furthermore, it can be observed that the spread of ionized surface traps across the GaN surface, above the drift region increases with the drain field that can add serious nonlinearity in the RF behaviour. Cut-off frequency roll-off in device 100s with aggressive gate scaling can be attributed to short-channel effects and poor gate electrostatics. This in conjunction with drain field-dependent surface trap ionization magnified nonlinearity. The AlN/GaN HEMT devices of the present disclosure can predict better linearity characteristics compared to AlGaN/GaN HEMT at large drain bias and sub 100nm channel lengths. It is found that the key to improve RF performance and reduce nonlinearity is improved electrostatics in the channel. This can be achieved by demonstrating a partially-recessed gate design. Moreover, compared with standard (non-recessed gate) design, improvement in RF performance can be found to be higher in AlN HEMT and partially-recessed barrier design as a function of lateral device scaling and contact resistance.
[00113] It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive patient matter, therefore, is not to be restricted except in the spirit of the appended claims.
[00114] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE PRESENT DISCLOSURE
[00115] The present disclosure provides for an approach to improve small signal RF performance.
[00116] The present disclosure provides for an approach to enhance device linearity at high drain bias.
[00117] The present disclosure provides for an approach to improve on-state device performance.
[00118] The present disclosure provides for an approach to improve device transconductance.
[00119] The present disclosure provides for an approach to facilitate high breakdown voltage and high cut-off frequency.
[00120] The present disclosure provides design guidelines for obtaining high cut-off frequency in scaled HEMT devices.
,CLAIMS:A High Electron Mobility Transistor device for enhancing RF performance and linearity, said device comprising:
a semiconductor barrier layer having a predefined barrier thickness;
a gate contact having a gate length, wherein the gate contact, in response to a voltage bias applied to the gate contact, modulates conductivity of a two-dimensional electron gas (2DEG) channel to control current between a source contact and a drain contact located on both sides of the gate contact respectively, wherein the source contact and the gate contact are separated by a first predefined distance, and the gate contact and the drain contact are separated by a second predefined distance,
wherein the gate contact is formed in a gate recess region, wherein the gate recess region extends through the semiconductor barrier layer such that depth of the gate recess region in the barrier layer is any or a combination of less than and equal to the predefined barrier thickness, and
wherein, upon scaling any or a combination of the first predefined distance, the second predefined distance, the gate length, and the depth of the gate recess region, transconductance of the device is amplified and cut off frequency is increased so as to improve RF performance and linearity of the device.
2. The device as claimed in claim 1, wherein a semiconductor substrate layer with one or more nucleating layers is disposed epitaxially on the semiconductor substrate layer, and wherein one or more semiconductor buffer layers are disposed epitaxially on the one or more nucleating layers, and wherein a semiconductor channel layer is disposed on the one or more semiconductor buffer layers, wherein the semiconductor forming the substrate is any or a combination of Silicon Carbide, Silicon and Sapphire semiconductors.
3. The device as claimed in claim 2, wherein the one or more semiconductor buffer layers comprise any or a combination of C-doped, unintentional doped and Fe-doped buffer layers.
4. The device as claimed in claim 3, wherein the C-doped buffer layer is used for high voltage HEMT device, wherein the C-doped buffer layer is sandwiched between the semiconductor channel layer and one or more buffer layers, wherein the buffer layer and the channel layer thickness is such that the C- doped buffer layer influences the 2DEG channel mobility and electron concentration and affects cut-off frequency of the device.
5. The device as claimed in claim 1, wherein the semiconductor barrier layer is disposed on top of a semiconductor channel layer to generate a two degree electron gas sheet, wherein the two degree electron gas sheet generated in the semiconductor channel layer and at the interface of the semiconductor barrier layer is configured as the 2DEG electron gas channel to conduct current between the source and the drain contact formed on or in the semiconductor channel layer.
6. The device as claimed in claim 1, said device comprising a passivation film for covering at least a side surface of the semiconductor barrier layer, wherein the passivation film provides protection to the device, and comprises of any or a combination of GaN and any a dielectric material selected from any or a combination of Al2O3, SiN, SiO2, GaO, HfO2, and SiON.
7. The device as claimed in claim 2, said device comprising a spacer layer that is disposed between the semiconductor barrier layer and the semiconductor channel layer.
8. The device as claimed in claim 1, said device comprises a highly doped GaN region below any or a combination of source and the drain contacts.
9. The device as claimed in claim 1, wherein the gate contact comprises a top head portion and a bottom foot portion, wherein the gate contact has a first shape and a second shape, wherein the first shape corresponds to the top head portion being wider than the bottom foot portion to provide a ‘T’ shape to the gate contact, and wherein the second shape corresponds to the top head portion being at least equal to the bottom foot portion.
10. The device as claimed in claim 1, wherein a dielectric layer is disposed surrounding the gate contact and between the gate contact and the gate recess region.
11. The device as claimed in claim 1, wherein the semiconductor barrier layer is N-type doped having any or a combination of uniform, graded and Gaussian doping profile and wherein the semiconductor barrier layer comprises group III-V materials, wherein the group III-V materials are any AlN, AlGaN and InAlN.
12. The device as claimed in claim 2, wherein one or more transition layers are disposed below the semiconductor buffer layer and above the substrate, wherein the one or more transition layers are any or a combination of step graded, linearly graded and AlN interlayer type.
13. The device as claimed in claim 1, wherein the source contact and the drain contacts pertain to ohmic metal contacts, wherein the ohmic metal contacts are made using any or a combination of a plurality of layers and a single layer metal with low contact resistance.
14. The device as claimed in claim 1, wherein surface-traps up to a predefined length from the gate contact is deionized.
15. A method for enhancing RF performance and linearity of a HEMT device, said method being executed by a set of instructions at a processor, and comprising:
depositing a semiconductor barrier layer having a predefined barrier thickness on top of a semiconductor channel layer;
etching a gate recess region through the semiconductor barrier layer such that depth of the gate recess region in the semiconductor barrier layer is any or a combination of less than and equal to the predefined barrier thickness;
depositing a gate contact having a gate length in the gate recess region configured to modulate a conductivity of a two dimensional electron gas (2DEG) channel in response to a bias voltage applied to the gate contact to control current between the source and the drain contact located on both sides of the gate contact respectively, wherein the source contact and the gate contact is separated by a first predefined distance, and the gate contact and the drain contact is separated by a second predefined distance; and
scaling any or a combination of the first predefined distance, the second predefined distance, the gate length and the depth of gate recess region, wherein upon scaling transconductance of the device amplifies resulting in high cut-off frequencies, wherein the high cut off frequencies improves RF performance and linearity of the device.