DESC:TECHNICAL FIELD
[0001] The present disclosure relates to the field of amplifier and microwave communication system. More particularly, the present disclosure relates to a C-Band self-biased two stage low noise amplifier (LNA) with high gain and ultra-low noise using InGaAs technology to achieve smaller die size, low noise figure and high gain.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] Low noise amplifiers (LNA) are used to receive weak signals and amplify them with low noise figure. C-band refers to a range of frequencies used in microwave communication which ranges from 4-7 GHz. LNAs are used to reduce unwanted noise content in the first stage of amplification. For high sensitivity of the receiver, the LNA must have good gain and low noise figure. LNA noise contribution will impact the overall Signal-to-Noise ratio of the receiver. Hence, it is important to design a stable LNA with good gain, low return loss and sufficient output power, minimizing the overall noise contribution of the receiver.
[0004] GaAs based monolithic microwave integrated circuits are vastly used in Radar & communication systems because of their high yield and reliable performance. Active electronically scanned array (AESA) RADARs are one such area where low noise amplifiers are used for miniaturizing size as well as improving signal to noise ratio. Transmit/Receive (T/R) modules are the core components of AESA radars, wherein the LNAs used in the receiver path play a key role in ensuring excellent receiver signal sensitivity. Hence for a low noise amplifier intended for use in T/R modules it is critical to achieve lower size, weight, power at lower cost. This LNA is specially designed for transmit/receive modules used in Active Electronically Scanned Array (AESA) RADAR.
[0005] Chinese Patent Document Number CN207339798U discloses a C Band Low noise amplifier which incorporates a power supply stabilization circuit and consists of two stages of amplification. The Noise Figure is around 3dB and 20d B gain with in-band flatness of 2dB. The disclosed LNA has been realized using discrete QFNs and power supply stabilization circuit uses additional discrete components. The invention is not a monolithic realization. a Low Noise Amplifier using discrete components but does not detail the techniques to achieving the same on single GaAs substrate
[0006] The United States Patent Document Number US 4,771,247 discloses a MMIC low noise amplifier for use at microwave frequencies. The LNA is a two-stage amplifier incorporating matching networks at the input and output. The die size is 2.14mmX0.99mm and designed for 5-6GHz, operating at +3V Drain Voltage and -1V gate voltage. the gain is about 20dB and noise figure is about 2 dB. Maximum gain is achieved at 80mA.The LNA has been fabricated on GaAs process which offers 0.5um gate length. It provides a way to realize a monolithic implementation of an LNA on GaAs, however, it requires drain and gate biasing requiring two supplies. The gain is 3dB lower than the current invention
[0007] The PCT Document Number WO 2011011754Al discloses a multi-mode low noise amplifier (LNA) with transformer source degeneration. It incorporates technique of using inductors at source of the NMOS devices in each stage of the LNA to improve linearity. This is mainly intended for use in wireless applications such as Bluetooth, Wifi, PDAs and mobile handsets. The technology used is Silicon. The technique of source degeneration used in multi stage amplifiers in Silicon technology may not be suitable for direct application at microwave frequencies, long range applications such as RADAR. The cited prior art document discloses the use of transformer source degeneration in multistage LNAs. However, it increases complexity and requires the use of Silicon technology.
[0008] The United States Patent Document US9641130 discloses Low noise amplifier with noise and linearity improvement. A low noise amplifier (LNA) has been disclosed for the noise and linearity performance improvement. The LNA includes an amplifying transistor and an auxiliary transistor. However, the frequency of operation is 0.5 to 4 GHz and requires two different technologies i.e BJT/HBT as an amplifying transistor and MOSFET/PHEMT as an auxiliary transistor.
[0009] Therefore, there is a need in the art for a monolithic C-Band self-biased two stage LNA with high gain and ultra-low noise using InGaAs pHEMT technology to achieve smaller die size, low noise figure and high gain, specifically for use in T/R modules wherein size, weight, power and cost requirements are critical.

OBJECTS OF THE PRESENT DISCLOSURE
[0010] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are as listed herein below.
[0011] It is an object of the present disclosure to provide a high gain and ultra-low noise figure 2-stage self–biased C-band low noise amplifier.
[0012] It is an object of the present disclosure to provide a high gain and ultra-low noise figure 2-stage self–biased C-band low noise amplifier, which is self-biased, light weight compact, and power efficient.
[0013] It is an object of the present disclosure to provide input matching in the amplifier for optimum noise figure match.
[0014] It is an object of the present disclosure to improve return losses at both input and output ports of the amplifier.
[0015] It is an object of the present disclosure to provide inter-stage matching RLC networks for better gain flatness over a broader frequency range and for better impedance match.

SUMMARY
[0016] The present disclosure relates to the field of amplifier and microwave communication system. More particularly, the present disclosure relates to a C-Band self-biased two stage low noise amplifier (LNA) with high gain and ultra-low noise using InGaAs technology to achieve smaller die size, low noise figure and high gain.
[0017] An aspect of the present disclosure pertains to a high gain and ultra-low noise C band amplifier, the amplifier comprises: an input matching unit configured to receive a first set of signals from a source, wherein the input matching unit may comprise a first capacitor, a first resistor, and a first inductor, having a predetermined impedance to facilitate impedance matching between the source and the amplifier; a first amplification unit operatively coupled to the input matching unit, wherein first amplification unit may comprise a first field effect transistor (FET) configured to filter the first set of signals by removing noise of first predefined frequencies from the first set of signals, and amplify the filtered first set of signals to a first predefined level to generate a second set of signals; and a second first amplification unit may be operatively coupled to the first amplification unit, wherein second amplification unit may comprise a second field effect transistor (FET) configured to filter the second set of signals by removing noise of second predefined frequencies from the second set of signals, and amplify the filtered second set of signals to a second predefined level to generate a set of output signals, wherein an inter-stage matching unit is configured between first amplification unit and the second amplification unit, to facilitate impedance matching between the first amplification unit and the second amplification unit.
[0018] In an aspect, the amplifier may comprise an output matching unit operatively coupled to the second amplification unit, and wherein the output matching unit may comprise a first set of four cascaded capacitors of predefined capacitance.
[0019] In an aspect, the first FET and the second FET may be a pseudomorphic high electron mobility transistor (pHEMT), and wherein the amplifier may be fabricated on an Indium gallium Arsenide (InGaAs) substrate of predefined thickness.
[0020] In an aspect, the pHEMT of each of the first FET and the second FET may be having a gate periphery of 300 micrometre.
[0021] In an aspect, the output power of the amplifier may be controlled by changing gate bias of the second amplification stage by shorting the gate of the second FET to ground using a set of resistors.
[0022] In an aspect, the inter-stage matching unit may comprise a third set of capacitors of a predefined capacitance, a second resistor of predefined resistance, and a second inductor of a predefined inductance, to facilitate impedance matching between the first amplification unit and the second amplification unit.
[0023] In an aspect, the amplifier may be self-biased, and configured with a single power source.
[0024] In an aspect, the amplifier may comprise an input port to enable the amplifier to receive the first set of signals form the source, and wherein the amplifier may comprise an output port to enable the amplifier to transmit the set of output signals.
[0025] In an aspect the amplifier may comprise a second set of capacitors being configured at the input port and the output port to block DC signals.
[0026] In an aspect, the amplifier may be configured to improve return losses at both the input port and the output port over a C band frequency range of 4-7 GHz.

BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0028] The diagrams are for illustration only, which thus is not a limitation of the present disclosure, and wherein:
[0029] FIG. 1 illustrates an architecture of the proposed amplifier, in accordance with an embodiment of the present invention.
[0030] FIG. 2 illustrates an exemplary layout of the proposed amplifier, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION
[0031] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0032] Various terms as used herein are shown below. To the extent a term used in a claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
[0033] In some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
[0034] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0035] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0036] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.
[0037] The present disclosure relates to the field of amplifier and microwave communication system. More particularly, the present disclosure relates to a C-Band self-biased two stage low noise amplifier (LNA) with high gain and ultra-low noise using InGaAs technology to achieve smaller die size, low noise figure and high gain.
[0038] According to an aspect, the present disclosure elaborates upon a high gain and ultra-low noise C band amplifier, the amplifier includes: an input matching unit configured to receive a first set of signals from a source, wherein the input matching unit can include a first capacitor, a first resistor, and a first inductor, having a predetermined impedance to facilitate impedance matching between the source and the amplifier; a first amplification unit operatively coupled to the input matching unit, wherein first amplification unit can include a first field effect transistor (FET) configured to filter the first set of signals by removing noise of first predefined frequencies from the first set of signals, and amplify the filtered first set of signals to a first predefined level to generate a second set of signals; and a second first amplification unit can be operatively coupled to the first amplification unit, wherein second amplification unit can include a second field effect transistor (FET) configured to filter the second set of signals by removing noise of second predefined frequencies from the second set of signals, and amplify the filtered second set of signals to a second predefined level to generate a set of output signals, wherein an inter-stage matching unit is configured between first amplification unit and the second amplification unit, to facilitate impedance matching between the first amplification unit and the second amplification unit.
[0039] In an embodiment, the amplifier can include an output matching unit operatively coupled to the second amplification unit, and wherein the output matching unit can include a first set of four cascaded capacitors of predefined capacitance.
[0040] In an embodiment, the first FET and the second FET can be a pseudomorphic high electron mobility transistor (pHEMT), and wherein the amplifier can be fabricated on an Indium gallium Arsenide (InGaAs) substrate of predefined thickness.
[0041] In an embodiment, the pHEMT of each of the first FET and the second FET can be having a gate periphery of 300 micrometre.
[0042] In an embodiment, the output power of the amplifier can be controlled by changing gate bias of the second amplification stage by shorting the gate of the second FET to ground using a set of resistors.
[0043] In an embodiment, the inter-stage matching unit can include a third set of capacitors of a predefined capacitance, a second resistor of predefined resistance, and a second inductor of a predefined inductance, to facilitate impedance matching between the first amplification unit and the second amplification unit.
[0044] In an embodiment, the amplifier can be self-biased, and configured with a single power source.
[0045] In an embodiment, the amplifier can include an input port to enable the amplifier to receive the first set of signals form the source, and wherein the amplifier can include an output port to enable the amplifier to transmit the set of output signals.
[0046] In an embodiment the amplifier can include a second set of capacitors being configured at the input port and the output port to block DC signals.
[0047] In an embodiment, the amplifier can be configured to improve return losses at both the input port and the output port over a C band frequency range of 4-7 GHz.
[0048] FIG. 1 illustrates an architecture of the proposed amplifier, in accordance with an embodiment of the present invention.
[0049] FIG. 2 illustrates an exemplary layout of the proposed amplifier, in accordance with an embodiment of the present invention.
[0050] As illustrated in FIGs. 1 and 2, in an embodiment, the proposed amplifier 100 can include an input matching unit 101 configured to receive a first set of signals from a source. The input matching unit 101 can include a first capacitor of predefined capacitance, a first resistor of predefined resistance, and a first inductor of predefined inductance, having a predetermined impedance to facilitate impedance matching between the source and the amplifier 100.
[0051] In an embodiment, the amplifier 100 can include a first amplification unit 102 operatively coupled to the input matching unit 101. The first amplification unit 102 can include a first field effect transistor (FET) configured to receive the first set of signals form the input matching unit 101; filter the first set of signals by removing noise of first predefined frequencies from the first set of signals, and further amplify the filtered first set of signals to a first predefined level to generate a second set of signals.
[0052] In an embodiment, the amplifier 100 can include a second first amplification 104 unit that can be operatively coupled to the first amplification unit 102 though an inter-stage matching unit 103. The second amplification unit 104 can include a second field effect transistor (FET) configured to filter the second set of signals by removing noise of second predefined frequencies from the second set of signals, and amplify the filtered second set of signals to a second predefined level to generate a set of output signals.
[0053] In an embodiment, the inter-stage matching unit 103 can be configured between first amplification unit 102 and the second amplification unit 104, to facilitate impedance matching between the first amplification unit 102 and the second amplification unit 104.
[0054] In an embodiment, the inter-stage matching unit 103 can include a RLC circuit 202 having third set of capacitors of a predefined capacitance, a second resistor of predefined resistance, and a second inductor of a predefined inductance, to facilitate impedance matching between the first amplification unit 102 and the second amplification unit 104.
[0055] In an embodiment, the amplifier 100 can include an output matching unit 105 operatively coupled to the second amplification unit 104. The output matching unit 105 can have a predefined impedance to facilitate impedance matching between the amplifier 100 and one or more devices coupled to the output of the amplifier. In an exemplary embodiment, the output matching unit can include a first set of four cascaded capacitors 205 of predefined capacitance.
[0056] In an embodiment, the amplifier 100 can include an input port (RF IN) to enable the amplifier 100 to be operatively coupled to the source, and receive the first set of signals form the source. Further, the amplifier 100 can include an output port (RF OUT) to enable the amplifier 100 to be operatively coupled to the one or more devices, and to transmit the set of output signals to the one or more devices.
[0057] In an exemplary embodiment, the first FET and the second FET can be a pseudomorphic high electron mobility transistor (pHEMT). The amplifier can be fabricated on an Indium gallium Arsenide (InGaAs) substrate of predefined thickness. In another exemplary embodiment, the pHEMT of each of the first FET and the second FET can be having a gate periphery of 300 micrometre.
[0058] In an embodiment, the amplifier 100 can be self-biased, and configured with a single power source. The amplifier (100) has been self-biased to ensure single supply operation, for maintaining stability of the amplifier 100
[0059] As illustrated in FIG. 2, in an embodiment the amplifier 100 can include a second set of capacitors (207, 208) being configured at the input port (RF IN) side and the output port (RF OUT) side to block DC signals. In an implementation, the realization of the output matching unit 105 with four series capacitors 205 cascaded, can have an effective capacitance value less than 0.12pF.
[0060] In an implementation, the proposed self-biased, monolithic, single supply, two stage low noise amplifier 100 can be fabricated using 0.15um InGaAs pseudomorphic high electron mobility transistor(pHEMT) technology, with high gain and low noise figure. The Input matching unit 101, the first amplification unit 102, inter-stage matching unit 10, the second amplification unit 104, and the output matching unit 105 can be realized with overall die (100) size less than 1.5 mm in both x and y directions, to provide the following features:
a. Operating frequency bandwidth of C Band.
b. Gain of 22dB typical across the C Band frequency.
c. Noise figure of Typical <1 dB across the frequency band.
d. Output power compression- P1dB of +11dBm typical and Output third order intercept point of minimum +21dBm.
e. Return losses better than 10dB at both input and output ports in C Band.
f. Self-biased topology with single supply operation with operating range from 2V to 4V with current consumption of 33mA typical at 3V supply.
g. Maximum power handling capability up to 27dBm in C Band
[0061] In an embodiment, the output power of the amplifier 100 can be controlled by changing gate bias of the second amplification stage by shorting the gate of the second FET of the second amplification unit 104 to ground using a set of resistors 204.
[0062] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention can be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGS OF THE INVENTION
[0063] The proposed invention provides a high gain and ultra-low noise figure 2-stage self–biased C-band low noise amplifier.
[0064] The proposed invention provides a high gain and ultra-low noise figure 2-stage self–biased C-band low noise amplifier, which is self-biased, light weight compact, and power efficient.
[0065] The proposed invention provides input matching in the amplifier for optimum noise figure match.
[0066] The proposed invention improves return losses at both input and output ports of the amplifier.
[0067] The proposed invention provides inter-stage matching RLC networks for better gain flatness over a broader frequency range and for better impedance match.

,CLAIMS:1. A high gain and ultra-low noise C band amplifier, the amplifier comprises:
an input matching unit configured to receive a first set of signals from a source, wherein the input matching unit comprises a first capacitor, a first resistor, and a first inductor, having a predetermined impedance to facilitate impedance matching between the source and the amplifier;
a first amplification unit operatively coupled to the input matching unit, wherein the first amplification unit comprises a first field effect transistor (FET) configured to filter the first set of signals by removing noise of first predefined frequencies from the first set of signals, and amplify the filtered first set of signals to a first predefined level to generate a second set of signals; and
a second first amplification unit operatively coupled to the first amplification unit, wherein the second amplification unit comprises a second field effect transistor (FET) configured to filter the second set of signals by removing noise of second predefined frequencies from the second set of signals, and amplify the filtered second set of signals to a second predefined level to generate a set of output signals
wherein an inter-stage matching unit is configured between first amplification unit and the second amplification unit, to facilitate impedance matching between the first amplification unit and the second amplification unit
2. The amplifier as claimed in claim 1, wherein the amplifier comprises an output matching unit operatively coupled to the second amplification unit, and wherein the output matching unit comprises a first set of four cascaded capacitors of predefined capacitance.
3. The amplifier as claimed in claim 1, wherein the first FET and the second FET are a pseudomorphic high electron mobility transistor (pHEMT), and wherein the amplifier is fabricated on an Indium gallium Arsenide (InGaAs) substrate of predefined thickness.
4. The amplifier as claimed in claim 3, wherein the pHEMT of each of the first FET and the second FET is having a gate periphery of 300 micrometre.
5. The amplifier as claimed in claim 1, wherein the output power of the amplifier is controlled by changing gate bias of the second amplification stage by shorting the gate of the second FET to ground using a set of resistors.
6. The amplifier as claimed in claim 1, wherein the inter-stage matching unit comprises a third set of capacitors of a predefined capacitance, a second resistor of predefined resistance, and a second inductor of a predefined inductance, to facilitate impedance matching between the first amplification unit and the second amplification unit.
7. The amplifier as claimed in claim 1, wherein the amplifier is self-biased, and configured with a single power source.
8. The amplifier as claimed in claim 1, wherein the amplifier comprises an input port to enable the amplifier to receive the first set of signals form the source, and wherein the amplifier comprises an output port to enable the amplifier to transmit the set of output signals.
9. The amplifier as claimed in claim 8, wherein the amplifier comprises a second set of capacitors being configured at the input port and the output port to block DC signals.
10. The amplifier as claimed in claim 8, wherein the amplifier is configured to improve return losses at both the input port and the output port over a C band frequency range of 4-7 GHz.