HIGH SPEED, LOW POWER, LOW LEAKAGE READ ONLY MEMORY
Field of the Invention
The present invention relates to read only memories (ROMs), and more particularly to a novel ROM having a high operational speed with reduced leakage and low power consumption.
Background of the Invention
Semiconductor memory devices have undergone various design changes in terms of package density, operating speed, or power/current dissipation. Many devices, such as micro-processors, or other related devices include onboard memory which contains one or more read only memory (ROM) cells.
Read only memory (ROM) circuits are generally composed of memory elements disposed in rows or word lines and columns or bit lines. A particular word in memory is generally addressed by energizing the row or word line corresponding to the desired word while also energizing the columns of bit lines for all of the bits corresponding to the addressed word. The read only memory circuits (ROM) are widely used in Basic Input/Output System (BIOS) type of systems, where the code hard coded in it will be read at the start of some operation. After that it will just be a leaky component in a system. Hence. low-leakage and low-power consumption are major goals of a ROM designing.
There are schemes that can reduce static leakage and dynamic power consumption of bit lines like selectively pre-charge bit lines of a selected column. But the ROM memory cell being very dense still gives rise to cross talks, leakage of load transistors within same column, VDD noise to a sense amplifier, etc. These problems give rise to a limited operating speed with unbalanced latching problems. Since bit lines (BLs) are in close proximity, there is a heavy coupling between adjacent BLs. If a cell in an unseleeted
column is programmed as zero, it will couple to an adjacent BL. If this adjacent BL is needed to be kept high (for bit ' 1') and is to be sensed, then some margin has to be kept in an unbalanced sense amplifier. The leakage of load resistance is another concern for ROM as memory cells are of minimum length, and hence sub-threshold leakage and its deviation are very high.
Therefore, there arises a need for a novel read only memory (ROM), which can overcome above mentioned problems. The novel ROM improves operational speed in addition to power and leakage benefits.
Summary of the Invention
It is an object of the present invention to provide a read only memory (ROM) having a high operational speed with reduced leakage and low power consumption.
To achieve the aforementioned objectives, the present invention provides a read only memory (ROM) for providing a high operational speed with reduced leakage and low power consumption comprising:
a plurality of bit lines;
a plurality of word lines;
a plurality of column select lines; and
a plurality of transistors operatively coupled to said bit lines, said word lines and said column select lines, said transistors having a source terminal connected to a word line o\~ said word lines, a drain terminal connected to a bit line of said bit lines, a gate terminal connected to a column select line of said column select lines, such that said word line being connected to a ground voltage and said column select line being
connected to a supply voltage to provide the high operational speed with reduced leakage and low power consumption.
Further, the present invention provides a method for providing a read only memory (ROM) having a high operational speed with reduced leakage and low power consumption comprising the steps of:
arranging a plurality of bit lines, a plurality of word lines and a plurality of column select lines; and
coupling a plurality of transistors to said word lines, said bit lines and said column select lines in the ROM to reduce one or more of cross talks, power leakages and power consumption.
wherein a word line selected from the plurality of word lines being connected to a source of a transistor selected from the plurality of transistors, a bit line selected from the plurality of bit lines being connected to a drain of said transistor and a column select line selected from the plurality of column select lines being connected to a gate of said transistor, such that said word line being connected to a ground voltage and said column select line being connected to a supply voltage to provide the high operational speed with reduced leakage and low power consumption.
Brief Description of Drawings
FIGURE 1 illustrates a read only memory (ROM) according to the present invention.
FIGURE 2 illustrates a block diagram of a read only memory (ROM) according to an embodiment of the present invention.
FIGURE 3 illustrates a diagram of a memory cell block according to the present invention.
FIGURE 4 illustrates a flow diagram for a method for providing a read only memory (ROM) according to the present invention.
Detailed Description of the Invention
The preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the preferred embodiments. The present invention can be modified in various forms.The preferred embodiments of the present invention are only provided to explain more clearly the present invention to the ordinarily skilled in the art of the present invention. In the accompanying drawings, like reference numerals are used to indicate like components.
FIGURE 1 illustrates a read only memory (ROM) 100 having a high operational speed with reduced leakage and low power consumption according to the present invention. The ROM includes multiple bit lines (BLs), multiple word lines (WLs). multiple column select lines (Colsel) and multiple transistors. The transistors are operatively coupled to the bit lines, the word lines and the column select lines. A source terminal of the transistors is connected to a word line, a drain terminal is connected to a bit line and a gate terminal is connected to a column select line. In an embodiment of the present invention the transistors are metal oxide semiconductor (MOS) transistors.
The working of the ROM is such that the word line of a selected row is pulled down to a ground voltage (Vgnd). Non-selected word lines arc kept at a supply voltage VDD. This ensures that unwanted row.s will not have any sub-threshold current, as Vds = 0. So during read 1 (that is when BL is high) load cells would not leak unnecessarily. Hence the margin that had to be kept due to leakage and its variation is not required here.
Activating only a particular column by charging a selected column select line to the supply voltage VDD in order to enable a bit line BL to discharge through the ground created from a word line WL. Rest of the column select lines (i.e., gates of memory cells) are connected to a ground voltage GND. So the bit lines BLs in other columns, not intended to be read, would not discharge. This provides a selective reading of a column. This reduces load on the word line WL, as the word line WL does not have to discharge unwanted columns since memory cells in those columns are in an off state.
Adjacent bit lines BLs can be used as inputs to an unbalanced latch type sense amplifier. However, a switch has to be used to route the selected bit lines BLs on to a drain of a weaker NMOS of the unbalanced sense amplifier. This makes the unbalanced sense amplifier more noise immune as none of the two nodes of the sense amplifier are tied to the supply voltage VDD. These adjacent bit lines BLs can be referred to as a reference bit line BL_ref
However, use of the adjacent bit lines BLs in a ROM, where a word line WL is connected to gate terminals of all transistors in a row, is not feasible. This is because the discharging of a reference bit line BL depends on programming of a cell. But in the present invention, since the bit line BL in an adjacent column is from a set of the bit lines BLs of a multiplexer and unselected columns of the multiplexer have gates at the ground voltage GND, so an adjacent bit line BL does not discharge irrespective of its programming.
FIGURE 2 illustrates a block diagram 200 of a read only memory (ROM) according to an embodiment of the present invention. The block diagram 200 includes memory cells coupled to word lines, bit lines and column select lines. The column select lines are in Metal 3, but couple the bit lines BLs due to a gate-drain overlap capacitance. This can be avoided by swapping a bit line BL, that is being read, and the bit line BL used as a reference after half rows. In swapping operation, the bit line is provided as a read bit line for a first half row and a reference bit line for a second half row to reduce coupling and thereby, enhancing operational speed. The word line is provided at bottom during the first half row and the word line is provided at top during the second half row. The coupling is
reduced by 50% in the bit line BL being read, as well as increases potential of reference bit line BLref to that of bit line BL being read. Hence, imbalance between the selected bit line BL and a reference bit line BLref is eliminated. Since bit lines BLs are swapped after half rows, some logic has to be incorporated in input/output IO to check whether reading is done in an upper half of a core or in a lower half.
FIGURE 3 illustrates a diagram of a memory cell 300 according to the present invention. A memory cell 300 includes a transistor connected to a word line, a bit line and a column select line. A source terminal of the transistor is connected to a word line WL. a drain terminal is connected to a bit line BL and a gate terminal is connected to a column select line Colsel.
FIGURE 4 illustrates a flow diagram of a method for providing a read only memory (ROM) having a high operational speed with reduced leakage and low power consumption according to the present invention. At step 402, a plurality of bit lines, a plurality of word lines and a plurality of column select lines are arranged. At step 404. a plurality of transistors are coupled to the word lines, the bit lines and the column select lines in the ROM to reduce one or more of cross talks, power leakages and power consumption.
In addition to high operational speed, reduced leakage and low power consumption, the present invention offers several advantages. First, the present invention eliminates discharging of adjacent bit lines (BLs) as the adjacent bit lines (BLs) are not coupled. Second, the memory cells do not have sub-threshold current during read "1" operation. Hence, the sense amplifier need not have so much unbalance to take care of the subthreshold leakage and coupling. Third, power is saved as only the selected column select line is charged. As the unselected column select lines are grounded, they will not be discharged. Due to this, the strength requirement of transistor that sinks charge from BL will not be very high. Fourth, static leakage of the memory cell is negligible. Fifth, adjacent BL can be used as an input to an unbalanced sense amplifier.
Although the disclosure of circuit and method has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the disclosure.

We Claim:
1. A read only memory (ROM) for providing a high operational speed with reduced
leakage and low power consumption comprising:
a plurality of hit lines;
a plurality of word lines;
a plurality of column select lines; and
a plurality of transistors operatively coupled to said bit lines, said word lines and said column select lines, said transistors having a source terminal connected to a word line of said word lines, a drain terminal connected to a bit line of said bit lines, a gate terminal connected to a column select line of said column select lines, such that said word line being connected to a ground voltage and said column select line being connected to a supply voltage to provide the high operational speed with reduced leakage and low power consumption.
2. The ROM as claimed in claim I, wherein said plurality of transistors comprises a
metal oxide semiconductor (MOS) transistor.
3. The ROM as claimed in claim I, wherein said bit lines provided as read bit lines for a first half row and reference bit lines for a second half row to reduce coupling for enhancing said operational speed.
4. The ROM as claimed in claim 1, wherein said transistors comprising balancing cross talks between said bit line and said column select line.
5. A method for providing a read only memory (ROM) having a high operational speed with reduced leakage and low power consumption comprising the steps of:
arranging a plurality of bit lines, a plurality of word lines and a plurality of column select lines; and
coupling a plurality of transistors to said word lines, said bit lines and said column select lines in the ROM to reduce one or more of cross talks, power leakages and power consumption,
wherein a word line selected from the plurality of word lines being connected to a source of a transistor selected from the plurality of transistors, a bit line selected from the plurality of bit lines being connected to a drain of said transistor and a column select line selected from the plurality of column select lines being connected to a gate of said transistor, such that said word line being connected to a ground voltage and said column select line bejng connected to a supply voltage to provide the high operational speed with reduced leakage and low power consumption.
6. The method as claimed in claim 5, wherein said transistor comprises a MOS transistor.
7. A read only memory (ROM) for providing a high operational speed with reduced leakage and low power consumption substantially as herein described with reference to and as illustrated in the accompanying drawings
8. A method for providing a read only memory (ROM) having a high operational speed with reduced leakage and low power consumption substantially as herein described with reference to and as illustrated in the accompanying drawings