[0001] The present disclosure relates to the semiconductor elements and devices. More
particularly, the present disclosure relates to a semiconductor based pseudo-resistive element.
BACKGROUND
[0002] Background description includes information that may be useful in
understanding the present invention. It is not an admission that any of the information provided
herein is prior art or relevant to the presently claimed invention, or that any publication
specifically or implicitly referenced is prior art.
[0003] In biomedical applications like Neural signal recording, On-Chip BioImpedance Spectroscopy, Bio-signal recording, Cardiac Electrical Impedance tomography and
Scanning Ion-Conductance Microscopy etc. various analog circuits such as voltage amplifiers,
Trans conductance amplifiers, trans impedance amplifiers and filters etc. deploy pseudoresistors for implementing very large R-C time constant circuits so as to achieve very low cutoff frequencies. Moreover, Pseudo-resistors are being used in Current conveyors, Current
reference and Data converters for mimicking the behaviour of passive resistors.
[0004] Pseudo-resistors based on MOS devices capable of emulating high resistance
used in aforesaid applications suffer from non-linearity in V-I characteristic curves or
inconsistency in V-R characteristic curves owing to inherent non-linear MOS device
behaviour. This leads to degradation of the performance of analog circuits used in the
biomedical applications. Linearity over a wider voltage swing and enhanced performance
against Process Voltage and Temperature (PVT) variations is major challenge faced in
implementing Pseudo-resistors.
[0005] There is, therefore, a need in the art to provide an efficient, smart, and costeffective pseudo-resistive element to overcome the above-mentioned problems, and, provide a
reliable means for facilitating linear operations.
OBJECTS OF THE PRESENT DISCLOSURE
[0006] Some of the objects of the present disclosure, which at least one embodiment
herein satisfies are as listed herein below.
[0007] It is an object of the present disclosure to provide a pseudo-resistive element
providing linearity over V-I characteristic curves.
3
[0008] It is another object of the present disclosure to provide a pseudo-resistive
element providing consistency in V-R characteristic curves.
[0009] It is another object of the present disclosure to provide a pseudo-resistive
element facilitating linearity over a wider voltage swing.
[0010] It is another object of the present disclosure to provide a pseudo-resistive
element with enhanced performance against Process Voltage and Temperature (PVT)
variations.
[0011] It is another object of the present disclosure to provide an efficient and cost
effective pseudo-resistive element.
SUMMARY
[0012] The present disclosure relates to the semiconductor elements and devices. More
particularly, the present disclosure relates to a semiconductor based pseudo-resistive element.
[0013] An aspect of the present disclosure pertains to a pseudo-resistive element
comprising: a first Metal Oxide Semiconductor (MOS) transistor having a first body terminal,
a first gate terminal, a first source terminal, and a first drain terminal; and a second MOS
transistor having a second body terminal, a second gate terminal, a second source terminal, and
a second drain terminal, electronically coupled to the first MOS transistor, wherein the first
body terminal, the first source terminal, the second body terminal, and the second source
terminal being connected to an input terminal, the first drain terminal being connected to an
output terminal, the first gate terminal and the second gate terminal being connected to a first
node, and the second drain terminal being grounded, and a first voltage may be applied to the
input terminal, and a second voltage may be applied to the output terminal, and wherein
resistance of the element changes with a change in any or a combination of the first voltage
and the second voltage to provide a better voltage- current linearity.
[0014] In an aspect, the pseudo-resistive element comprises a third MOS transistor
having a third body terminal, a third gate terminal, a third source terminal, and a third drain
terminal, electronically coupled to the second MOS transistor such that the second drain
terminal, the third gate terminal and the third drain terminal may be connected to the first node,
and the third body terminal and the third source terminal may be grounded.
[0015] In an aspect, the pseudo-resistive element comprises a fourth MOS transistor
having a fourth body terminal, a fourth gate terminal, a fourth source terminal, and a fourth
drain terminal such that the third body terminal, the third source terminal, the fourth gate
4
terminal and the fourth drain terminal are connected to a second node, and the fourth body
terminal and the fourth source terminal are grounded.
[0016] In an aspect, the first MOS transistor may be operated in subthreshold region,
and the second MOS transistor, the third MOS transistor, and the fourth MOS transistor may
be operated in any or a combination of subthreshold region, linear region, and saturation region.
[0017] In an aspect, the pseudo-resistive element comprises any or a combination of
the first body terminal, the second body terminal, the third body terminal, and the fourth body
terminal being short-circuited with any or a combination of the first source terminal, the second
source terminal, the third source terminal, and the fourth source terminal, respectively.
[0018] In an aspect, the first MOS transistor, the second MOS transistor, the third MOS
transistor, and the fourth MOS transistor may be any or a combination of N-channel MOSFET,
P-channel MOSFET, and CMOS.
[0019] In an aspect, the first voltage and the second voltage may be supplied through
any or a combination of independent voltage source, current-controlled voltage source, and
voltage-controlled voltage source.
[0020] In an aspect, the pseudo-resistive element may provide a better voltage- current
linearity over a wide voltage swing.
[0021] In an aspect, the pseudo-resistive element may be adapted against Process
Voltage and Temperature (PVT) variations.
[0022] In an aspect, the pseudo-resistive element may be capable of emulating
Incremental Resistance (IR) of 1 TΩ.
[0023] In an aspect, the first body terminal, the second body terminal, the third body
terminal, and the fourth body terminal may be biased through any or a combination of a voltage
source, a current source, and a large valued self-current controlled resistor.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The accompanying drawings are included to provide a further understanding of
the present disclosure, and are incorporated in and constitute a part of this specification. The
drawings illustrate exemplary embodiments of the present disclosure and, together with the
description, serve to explain the principles of the present disclosure.
[0025] The diagrams are for illustration only, which thus is not a limitation of the
present disclosure, and wherein:
5
[0026] FIG. 1 illustrates exemplary block diagram of the proposed pseudo-resistive
element to illustrate its overall working in accordance with an embodiment of the present
disclosure.
[0027] FIGs. 2A-2C illustrate exemplary diagrams pertaining to biasing of pseudoresistive element, in accordance with an exemplary embodiment of the present disclosure.
[0028] FIGs. 3A-3B illustrate exemplary circuital diagrams, in accordance with an
embodiment of the present disclosure.
[0029] FIG. 4 illustrates exemplary circuit diagram of the proposed pseudo-resistive
element, in accordance with an embodiment of the present disclosure.
DETAILED DESCRIPTION
[0030] The following is a detailed description of embodiments of the disclosure
depicted in the accompanying drawings. The embodiments are in such detail as to clearly
communicate the disclosure. However, the amount of detail offered is not intended to limit the
anticipated variations of embodiments; on the contrary, the intention is to cover all
modifications, equivalents, and alternatives falling within the spirit and scope of the present
disclosure as defined by the appended claims.
[0031] Various terms as used herein are shown below. To the extent a term used in a
claim is not defined below, it should be given the broadest definition persons in the pertinent
art have given that term as reflected in printed publications and issued patents at the time of
filing.
[0032] In some embodiments, the numerical parameters set forth in the written
description and attached claims are approximations that can vary depending upon the desired
properties sought to be obtained by a particular embodiment. In some embodiments, the
numerical parameters should be construed in light of the number of reported significant digits
and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and
parameters setting forth the broad scope of some embodiments of the invention are
approximations, the numerical values set forth in the specific examples are reported as
precisely as practicable. The numerical values presented in some embodiments of the invention
may contain certain errors necessarily resulting from the standard deviation found in their
respective testing measurements.
[0033] As used in the description herein and throughout the claims that follow, the
meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates
6
otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on”
unless the context clearly dictates otherwise.
[0034] The recitation of ranges of values herein is merely intended to serve as a
shorthand method of referring individually to each separate value falling within the range.
Unless otherwise indicated herein, each individual value is incorporated into the specification
as if it were individually recited herein. All methods described herein can be performed in any
suitable order unless otherwise indicated herein or otherwise clearly contradicted by context.
The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect
to certain embodiments herein is intended merely to better illuminate the invention and does
not pose a limitation on the scope of the invention otherwise claimed. No language in the
specification should be construed as indicating any non-claimed element essential to the
practice of the invention.
[0035] Groupings of alternative elements or embodiments of the invention disclosed
herein are not to be construed as limitations. Each group member can be referred to and
claimed individually or in any combination with other members of the group or other elements
found herein. One or more members of a group can be included in, or deleted from, a group
for reasons of convenience and/or patentability. When any such inclusion or deletion occurs,
the specification is herein deemed to contain the group as modified thus fulfilling the written
description of all groups used in the appended claims.
[0036] The present disclosure relates to the semiconductor elements and devices. More
particularly, the present disclosure relates to a semiconductor based pseudo-resistive element.
[0037] According to an aspect the present disclosure pertains to a pseudo-resistive
element including: a first Metal Oxide Semiconductor (MOS) transistor having a first body
terminal, a first gate terminal, a first source terminal, and a first drain terminal; and a second
MOS transistor having a second body terminal, a second gate terminal, a second source
terminal, and a second drain terminal, electronically coupled to the first MOS transistor,
wherein the first body terminal, the first source terminal, the second body terminal, and the
second source terminal being connected to an input terminal, the first drain terminal being
connected to an output terminal, the first gate terminal and the second gate terminal being
connected to a first node, and the second drain terminal being grounded, and a first voltage can
be applied to the input terminal, and a second voltage can be applied to the output terminal,
and wherein resistance of the element changes with a change in any or a combination of the
first voltage and the second voltage to provide a better voltage- current linearity.
7
[0038] In an embodiment, the pseudo-resistive element can be including a third MOS
transistor having a third body terminal, a third gate terminal, a third source terminal, and a third
drain terminal, electronically coupled to the second MOS transistor such that the second drain
terminal, the third gate terminal and the third drain terminal can be connected to the first node,
and the third body terminal and the third source terminal can be grounded.
[0039] In an embodiment, the pseudo-resistive element can be including a fourth MOS
transistor having a fourth body terminal, a fourth gate terminal, a fourth source terminal, and a
fourth drain terminal such that the third body terminal, the third source terminal, the fourth gate
terminal and the fourth drain terminal are connected to a second node, and the fourth body
terminal and the fourth source terminal are grounded.
[0040] In an embodiment, the first MOS transistor can be operated in subthreshold
region, and the second MOS transistor, the third MOS transistor, and the fourth MOS transistor
can be operated in any or a combination of subthreshold region, linear region, and saturation
region.
[0041] In an embodiment, the pseudo-resistive element can be including any or a
combination of the first body terminal, the second body terminal, the third body terminal, and
the fourth body terminal being short-circuited with any or a combination of the first source
terminal, the second source terminal, the third source terminal, and the fourth source terminal,
respectively.
[0042] In an embodiment, the first MOS transistor, the second MOS transistor, the third
MOS transistor, and the fourth MOS transistor can be any or a combination of N-channel
MOSFET, P-channel MOSFET, and CMOS.
[0043] In an embodiment, the first voltage and the second voltage can be supplied
through any or a combination of independent voltage source, current-controlled voltage source,
and voltage-controlled voltage source.
[0044] In an embodiment, the pseudo-resistive element can provide a better voltagecurrent linearity over a wide voltage swing.
[0045] In an embodiment, the pseudo-resistive element can be adapted against Process
Voltage and Temperature (PVT) variations.
[0046] In an embodiment, the pseudo-resistive element can be capable of emulating
Incremental Resistance (IR) of 1 TΩ.
[0047] In an embodiment, the first body terminal, the second body terminal, the third
body terminal, and the fourth body terminal can be biased through any or a combination of a
voltage source, a current source, and a large valued self-current controlled resistor.
8
[0048] FIG. 1 illustrates exemplary block diagram of the proposed pseudo-resistive
element 100 to illustrate its overall working in accordance with an embodiment of the present
disclosure.
[0049] In an embodiment, as illustrated in FIG. 1, the proposed pseudo-resistive
element 100 can include one or more Metal Oxide Semiconductor (also, referred to as MOS,
herein) transistors (not shown). Each of the one or more MOS transistors can be having four
terminals, i.e., a body terminal 102 (also, referred to as bulk terminal 102, herein), a gate
terminal 104, a source terminal 106, and a drain terminal 108, where each of the terminals can
be distinct from other. In an illustrative embodiment, each of the one or more MOS transistors
can be identical to each other. In another illustrative embodiment, each of the one or more MOS
transistors can be identical to each other.
[0050] In an illustrative embodiment, a pre-defined drain voltage, VD, can be applied
to the drain terminal 108 of at least one of the one or more MOS transistors, bulk voltage, VBulk,
can be applied to the bulk terminal 102 of at least one of the one or more MOS transistors,
source voltage, VS, can be applied to the source terminal 106 of at least one of the one or more
MOS transistors, and gate voltage, VG, can be applied to the gate terminal 104 of at least one
of the one or more MOS transistors to enable the proposed pseudo-resistive element 100 to
operate efficiently. In another illustrative embodiment, a pre-defined biasing voltage, VBIAS,
can be applied to the gate terminal 104 of at least one of the one or more MOS transistors to
enable the proposed pseudo-resistive element 100 to operate efficiently.
[0051] FIGs. 2A-2C illustrate exemplary diagrams pertaining to biasing of pseudoresistive element, in accordance with an exemplary embodiment of the present disclosure.
[0052] In an embodiment, as illustrated in FIG. 2A, direct bulk biasing of the proposed
pseudo-resistive element 100 can be done by applying bulk voltage, VBulk, directly to the bulk
terminal of at least one of the one or more MOS transistors, M1, whereas, a biasing voltage,
VBIAS, can be applied to the gate terminal of said MOS transistor M1 of the proposed pseudoresistive element 100. In an embodiment, the MOS transistor M1 can be operated in
subthreshold region.
[0053] In an embodiment, as illustrated in FIG. 2B, bulk biasing through VBIAS of the
proposed pseudo-resistive element 100 can be done by applying a biasing voltage, VBIAS, to the
bulk terminal and the gate terminal of said MOS transistor M1 of the proposed pseudo-resistive
element 100.
[0054] In an embodiment, bulk biasing through a resistor R of the proposed pseudoresistive element 100 can be done as illustrated in FIG. 2C.
9
[0055] FIGs. 3A-3B illustrate exemplary circuital diagrams, in accordance with an
embodiment of the present disclosure.
[0056] In an embodiment, as illustrated in FIGs. 3A-3B, a MOS transistor can be
implemented as a capacitor by short-circuiting one or more terminals of said MOS transistor.
[0057] In an illustrative embodiment, a MOS transistor M2, of a first predefined rating,
can be configured to provide a capacitance of αC. In another illustrative embodiment, a MOS
transistor M3, of a second predefined rating, can be configured to provide a capacitance of (1-
α) C.
[0058] FIG. 4 illustrates exemplary circuit diagram of the proposed pseudo-resistive
element, in accordance with an embodiment of the present disclosure.
[0059] In an embodiment, as illustrated in FIG. 4, the proposed pseudo-resistive
element 100 can include MOS transistors M4, M5, M6, and M7, which can be configured with
each other in a pre-determined way.
[0060] In an embodiment, body terminal and source terminal of the MOS transistor
M4, and body terminal and source terminal of the MOS transistor M5 can be connected to an
input terminal, and a first voltage can be applied to the input terminal, wherein the first voltage
can be VBIAS.
[0061] In an embodiment, drain terminal of the MOS transistor M4 can be connected
to an output terminal, and a second voltage VG can be applied to the output terminal. In an
embodiment, gate terminals of the MOS transistors M4 and M5 can be connected to a first node
N1.
[0062] In an embodiment, the MOS transistor M6 can be electronically coupled to the
MOS transistor M5 such that drain terminal of the MOS transistor M5 can be connected to gate
terminal and drain terminal of the MOS transistor M6 through the first node N1.
[0063] In an embodiment, the MOS transistor M7 can be coupled to the MOS transistor
M6 such that body terminal and source terminal of the MOS transistor M6 can be connected to
gate terminal and drain terminal of the MOS transistor M7 through a third node, and body
terminal and source terminal of the MOS transistor M7 can be grounded.
[0064] In an embodiment, the MOS transistor M4 is operated in subthreshold region,
whereas the MOS transistors M5, M6, and M7 can be operated in any or a combination of
subthreshold region, linear region, and saturation region.
[0065] In an embodiment, a MOS transistor is said to be operating in the subthreshold
region (also, referred to as cut-off region, herein) when gate-to-source voltage (VGS) of said
10
MOS transistor is less than threshold voltage (also, referred to as Vth, herein). Thus, for said
MOS transistor to be in cut-off region, the necessary condition is –
0< VGS < Vth - for NMOS
0 > VGS > Vth - for PMOS (as threshold voltage of PMOS is negative)
[0066] In an embodiment, in subthreshold region, magnitude of current flowing
through MOS transistor is negligible as no channel is present. The conduction happening in
said region is known as sub-threshold conduction.
[0067] In an embodiment, in linear region, for an NMOS transistor, as gate voltage
increases beyond threshold voltage, a channel is formed between the source and drain
terminals. Now, if there is a voltage difference between the source and drain terminals, the
current can flow. The magnitude of the current increases linearly with increasing drain voltage
till a particular drain voltage determined by the following relations –
VGS ≥ Vth
VDS < VGS – Vth
The current is, then, can be represented as a linear function of gate-to-source and drain-tosource voltages. That is why, the MOS transistor is said to be operating in linear region.
[0068] Similarly, for P-MOS transistor, condition for P-MOS to be in linear region is
represented byVGS < Vth OR VSG > |Vth|, and
VDS > VGS + Vth; or VSD < VSG - |Vth|
[0069] In an embodiment, in saturation region, for an NMOS transistor, at a particular
gate and source voltage, there is a particular level of voltage for drain, beyond which, increasing
drain voltage seems to have no effect on current. When a MOS transistor operates in the region,
it is said to be in saturation. The condition is given as:
VGS ≥ Vth
VDS > VGS – Vth
[0070] In an embodiment, said arrangement of the MOS transistors can result in highly
linear change of resistance of the proposed pseudo-resistive element 100 with a change in any
or a combination of the first voltage and the second voltage to provide a better voltage- current
linearity.
[0071] In an embodiment, the MOS transistors can be any or a combination of Nchannel MOSFET, P-channel MOSFET, CMOS, and the likes.
[0072] In an embodiment, said arrangement of the MOS transistors can be represented
by an equivalent circuit, which can be including a pre-defined resistance ‘R’, and, hence, can
11
facilitate linear V-I characteristics. In an illustrative embodiment, a pre-defined biasing
voltage, VBIAS, can be applied on at least one of the terminals of the equivalent circuit of the
proposed pseudo-resistive element, and a pre-defined voltage, VG, can be applied at other
terminal of the equivalent circuit.
[0073] Thus, it will be appreciated by those of ordinary skill in the art that the diagrams,
schematics, illustrations, and the like represent conceptual views or processes illustrating
systems and methods embodying this invention. Those of ordinary skill in the art further
understand that the exemplary hardware, software, processes, methods, and/or operating
systems described herein are for illustrative purposes and, thus, are not intended to be limited
to any particular named.
[0074] While embodiments of the present invention have been illustrated and
described, it will be clear that the invention is not limited to these embodiments only. Numerous
modifications, changes, variations, substitutions, and equivalents will be apparent to those
skilled in the art, without departing from the spirit and scope of the invention, as described in
the claim.
[0075] In the foregoing description, numerous details are set forth. It will be apparent,
however, to one of ordinary skill in the art having the benefit of this disclosure, that the present
invention may be practiced without these specific details. In some instances, well-known
structures and devices are shown in block diagram form, rather than in detail, to avoid
obscuring the present invention.
[0076] As used herein, and unless the context dictates otherwise, the term "coupled to"
is intended to include both direct coupling (in which two elements that are coupled to each
other contact each other)and indirect coupling (in which at least one additional element is
located between the two elements). Therefore, the terms "coupled to" and "coupled with" are
used synonymously. Within the context of this document terms "coupled to" and "coupled
with" are also used euphemistically to mean “communicatively coupled with” over a network,
where two or more devices are able to exchange data with each other over the network, possibly
via one or more intermediary device.
[0077] It should be apparent to those skilled in the art that many more modifications
besides those already described are possible without departing from the inventive concepts
herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the
appended claims. Moreover, in interpreting both the specification and the claims, all terms
should be interpreted in the broadest possible manner consistent with the context. In particular,
the terms “comprises” and “comprising” should be interpreted as referring to elements,
12
components, or steps in a non-exclusive manner, indicating that the referenced elements,
components, or steps may be present, or utilized, or combined with other elements,
components, or steps that are not expressly referenced.
[0078] While the foregoing describes various embodiments of the invention, other and
further embodiments of the invention may be devised without departing from the basic scope
thereof. The scope of the invention is determined by the claims that follow. The invention is
not limited to the described embodiments, versions or examples, which are included to enable
a person having ordinary skill in the art to make and use the invention when combined with
information and knowledge available to the person having ordinary skill in the art.
ADVANTAGES OF THE PRESENT DISCLOSURE
[0079] The present disclosure provides a pseudo-resistive element providing linearity
over V-I characteristic curves.
[0080] The present disclosure provides a pseudo-resistive element providing
consistency in V-R characteristic curves.
[0081] The present disclosure provides a pseudo-resistive element facilitating linearity
over a wider voltage swing.
[0082] The present disclosure provides a pseudo-resistive element with enhanced
performance against Process Voltage and Temperature (PVT) variations.
[0083] The present disclosure provides an efficient and cost effective pseudo-resistive
element.

We Claim:

1. A pseudo-resistive element comprising:
a first Metal Oxide Semiconductor (MOS) transistor having a first body terminal, a first
gate terminal, a first source terminal, and a first drain terminal; and
a second MOS transistor having a second body terminal, a second gate terminal, a
second source terminal, and a second drain terminal, electronically coupled to the first
MOS transistor,
wherein the first body terminal, the first source terminal, the second body terminal,
and the second source terminal being connected to an input terminal, the first drain
terminal being connected to an output terminal, the first gate terminal and the second
gate terminal being connected to a first node, and the second drain terminal being
grounded, and a first voltage is applied to the input terminal, and a second voltage is
applied to the output terminal, and
wherein resistance of the element changes with a change in any or a combination of
the first voltage and the second voltage to provide a better voltage- current linearity.
2. The pseudo-resistive element as claimed in claim 1, wherein the pseudo-resistive
element comprises a third MOS transistor having a third body terminal, a third gate
terminal, a third source terminal, and a third drain terminal, electronically coupled to
the second MOS transistor such that the second drain terminal, the third gate terminal
and the third drain terminal are connected to the first node, and the third body terminal
and the third source terminal are grounded.
3. The pseudo-resistive element as claimed in claim 2, wherein the pseudo-resistive
element comprises a fourth MOS transistor having a fourth body terminal, a fourth gate
terminal, a fourth source terminal, and a fourth drain terminal such that the third body
terminal, the third source terminal, the fourth gate terminal and the fourth drain terminal
are connected to a second node, and the fourth body terminal and the fourth source
terminal are grounded.
4. The pseudo-resistive element as claimed in claim 2, wherein the first MOS transistor is
operated in subthreshold region, and wherein the second MOS transistor, the third MOS
transistor, and the fourth MOS transistor are operated in any or a combination of
subthreshold region, linear region, and saturation region.
5. The pseudo-resistive element as claimed in claim 2, wherein the pseudo-resistive
element comprises any or a combination of the first body terminal, the second body
14
terminal, the third body terminal, and the fourth body terminal being short-circuited
with any or a combination of the first source terminal, the second source terminal, the
third source terminal, and the fourth source terminal, respectively.
6. The pseudo-resistive element as claimed in claim 2, wherein the first MOS transistor,
the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are
any or a combination of N-channel MOSFET, P-channel MOSFET, and CMOS.
7. The pseudo-resistive element as claimed in claim 1, wherein the first voltage and the
second voltage are supplied through any or a combination of independent voltage
source, current-controlled voltage source, and voltage-controlled voltage source.
8. The pseudo-resistive element as claimed in claim 1, wherein the pseudo-resistive
element provides a better voltage- current linearity over a wide voltage swing, and is
adapted against Process Voltage and Temperature (PVT) variations.
9. The pseudo-resistive element as claimed in claim 1, wherein the pseudo-resistive
element is capable of emulating Incremental Resistance (IR) of 1 TΩ.
10. The pseudo-resistive element as claimed in claim 1, wherein the first body terminal, the
second body terminal, the third body terminal, and the fourth body terminal can be
biased through any or a combination of a voltage source, a current source, and a large
valued self-current controlled resistor.