DIFFERENTIAL INPUT RECEIVER WITH HYSTERESIS
Field of the Invention
The invention relates to an improved differential input receiver with hysteresis.
Background of the Invention
Differential signaling techniques are also known as balanced input signaling techniques. Balanced signaling techniques have distinct advantages in providing immunity to noise pickup and crosstalk between channels. These techniques are often employed for preventing false output owing to noise or interference pickup at the input. For applications where the switching speed is high the probability of noise influence is greater and hysteresis becomes essential for proper operation.
The Figure 1 shows a conventional differential signal receiver 1 without any hysteresis. The receiver consists of a current mirror biasing circuit formed by MOS transistors P1, Nl and P2. PMOS transistors P3 and P4 are the input transistors whose gates are connected to input voltage IN and reference voltage VREF respectively. NMOS transistors N2 and N3 are the current mirror load transistors.
The source of biasing PMOS transistor P1 is connected to VDD while its gate and drain are connected together and to the gate of PMOS transistor P2 and drain of NMOS transistor Nl. The gate and drain of NMOS transistor Nl are connected together while its source is connected to ground. Since the drain and gate of transistors P1 and Nl are shorted, these transistors always remain in saturation. The source of PMOS transistor P2 is connected to VDD while its drain is connected to the sources of input PMOS transistors P3 and P4. The drains of PMOS transistors P3 and P4 are connected to the drains of NMOS transistors N2 and N3 respectively. The gates of NMOS transistors N2 and N3 are connected together and to the drain of NMOS transistor N2 while their sources are connected to ground.
The current mirror circuit provides a constant current through the receiver. When the input voltage IN is less than the reference voltage VREF, the resistance of PMOS transistor P3 become less than that of PMOS transistor P4. Therefore the current in the input transistor branch which consists of transistors P3 and N2, increases while the current in the reference voltage transistor branch consisting of transistors P4 and N3 decreases by an equal amount.
This makes output voltage VOUTprior LOW. Similarly, when input voltage IN is greater than the reference voltage VREF, the current in the P4 - N3 transistor branch decreases while that in the P3 - N2 transistor branch increases by the same amount and output voltage VOUTprior goes HIGH. In this manner, the differential input receiver functions as a comparator whose trip point is set at the reference voltage VREF.
This type of differential input receiver is however susceptible to noise when the input voltage is close to the trip point of the differential input receiver. The influence of the noise can be seen in figures 2, which shows the waveforms for a conventional differential receiver. As shown, the noise results in large false spikes.
The effect of noise in the circuit results in incorrect functioning of the circuit.
Figure 3 shows waveforms comparing a differential receiver without hysteresis with a differential input receiver having hysteresis. As shown, whenever the input crosses the reference voltage (here 0.75V), the output of a differential receiver without hysteresis the circuit V(OUT)_prior switches, whereas the output of a differential receiver with hysteresis V(OUT) goes HIGH only when input goes beyond VTH (here 0.84V) and remains HIGH till the input signal IN goes lower than VTL (here 0.66V) thereby providing a greater noise immunity.
Hysteresis enables suppression of the effect of noise by adjusting the threshold voltage on the basis of the output voltage, setting a higher threshold voltage VTH or a lower threshold voltage VTL as shown in figure 4. The higher threshold voltage VTH is the threshold value when the output is low while the lower threshold voltage VTL is the threshold value when the output is high. This arrangement ensures that the output goes low only when the input becomes greater than VTH, and will go high only when the input drops below the lower threshold VTL. This provides an input noise margin of (VTH-VTL).
U.S. Patent 5,796,281 describes a differential input receiver with hysteresis as shown in figure 5. PMOS transistor Q2 is connected in parallel with reference voltage transistors Ql to provide hysteresis. The input to this parallel transistor is the output of the input stage Vout. Since the output of the input buffer is never at a strong logic low, significant hysteresis is
only possible with a large size of parallel transistor. Furthermore, this circuit provides hysteresis only in one direction.
United States Patent 5,666,068 describes a differential input receiver with hysteresis as shown in figure 6. In this circuit parallel transistors P8 and P9 are used to provide hysteresis. The inputs to these transistors VIN1 and VIN2 is the input signal itself, since this signal level is small here too transistors P8 and P9 are required to be large in size to provide adequate hysteresis. In addition, this arrangement reduces the input impedance of the receiver.
Object and Summary of the Invention
The object of the invention is to provide a differential input receiver with hysteresis to achieve higher immunity to noise occurring at the input or in reference voltage for improved performance.
The second object of the invention is to provide a differential input receiver with high common mode rejection ratio by providing symmetrical input configurations with high impedances.
Another object of the invention is to provide a differential input receiver with hysteresis, using small size of transistors.
Yet another object of the invention is to provide a differential input receiver with hysteresis characteristics that are symmetric about the reference voltage inorder to achieve better noise immunity at both low to high and high to low transitions.
To achieve the said objectives this invention provides an improved differential receiver providing symmetrical hysteresis, using only small size transistors, comprising:
a 2-input, 1-output differential amplifier consisting of 2 input transistors
having a common terminal coupled together with the control terminal of each
transistor connected to one input of the differential amplifier,
the output of the differential amplifier being connected to a set of cascaded
digital inverters/buffers, and
the output of each digital buffer being coupled to the control terminal of a
feedback transistor connected in parallel across each of the input transistors
such that when one input voltage increases above or decreases below the input voltage at the second input by a defined threshold value the feedback transistors operate to provide positive feedback to facilitate a rapid switching action at the output.
One input terminal is connected to a reference voltage while the second input receives the input voltage, thereby forming a comparator with hysteresis.
The invention further provides a method of improving a differential receiver comprising the
steps of:
providing a 2-input, 1-output differential amplifier consisting of 2 input transistors having a common terminal coupled together with the control terminal of each transistor connected to one input of the differential amplifier, connecting the output of the differential amplifier to a set of cascaded digital inverters/buffers, and
coupling the output of each digital buffer to the control terminal of a feedback transistor connected in parallel across each of the input transistors such that when one input voltage increases above or decreases below the input voltage at the second input by a defined threshold value the feedback transistors operate to provide positive feedback to facilitate a rapid switching action at the output.
Brief Description of the Drawings
The invention will now be described with reference to the following drawings:
Figure 1 shows a schematic diagram of a conventional PMOS differential input
receiver.
Figure 2 shows waveforms showing the effect of noise occurring at reference voltage node VREF.
Figure 3 shows waveforms showing the effect of noise occurring at input-voltage IN
for a differential input receiver with hysteresis.
Figure 4 shows the dc characteristics of a differential receiver with hysteresis.
Figure 5 shows a schematic diagram of a differential input receiver in accordance with
the prior art of United States patent 5,796,281.
Figure 6 shows a schematic diagram of a differential input receiver according to United
States patent 5,666,068.
Figure 7 shows a schematic diagram of the preferred embodiment of the differential input receiver in accordance with the present invention.
Detailed Description
Figures 1 to 6 have already been described in the background to the invention.
Figure 7 shows a differential input receiver according to the present invention. The receiver consists of pass transistors P20, N20 and P21 forming the current mirror circuit. MOS transistors P20 and N20 together act as a potential divider that controls the voltage at node Nl, and thereby the current flowing through transistor P21 and the rest of the circuit. The invention provides a symmetrical input-voltage transistor branch consisting of transistors P22, P24 and N21 and the reference-voltage transistor branch consisting of transistor P23, P25 and N22. The sources of MOS transistors P20 and N20 are connected to VDD and ground respectively while the gates of the MOS transistors N20 and P20 are connected to the drains of the same transistors. The source of the PMOS transistor P21 is connected to the supply voltage VDD while its drain is connected to the sources of PMOS transistors P22, P23, P24 and P25. PMOS transistors P22 and P23 are the input-voltage transistor and reference-voltage transistor, with their gates connected to input voltage signal IN and reference voltage VREF respectively. The drains of PMOS transistors P22 and P23 are connected to the drains of NMOS transistors N21 and N22. PMOS transistors P24 and P22 and PMOS transistors P25 and P23 are connected in parallel. The gates of PMOS transistors P24 and P25 are connected to the output of inverters 120 and 121 respectively. NMOS transistor N21 has its drain and gate shorted and connected to the gate of NMOS transistor N22. NMOS transistors N21 and N22 have their source connected to the ground. The input terminal of inverter DO is connected to the drains of MOS transistors P23, P25 and N22
which is the output node OUT and output node X of inverter 120 is connected to the input of inverter 121.
The operation of the circuit is analysed for two cases, a low to high transition and a high to low transition.
CASE 1: LOW to HIGH transition
In this case the voltage at IN is initially considered less then reference voltage VREF. Output voltage OUT is LOW and node X is at HIGH while node Y is LOW, consequently the PMOS transistors P24 and P25 are ON and OFF respectively. Since the voltage at IN is less than the reference voltage VREF, the resistance of transistor P22 is less than the resistance of transistor P23. Further, since transistor P25 is OFF and transistor P24 is ON the effective resistance of transistors P22 and P24 is smaller than the effective resistance of P23 and P25, resulting in a higher current in the input voltage-transistor branch than the current in reference-voltage transistor branch. When the input voltage IN increases to the reference voltage VREF, the resistance of transistor P22 increases and becomes equal to the resistance of reference-voltage transistor P23. Since node Y is LOW, transistor P24 is ON, resulting in the effective resistance of the transistors P22 and P24 becoming less than the resistance of transistors P23 and P25. Thus the current in the input voltage transistor branch remains greater than that in reference voltage transistor branch keeping the output node OUT at LOW, X at high and Y at low.
Further increase in the input voltage IN increases the resistance of input-voltage transistor branch until it is equal to the resistance of the reference-voltage transistor branch, resulting in an equal current through both the branches. Any increase in the input-voltage IN beyond this causes a higher current in reference- voltage branch than the current in the input-voltage branch turning output voltage OUT HIGH and nodes X, Y to low and high respectively, switching transistor P25 ON and transistor P24 OFF, which further increases the current in the reference voltage transistor branch. Hence the output goes HIGH at a value VTH which is greater than VREF. So a hysteresis of VTH-VREF is achieved in LOW to HIGH transition.
CASE 2: HIGH to LOW transition
In this case the input voltage IN is initially greater then the reference voltage VREF, the output voltage OUT is HIGH, hence node X is LOW and Y is HIGH. Consequently PMOS transistor P25 is ON and P24 is OFF resulting in a higher effective resistance of PMOS transistors P22 and P24 than PMOS transistors P23 and P25 and a greater current in the reference-voltage transistor branch compared to the current in the input-voltage transistor branch. When the input voltage IN decreases to VREF, the resistance of MOS transistor P22 becomes equal to the resistance of P23. Since PMOS transistor P25 is ON and PMOS transistor P24 is OFF, the effective resistance of MOS transistors P22 and P24 is still higher than the effective resistance of the PMOS transistors P23 and P25 keeping the current in reference-voltage transistor branch higher than the current in input voltage transistor branch and the output voltage OUT at logic HIGH.
Further decrease in input voltage IN decreases the resistance of PMOS transistor P22 equalizing the effective resistance of input-voltage branch and reference voltage branch resulting in a equal amount of current through both the branches. A decrease in input voltage IN beyond this leads to a higher effective resistance of PMOS transistor pair P23 and P25 than the effective resistance of PMOS transistors pairs P22 and P24, resulting in greater current through input-voltage transistor branch compared to the current through the reference-voltage transistor branch bringing the output LOW. Since node X is HIGH and node Y is LOW, transistor P24 is switched ON whereas transistor P25 is switched OFF which further reduces the effective resistance of P22 and P24 and increases the current in input-voltage transistor branch. This brings the output LOW when the input voltage IN is at threshold voltage VTL which is less than VREF thereby achieving a hysteresis value of VREF-VTL for a HIGH to LOW transition.
The value of hysteresis VTH-VTL can be increased or decreased by adjusting the size of MOS transistors P24 and P25 while the transition times can be changed by varying the sizes of inverters 121 and 122. Inverters 120 and 121 also improve the output swing providing rail-to-rail output. The gates of the parallel transistors P24 and P25 are connected to the outputs of inverters 120 and 121, providing a wide hysteresis using relatively smaller sizes of transistors.

We claim:
1. An improved differential receiver providing symmetrical hysteresis, using only small
size transistors, comprising:
a 2-input, 1-output differential amplifier consisting of 2 input transistors
having a common terminal coupled together with the control terminal of each
transistor connected to one input of the differential amplifier,
the output of the differential amplifier being connected to a set of cascaded
digital inverters/buffers, and
the output of each digital buffer being coupled to the control terminal of a
feedback transistor connected in parallel across each of the input transistors
such that when one input voltage increases above or decreases below the input
voltage at the second input by a defined threshold value the feedback
transistors operate to provide positive feedback to facilitate a rapid switching
action at the output.
2. An improved differential receiver as claimed in claim 1 wherein one input terminal is connected to a reference voltage while the second input receives the input voltage, thereby forming a comparator with hysteresis.
3. A method for improving a differential receiver comprising the steps of:
providing a 2-input, 1-output differential amplifier consisting of 2 input transistors having a common terminal coupled together with the control terminal of each transistor connected to one input of the differential amplifier, connecting the output of the differential amplifier to a set of cascaded digital inverters/buffers, and
coupling the output of each digital buffer to the control terminal of a feedback transistor connected in parallel across each of the input transistors such that when one input voltage increases above or decreases below the input voltage at the second input by a defined threshold value the feedback transistors operate to provide positive feedback to facilitate a rapid switching action at the output.
4. An improved differential receiver providing symmetrical hysteresis, using only small size transistors substantially as herein described with reference to and as illustrated in the accompanying drawings
5. A method for improving a differential receiver substantially as herein described with reference to and as illustrated in the accompanying drawings