IMPROVED RESOLUTION IN MEASURING THE PULSE WIDTH OF
DIGITAL SIGNALS
Field of the Invention
The present invention relates to a method and system for providing improved resolution in measuring the pulse width of digital signals. This invention can be used for On-Chip Pulse measurement and Pulse to Digital conversion.
Background of the Invention
Pulse width measurements are an essential requirement in characterising digital circuits. With the advancements in technology digital circuits are becoming increasingly faster and such measurements are becoming increasingly challenging. In particular, pulse width measurements of high speed digital circuits embedded in integrated circuits is extremely difficult and error-prone as the internal timings are significantly smaller than the signal delays from chip IO pads to external measuring instruments. The IO pads themselves contain buffering circuitry that adds considerable delay and that is incapable of operating at the high speeds of the internal circuitry. If Fax is the maximum operating frequency of the IO then the pulse of width more or equal to l/(2*Fmax.) can only be measured by this method.
For this reason, pulse width measurement circuits need to be integrated with the remaining circuitry of the device.
Existing designs of on-chip and off-chip pulse measurement circuitry utilise a high speed clock as a timebase fed to a counter gated by the pulse width to be measured. Such designs are limited in resolution to the time period of the timebase clock.
The objects and summary of the present invention
The object of the present invention is to provide a method and system for providing improved resolution in measuring of width of a digital pulse signals, more particularly on-chip pulse characterisation.
To achieve the said objective, this invention provides a method for providing improved resolution in the measuring of the pulse width of a digital signals, comprising the steps of:
counting the integral number of measuring clock pulses covered by
said digital pulse,
triggering a chain of cascaded high resolution delay elements from
the trailing edge of said measuring clock pulses.
measuring the delay count obtained from said chain of cascaded
delay elements from the trailing edge of the last measuring clock
pulse upto the end of said digital pulse, and
adding said measured delay count to said integral measuring clock
pulse count to obtain the total width of said digital pulse.
The number of cascaded minimum delay elements is such that the cumulative delay of said chain of delay elements is slightly greater than the time period of the measuring clock.
The said chain of cascaded minimum delay elements is triggered by both the leading and trailing edges of said measuring clock pulse so that the required number of delay elements is reduced to half.
The count value is converted to a compressed digital form.
The above method is applied to measurement of on chip pulse widths thereby overcoming 1O pad speed limitations of off-chip measurement techniques.
The instant invention further provides a system for providing improved resolution in measurement of pulse width of a digital signals, comprising
means for counting the integral number of measuring clock pulses
covered by said digital pulse,
means for triggering a chain of cascaded minimum delay elements
from the trailing edge of said measuring clock pulses,
means for measuring the delay count obtained from said chain of
cascaded delay elements from the trailing edge of the last measuring
clock pulse upto the end of said digital pulse, and
means for adding said measured delay count to said integral
measuring clock pulse count to obtain the total width of said digital
pulse.
The said delay elements are digital inverters.
The said measuring clock pulses are generated by any known oscillator.
The said count value is connected to a compressed digital form.
The number of said delay elements is such that the cumulative delay is slightly greater than the time period of the measuring clock.
The said chain of cascaded minimum delay elements is triggered by both the leading and trailing edges of said measuring clock pulse so that the required number of delay elements is reduced to half.
The said system is applied to on-chip pulse width measurements thereby overcoming the IO pad speed limitations of off-chip measurement techniques.
Brief Description for the accompanying Drawings:
The invention will now be described with reference to the accompanying drawings.
Fig. 1 shows the pulse width measurement, according to prior art.
Fig. 2 shows the pulse width measurement according to the invention
Fig. 3 shows the data flow in the inverter chain
Fig. 4 shows the method to reduce the chain length
Fig. 5 shows the block diagram of the invention
Fig. 6 shows the simulation results of the RING Oscillator.
Fig. 7 shows the simulation results of main scale counter.
Fig. 8 shows secondary scale block diagram
Detailed description:
Figure 1 shows the pulse width measurement system of the prior art. Timebase signal 'clock' is counted for the duration of the pulse to be measurement. The measurement resolution us the 'clock' period.
If the frequency of the high frequency clock is Fclk and Counter Count is N. Then the pulse width can be given as ~= (l/Fclk)*N .The value of pulse Width given above is inaccurate as the accuracy is ± (1/Fclk).
in tne example shown, the system will measure the pulse width till count 4 and as the pulse to be measured is falling before 5th clock pulse hence that much is the error in the measurement.
Figure 2 shows the improvement introduced by this invention. The system calculates the time for which the input PULSE has travelled before the next clock. This is done by using a cascaded inverter chain, which is the smallest delay element that can be used.
The error introduced in measuring the PULSE width is reduced to 1 inverter delay after this step. After doing the calculation in two steps the pulse width can be mathematically represented as
Pulse width = (l/Fc!k)*Nl + Tiv*N2 Where Fclk = Counter clock frequency Nl = Counter Count Tiv = 1 inverter delay N2 = No. of inverters till which pulse has travelled
To meet the measurement requirement, the Inverter chain length should be greater than the Fclk (counter clock) clock period, i.e. No. of Inverters Needed = [ (1/Fclk) + t ] / Tinv Where Fclk : Operating frequency Tinv = delay of inverter used
t. = Margin kept in the system after spice simulations and Clock jitter analyses, to ensure that the pulse to be measured do not cross the chain else this can result in error of - 1 clock period.
To trace the point till which the Pulse has reached in the inverter chain. At the output of all the inverters, latch is connected which can be controlled by the Pulse. Pulse rising enables all the latches for transparent mode and falling makes them in latch mode.
Figure 3 shows the data flow in the inverter chain. Clock edge (rising edge in above fig.) travelling in the chain is transparent at the output of latches till pulse is high. At the point pulse goes low, all the latches enter into latch mode at this moment in the chain at the point till which the rising edge of clock has travelled we get a inverted outputs between 2 consecutive latches output. Falling of Pulse enable makes the clock pulse not latched in latch just after the inverter
till which the clock has reached (due to propagation delay of inverter). This
i
effect makes a repetition (..0110,. or ..1001..) in the chain. Number of such
repetition shows no. of edges travelling in the chain. Hence the delay time can
be given as Tiv * N (where N = No. of inverter at1 which we get repetition
effect, Tiv is the propagation delay of one inverter). '
Chip area required for implementing Step 2 is directly proportional to the (I/ Fclk) hence the above mentioned methodology can be modified to reduce the area by reducing the chain length and "f (margin) to half, which means that area is reduced by 2. . This is possible with sampling done on both the edges (riging and falling)
Figure 4 shows the pulse measurement using both clock edges. It is assumed that the counter increments at every positive edge of the Fclk.
The chain length is = { [ (1/Fclk) / 2 ] + Margin } The input of the first inverter in the chain can be latched and can be used to check position of Fclk at the time pulse goes Low. This makes the calculations as below.
Tscc = K + Tinv N
Where K = 0 if the output of the latch at the starting of chain is 11' his shows that the Fclk was high when pulse went low.
- [ (1/Fclk) / 2 ] if the output of the starting latch is '0'
This shows that the Fclk was Low and hence we need to add the half period in the calculation
Tinv = Propagation delay of single inverter
N = No. of inverter at which we see the repetition effect.
Figure 5 shows a preferred embodiment of the invention uses blocks: RING_OSC MAIN_SCALE SECONDARY_SCALE COMPRESS_BITS
The RING OSC block is a ring oscillator, which is enabled by input pulse to be measured . The main feature of this ring oscillator is that it maintains the final stage(0,l) when pulse at input(which is to be measured) goes low. This feature of the RING_OSC remove the inaccuracy of one clock period of output oscillation which will be in case of normal ring oscillator.
The MA1N_SCALE block is a simple counter, to perform step 1 calculations. Which counts the number of clock pulses delivered by the RING OSC block.
The SECONDAY_SCALE block is used to trace the distance till which the Pulse has travelled in Clock from RING_OSC i.e.; for the Step 2 Calculation
.This consist of chain of inverters in which the Clock from RfNG_OSC propagates and the values at the output of the inverters are latched . Final inverter chain value is latched by the falling of the PULSE to be measured. The chain of inverters can be switched in oscillate mode to get the delay of one inverter. So, the accuracy is till +- one inverter delay.
The COMPRESS BITS block reduces the number of bits from the SECONDARY_SCALE. This is done by comparing the bits in a normal inverter chain and the inverter chain output latched by SECONDAY_SCALE. In normal inverter chain the pattern of ..01010.. will be repeated for the no. of inverters in the chain but in the Secondary scale latched value there will be repetition of 00 or 11 in the full chain somewhere (..0110101.. or ..010010..) the repetition of bits shows that the clock edge has travelled till that inverter. For a secondary scale output of 64 bits(that means 64 inverters are used in the secondary scale) the compress bit will convert it to 6bit which will be the inverter till which the clock is reached.
Figures 6, 7 & 8 show the signals obtained at each lock of the preferred embodiment of Figure 5, using a simulation of the system.
Advantages of the present invention
On-chip pulse width characterisation is possible, which removes the tester
inaccuracy while characterisation of pulse width.
Accuracy is increased by the method proposed. The inaccuracy inserted is
± of 1 inverter delay (which is few ten ps).
The pulse width available is in form of Digital data (binary, grey etc..
depending on the Compress_BITS logic).
The pulses of width less the l/(2*Fmax) (where Fax is the maximum
operating frequency of the output pad) can also be measured now.
No repeater is needed to transfer the data from block to block/lO Pads, as
data is static and in digital format.
Measurement range can be increased with minimum increase of hardware.
For example to double the range only addition of single Flip- Flop is
needed in the step 1 counter.

We claim:
1. A method for providing improved resolution in the measuring the pulse
width of digital signals, comprising the steps of:
counting the integral number of measuring clock pulses covered by
said digital pulse,
triggering a chain of cascaded high resolution delay elements from
the trailing edge of said measuring clock pulses,
measuring the delay count obtained from said chain of cascaded
delay elements from the trailing edge of the last measuring clock
pulse upto the end of said digital pulse, and
adding said measured delay count to said integral measuring clock
pulse count to obtain the total width of said digital pulse.
2. A method as claimed in claim 1 wherein the number of cascaded
minimum delay elements is such that the cumulative delay of said chain of
delay elements is slightly greater than the time period of the measuring
clock.
A method as claimed in claim 2 wherein said chain of cascaded minimum
delay elements is triggered by both the leading and trailing edges of said
measuring clock pulse so that the required number of delay elements is
reduced to half.
A method as claimed in claim 1 wherein the count value is converted to a
compressed digital form.
A method as claimed in claim 1 applied to measurement of on chip pulse
widths thereby overcoming 1O pad speed limitations of off-chip
measurement techniques.
A system for providing improved resolution in the measuring the pulse
width of digital signals, comprising
means for counting the integral number of measuring clock pulses
covered by said digital pulse,
means for triggering a chain of cascaded minimum delay elements
from the trailing edge of said measuring clock pulses,
means for measuring the delay count obtained from said chain of
cascaded delay elements from the trailing edge of the last measuring
clock pulse upto the end of said digital pulse, and
means for adding said measured delay count to said integral
measuring clock pulse count to obtain the total width of said digital
pulse.
A system as clamed in claim 6 wherein said delay elements are digital
inverters.
A system as claimed in claim 7 wherein said measuring clock pulses are
generated by any known oscillator.
A system as claimed in claim 6 wherein said count value is connected to a
compressed digital form.
1 0. A system as claimed in claim 6 wherein the number of said delay elements is such that the cumulative delay is slightly greater than the time period of the measuring clock.
A system as claimed in claim 6 wherein said chain of cascaded minimum
delay elements is triggered by both the leading and trailing edges of said
measuring clock pulse so that the required number of delay elements is
reduced to half.
A system as claimed in claim 6 applied to on-chip pulse width
measurements thereby overcoming the IO pad speed limitations of off-
chip measurement techniques.
A method for providing improved resolution in the measuring the pulse
width of digital signals substantially as herein described with reference to
and as illustrated in the accompanying drawings.
A system for providing improved resolution in the measuring the pulse
width of digital signals substantially as herein described with reference to
and as illustrated in the accompanying drawings.