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FIELD OF THE INVENTION
The invention relates to the method of improvement in efficiency of
multicrystallin silicon solar cells using self-masking and low-energy
Reactive Ion Etching (RIE) process for texturization.
OBJECT OF THE INVENTION
- The object of the invention is to develop a self-masking, damage
free RIE texturization process capable of enhancing light trapping
in the multicrystalline silicon wafers for producing high efficiency
solar cells.
- Further object of the invention is to develop a process to produce
damage free, nano scale textures on the grain surface and
boundaries.
- Yet another object of the invention is to avoid high energy ions
induced sputter damage

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- Also the object of the invention is to remove loose, spiky silicon
material from the etched surface to make it damage free.
- Yet another object of the invention is to develop a wafer carrier /
jig to carry 12 nos of 125mm Sq wafers providing perfect
grounding path.
BACKGROUND OF THE INVENTION
Multicrystalline silicon wafer are strong contender for reduction in the
cost of solar cells due to relatively lower cost of the starting wafers.
However, the cost advantage is often offset by lower efficiency of
these cells, when processed with regular process steps employed for
mono crystalline silicon wafers. In particular, the conventional
texturization technique (orientation dependent) used for < 100 >
oriented monocrystalline silicon wafers is not effective in the case of
multicrystalline silicon wafers.

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Reactive Ion Etching (RIE) process has proven its potential in forming
random nanostructures on the surface of multicrystalline silicon
wafers leading to a low reflectivity of the surface suitable for solar
cell fabrication. Various approaches are being attempted besides
mask-less RIE. Many workers use nano-masks, such as, organic
colloidal molecules onto the wafer surface and some follow metal
assisted RIE process for selective etching. However, scaling up of
the process to industrial production scale is still a challenge for the
PV industry.
RIE plasma texturing does not rely on the crystallographic orientation
of the substrate resulting in an isotropic, random shaped texture onto
as-cut / polished mc-Si material. Major advantages of RIE
texturization over wet chemical isotropic texturing, considering
production of larger and thinner wafers in the future, are as follows:
■ Texturization process is independent of the type and crystallinity
of silicon substrate leading to high flexibility with regard to wafer
supply. Further the optical properties of the surface are

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comparable to wet chemical etching methods ad can be achieved
on all types of materials.
■ Compared to wet chemical isotropic texturing, RIE texturing shows
higher efficiency potential due to lower achievable reflectance
values.
■ RIE process is a stress-free process suitable for thin wafers
compared to the conventional wet texturization process.
Therefore it has a prospect of better yields. The process is also
amendable to mass production. Use of thinner wafers for solar
cells is the current trend in industry for bringing down the cost.
■ RIE process is a technological achievement in the direction of a
fully dry solar cell process involving minimum usage of costly DM
water, hazardous chemicals and also having no environmental
issues.
In the present invention, a metal catalyst-free, self-masking and low-
energy RIE process has been developed to texturize mc-Si wafers of

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125 mm sq. using an in-house integrated pilot facility for RIE
texturization. The RIE textured wafers been used in solar cell
manufacturing line leading to substantial improvement, i.e., up to 2.4
% absolute improvement in the efficiency of the multicrystalline
silicon solar cells.
SUMMARY OF THE INVENTION
The present invention discloses a self-masking and low-energy
Reactive Ion Etching (RIE) process for texturization of large area
multicrystalline silicon (mc-Si) wafers for use in solar cell processing.
The safe and non-toxic sulfur hexafluoride and oxygen (SF6 & O2)
reactant gases, under the influence of RF (13.56 MHz) or VHF (70
MHz) power, in a narrow band of process conditions, create micro
masks giving rise to selective etching of the multicrystalline silicon
surface. This leads to the formation of randomly distributed nano
structures giving black look to the silicon surface irrespective of the
crystal orientation. These nano structures are found to exhibit
enhanced light trapping property when their dimensions are

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comparable to or larger than the wavelengths of the incident sunlight
leading to substantial improvement in the efficiency of mc-Si solar
cells.
As a preparatory step, viz., conventional alkali etching solution was
used for saw damage removal. This was considered necessary for
initiating texturization process by RIE on defect free surface for
emitter formation. The sample wafers were mounted on the specially
designed carrier / jig to form grounded electrode required to inflict
minimum damage for maintaining device quality wafer surface.
Reactant gases were subjected to medium RF power to minimize RIE
induced surface damage. An acidic etching solution, called Damage
Removal Etch (DRE) was used to ensure totally damage free surface.
The overall effect of enhanced light trapping and cell area
enhancement due to RIE texturization lead to an absolute
improvement in efficiency of 125 mm sq mc-Si solar cell up to 2.4%.
The maximum efficiency of the cell with and without RIE were

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observed to be 15.1% and 12.7%, respectively, when processed
under identical conditions.
DETAILED DESCRIPTION OF THE PREFERED EMBODIMENT
The present invention gives a brief description of the RIE process
facility, process trials for optimization of process parameters, testing
with respect to optoelectornic properties of the textured surface and
finished solar cell.
The basic reactive ion etching system used in texturization of mc-Si
wafers consists of various components / subcomponents of the
system as shown in Fig. 1. Essentially, the plasma chamber (1) with
plasma (7) at the centre consists of a powered RF electrode (2) and
specially designed grounded wafer carrier plate/jig (3) carrying wafer
(6) forming a paralled plate capacitor configuration with powered
electrode. The chamber is also provided with gas inlet/ exhausts
ports, throttle valve to maintain the process pressure, roots/dry
pump (4) combination (5) to evacuate residual reactant gases and

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reaction byproducts. A capacitance manometer is used to monitor
the pressure of the reactant gases inside the chamber. Reactant gas
cylinders are fitted with suitable pressure regulators and excess flow
valves. Flow of gases to the chamber is monitored and accurately
controlled through calibrated mass flow controllers.
RF/VHF generators (13.56 /70 MHz) with matching network is used
for generation of reactive ion species responsible for isolrotpic
etching of the silicon wafer except on the surface areas which are
self-masked by the polymer (SixOyFz) formed and adsorbed randomly
during the reaction. This selective etching of the silicon surface is
independent of the orientation of the silicon grain present in the
multicrystalline silicon. This random etching on silicon surface
givesblack appearance and reduces reflectance of visible light to
around 3%.
A special jig suitable for mounting a maximum of 12 wafers each of
125 mm sq. was designed and fabricated. The jig was designed with

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an aluminum back plate for perfect grounding of the wafers mounted
in the collared slots.
Alkali solution of an optimum concentration (15 to 50% by mass) at
elevated temperatures (60-98 deg C) was used for a duration (5 to
300 seconds) decided by silicon removal rate till the wafers are free
from saw marks required for defect free surface.
A specially designed carrier to load wafers was used to inflict
minimum damage for maintaining device quality surface. The
arrangement facilitated etching due to reactive chemical specifies
present in the plasma and minimized damage to silicon surface due
to impact of high-energy ions responsible for sputtering. This
condition also facilitated formation of nano structures on the alkali-
etched microstructures on randomly oriented crystallites present on
the surface of the wafer.
Process optimization trials were initiated with full factorial Design of
Experiments considering the most critical process parameters only.

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These parameters were short-listed with preliminary experimentation.
Process parameters such as, flow of reactant gases, chamber
pressure, RF or VHF power applied, wafer mounting arrangement -
on RF electrode or grounded carrier etc., were tried for arriving at
optimum process parameters that resulted in producing black silicon.
The optimum process parameters were frozen and statistically
significant quantities of wafers were processed using the optimum
RIE process parameters. After the RIE process, wafers were
subjected to an acidic Damage Removal Etch (DRE) for making the
textured surface suitable for subsequent solar cell process steps
without much loss of reflectivity of the wafer surface. The DRE
process was optimized with respect to composition of etching
solution, process time and temperature and finally the roughness of
the textured surface.
During the course of process trails, samples were inspected using
digital camera [Fig 2], metallurgical microscope [Fig 3] and SEM
micrograhps [Fig 4]. Measurement of relative reflectance on full size

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- 125x125 mm sq., wafer was made after RIE and DRE process steps
using a proprietary in-house developed diffused reflectance test set
up.
In addition to visual inspection for uniformly black surface
morphology, RIE textured samples were tested using an in house
developed set up for getting relative reflectance data. This relative
measurement was enough to get feedback to process improvement.
Microscope pictures of samples and SEM micrograph of some of the
samples revealed very good textured silicon surface and other optical
properties. The average surface roughness of the RIE etched wafers
was measured using Tencor's Alpha Step-250 surface profilometer
and was found to be in the range of 1 to 1.5 ^m after RIE.
The RIE textured multicrystalline silicon wafers of 125 mm sq, size
showed the minimum total diffused reflectance of ~3% after RIE
process and ~5% after damage removal etch (DRE). Fig 5, shows
diffused reflectance spectra for RIE wafers at different stages of solar
cell processing.

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Measurements of electrical performance of the mc-Si solar cell of
125mm xl25mm size showed conversion efficiency up to 15.1% for
RIE textured cells against 12.7% for the cell without RIE, showing
2.4% absolute improvement in the efficiency [Fig. 7 and 8].
The best efficiency obtained (15.1%) is among the highest reported
values for mc-Si solar cells with RIE texturization and AR Coating.
Light and Dark I-V characteristics of solar cells (rii: 1.4, JO1: 1.28
nA/cm2, lsc: 5.1 A, Voc: 0.601V and FF: 0.71) indicate damage free
junction of the device and hence optimized RIE texturization and DRE
process that is a necessary process step after RIE texturization.
The following RIE Process parameters with their values were used in
the optimization.

SN RIE Process Parameters Value
1. Electrode Size (cm2) ~35x15 to 35x40
2. Gases used & their ratio SF6:O2=8:1TO1.1
3. RF ower(W) 90-300
4. Total flow of SF6 & O2 gases (cm) 100 to 250
5. Chamber Pressure (m Torr) 50 to 600
6. Process Duration (min) 15-60
7. No. of wafers per Batch I to 4
8. Frequency of RF/VHF generator(MHz) 13.56 / 70

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a) For DRE process optimization, the following parameters with their
values were used.

SN DRE Process parameters Value
1. Ratio of the acid mixture (HF:HNO3: DM Water) 1:39:60 TO 10:55:35
2. Duration (sec) 10 to 250
3. Temperature (°C) 2 to 25
4. No. of wafers per Batch l to 10
BREF DESCRIPTION OF THE ACCOMPANIED DRWAINGS
Fgure - 1 gives a Schematics of RIE process Chamber with details of
wafer mounting, RF plasma etc.
Figure - 2 shows "photograph" of silicon wafers after RIE
texturization-Black silicon is visible.
Figure - 3 shows microscope photograph of mc-Si sample wafers a)
as-cut (800x) and b) RIE Textured (800x).
Figure - 4 shows SEM micrographs of mc-Si sample wafers a) before
RIE (X 15K) and b) after RIE (x 15k)

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Figure - 5 shows spectroscopic measurement of diffused reflectance
of samples mc-Silicon wafers and cells taken at different stages of
process
Figure - 6 shows typical solar cell manufacturing process sequence
Figure - 7 shows a comparison of I-V characteristics of 125 mm sq
mc-Si solar cells with and w/o RIE texturization
Figure - 8 shows improvement in mc-Si solar cell efficiency using RIE
for texturization and SiNx A R Coating - comparison of best cells with
and without RIE.
Figure - 9 shows dark I-V (Forward and Reverse) characteristics of
the 125 mm sq mc-Si solar cell.
Figure - 10 shows design of a typical wafer carrier used for mounting
for wafers.

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WE CLAIM
(1) A method of reactive ion etching (RIE) texturization, tailored for
multi crystalline silicon solar cells of 125 mm sq, to improve its
efficiency.
(2) The method as claimed under claim 1, wherein a self-masking
process due to the formation and adsorption of a polymer (e.g.
SixOy/Fz) leading to selective etching of the wafer surface,
resulting in low reflectance and increase in current.
(3) The method as claimed under claim 1 and 2, wherein the
device of positioning wafers on the ground electrode resulting
in damage free, nano scale textures on the grain surfaces and
grain boundaries delineated by alkali based etching solution.
(4) The method as claimed under claim 1, 2, and 3, wherein
application of medium RF (radio frequency) power density,
avoiding high energy ion induced sputter damage.

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(5) The method as claimed under claim 1, 2, 3, and 4, wherein a
device to remove loose, spiky silicon material from the etched
surface after RIE process and also loose reaction by products
adhering to the silicon surface.
(6) A novel wafer carrier / jig for mounting up to 12 nos. of 125
mm sq. wafers grounded electrically to achieve minimum RIE
damage.

The present invention discloses a self-masking and low-energy
Reactive Ion Etching (RIE) process for texturization of large area
multicrystalline silicon (mc-Si) wafers for use in solar cell processing.
The safe and non-toxic sulfur hexafluoride and oxygen (SF6 & O2)
reactant gases, under the influence of RF (13.56 MHz) or VHF (70
MHz) power, in a narrow band of process conditions, create micro
masks giving rise to selective etching of the multicrystalline silicon
surface. This leads to the formation of randomly distributed nano
structures giving black look to the silicon surface irrespective of the
crystal orientation. These nano structures are found to exhibit
enhanced light trapping property when their dimensions are
comparable to or larger than the wavelengths of the incident sunlight
leading to substantial improvement in the efficiency of mc-Si solar
cells.
As a preparatory step, viz., conventional alkali etching solution was
used for saw damage removal. This was considered necessary for
initiating texturization process by RIE on defect free surface for
emitter formation. The sample wafers were mounted on the specially
designed carrier / jig to form grounded electrode required to inflict
minimum damage for maintaining device quality wafer surface.
Reactant gases were subjected to medium RF power to minimize RIE
induced surface damage. An acidic etching solution, called Damage
Removal Etch (DRE) was used to ensure totally damage free surface.
The overall effect of enhanced light trapping and cell area
enhancement due to RIE texturization lead to an absolute
improvement in efficiency of 125 mm sq mc-Si solar cell up to 2.4%.
The maximum efficiency of the cell with and without RIE were
observed to be 15.1% and 12.7%, respectively, when processed
under identical conditions.