Description:RELATED APPLICATION
[0001] The present application claims priority to U.S. Non-Provisional Patent Application No. 17/549,192 filed on 13 December 2021 and titled “INSTRUCTION DECODE CLUSTER OFFLINING” the entire disclosure of which is hereby incorporated by reference.

BACKGROUND
1. Technical Field
[0002] This disclosure generally relates to processor technology, and instruction decode technology.
2. Background Art
[0003] An instruction cycle for a processor or core may involve fetch, decode, and execution of instructions. Parallel and/or out-of-order processors may include multiple decoders to decode more than one instruction at a time. A decode unit than can decode N instructions at a time may be referred to as an N-wide decoder (e.g., 4-wide, 8-wide, etc.).

BRIEF DESCRIPTION OF THE DRAWINGS
[0004] The various embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:
[0005] FIG. 1 is a block diagram of an example of an integrated circuit according to an embodiment;
[0006] FIGs. 2A to 2C are flow diagrams of an example of a method according to an embodiment;
[0007] FIG. 3 is a block diagram of an example of an apparatus according to an embodiment;
[0008] FIG. 4 is a block diagram of an example of a front end unit according to an embodiment;
[0009] FIG. 5 is an illustrative diagram of an example of taking a cluster offline for power savings according to an embodiment;
[0010] FIG. 6 is an illustrative diagram of an example of taking a cluster offline for prefetch activity according to an embodiment;
[0011] FIG. 7 is a block diagram of an example of an out-of-order processor according to an embodiment;
[0012] FIG. 8A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention;
[0013] FIG. 8B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention;
[0014] FIGs. 9A-B illustrate a block diagram of a more specific exemplary in-order core architecture, which core would be one of several logic blocks (including other cores of the same type and/or different types) in a chip;
[0015] FIG. 10 is a block diagram of a processor that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention;
[0016] FIGs. 11-14 are block diagrams of exemplary computer architectures; and
[0017] FIG. 15 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention.

DETAILED DESCRIPTION
[0018] Embodiments discussed herein variously provide techniques and mechanisms for instruction decode cluster offlining. The technologies described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, laptop computers, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices including integrated circuitry which is operable to take a decode cluster offline.
[0019] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.
, Claims:1. An integrated circuit, comprising:
a core; and
an instruction decoder communicatively coupled to the core to decode one or more instructions for execution by the core, wherein the instruction decoder includes:
two or more decode clusters in a parallel arrangement, and
circuitry to offline a decode cluster of the two or more decode clusters.