Abstract: The invention is a method and a system for the study and test of thyristors using digitally controlled gate current source for precise and independent triggering. The system can test the static characteristics of thyristor devices like SCR, TRIAC, SCS, IGCT and GTO for educational trainers and industrial testing applications. The system consists of bidirectional current source power supplies{300,400) which are used to precisely control the gate current in addition to a current limited voltage source power supply(200) that supplies the power across the power terminals of the thyristor. The power supply can be digitally controlled for performance of the requisite task. A microcontroller(IOO) with a built-in microprocessor (101) is used for monitoring the output voltage through an amplifier(207) keeping its operating program in a flash memory{102) with the help of RAM area(103).
Field of invention
The invention generally relates to electronics and more particularly, an arrangement of thyristor based devices that can maintain a constant gate current even under varying power terminal voltage conditions.
Background of Invention
A thyristor is a solid-state semiconductor device with four layers of alternating P- and N-type materials. It acts exclusively as a bistable switch, conducting when the gate receives a current trigger, and continuing to conduct until the voltage across the device is reverse biased, or until the voltage is removed.
The primary function of a thyristor is to control electric power and current by acting as a switch. For such a small and lightweight component, it offers adequate protection to circuits with large voltages and currents (up to 6000 V, 4500 A).
The measurement and plotting of static characteristics is one of the most important part of study, testing and characterization of any electronic device. Thyristor, by their nature are current controlled latching devices which require a momentary current pulse through the gate terminal to be triggered into conduction. Once triggered, the devices continue to conduct even after the removal of the triggering current pulse and only extinguishing when the ON state current drops below a certain minimum value.
Therefore, it is essential to know exactly the minimum triggering current for various main terminal voltage ranges for optimal implementation of the triggering circuits. Traditionally, a circuit with two voltage source power supplies, one for the gate and another for the main terminal voltage have been used each with an appropriate limiting resistor.
Thyristors, by their very nature, produce variance in gate voltage when the main terminal voltage varies. Such circuits described above have the significant limitation of the inability to maintain the gate current at a constant level when the main terminal voltage is varied. This makes it almost impossible to get multiple accurate VI
characteristics plots which are essential for device characterization, testing and study applications.
The US patent application No. "20120084604" titled "Automation system for testing and measurement of system and device parameters, and control and automation of systems" discloses a system and apparatus which allows for superior testing and measurement, as well as control and automation capabilities. This invention comprises a modular foundational system for automation that provides essential building blocks for a variety of test, measurement and internal or external control demands. The essentials include IEEE-488 communications capability which matches the caliber of large test stand, thus providing a configurable system that possesses great capabilities in test, measurement and automation, without prohibitive cost and complexities for the user. The platform described herein is also well suited for portable applications as the system does not occupy a significant amount of space.
Prior art for the study and test of thyristors with single gate terminal
The above diagram describes prior art for the study and test of thyristors with single gate terminal (SCR, TRIAC, GTO and IGCT) with voltage source power supply 2 with a series connected current limiting resistor for powering up the gate and voltage source
power supply 1 with a series connected current limiting resistor for powering up the power terminals. Since current control for the gate power supply is absent, there is a need to continuously adjust the voltage source power supply 2 every time the voltage power supply 1 is adjusted, for the maintenance of a constant gate current.
Prior art for thyristors with dual gate terminal {SCS)
The above diagram describes prior art for the study and test of thyristors with dual gate terminal (SCS) with voltage source power supplies 2 and 3 with series connected current limiting resistors for powering up the gate terminals 1 and 2 respectively. The voltage source power supply 1 with a series connected current limiting resistor is used for powering up the power terminals. Since current control for the gate power supplies is absent, there is a need to continuously adjust the other voltage source power supplies every time the voltage power supply 1 is adjusted, for the maintenance of a constant gate current as in the below diagram.
Prior art - Graph V-l characteristics depicting constant gate current
The prior art described in the above diagrams depicts the significant disadvantage of not being able to maintain the gate current at a constant level. This makes it almost impossible to get multiple accurate VI characteristics graphs which are essential for device characterization and study applications.
To overcome these limitations, a circuit arrangement with digitally controlled bidirectional current sources is developed to maintain a constant gate current even under varying power terminal voltage conditions.
Objective of invention
The main objective of the invention is the design, study and test of a circuit arrangement with digitally controlled bidirectional current sources developed to maintain a constant gate current even under varying power terminal voltage conditions.
Summary of invention
A circuit arrangement for the study and test of thyristors with gate terminals such as SCS, SCR, TRIAC, GTO and IGCT is developed. The gate terminals supplies digitally controlled bidirectional current source by powering up the power terminal. A current limiting resistor is connected in series with the voltage source to limit the current flowing into the power terminals of the thyristors under test.
The circuit enables precise, reliable and accurate triggering of thyristor devices for study, characterization and testing applications. The arrangement can be used as a standalone system without requiring any external equipments. Required power sources, both voltage and current sources are built into the system. Also, all the required measuring and monitoring facilities are built into the system itself. Because of its standalone nature, the invention can be carried easily around the laboratory and also to the field. Since all the requirements are built-in the invention, it helps users to studies and finish their work faster than before. The method can be implemented in thyristor devices with single gate or dual gate.
Brief description of the drawings
Figure 1 shows the Circuit arrangement for the study and test of thyristors with single gate terminal
Figure 2 shows the Circuit arrangement for the study and test of thyristors with dual gate terminal
Detailed Description of the Invention
A method and system for study and test of thyristors using digitally controlled gate current source for precise and independent triggering and study is formulated. The system enables for the study and test of static characteristics of thyristor devices like SCR, TRIAC, SCS, IGCT and GTO for educational trainer and industrial testing applications. The system consists of bidirectional current source power supplies which
are used to precisely control the gate current in addition with a current limited voltage source power supply which supplies the power across the power terminals of the thyristor. The power supplies can be digitally controlled for performance of the requisite task.
One digitally controlled bidirectional current source power supply is used in case of thyristors with single gate like SCR, TRIAC, GTO, IGCT and two digitally controlled bidirectional current source power supply are used in case of thyristors with dual gates like SCS.
The digitally controlled current source power supply for the thyristor maintains the gate current at a constant level irrespective of the changes in the voltage power supply which applies the voltage across the power terminals of the thyristor. In absence of the same, the thyristor gate current tends to vary with respect to the variation in the power terminal voltage. This maintenance of gate current at a constant level enables the precise observation of the triggering point of the thyristor which is essential for device characterization, testing and study.
The digitally controlled power supplies enable the'plotting of theoretically compliant V-l characteristics waveforms which aids greatly in the study, test and characterization of the thyristor devices under test. The current source is capable of generating current output in either polarities enabling precise four quadrant gate triggering for TRIACs, GTO, IGCT and SCS thyristors. Experimental V-l Characteristics plots are depicted as graphs for both positive and negative gate current values.
The power supplies are controlled digitally by an integrated, on-board microprocessor which precisely controls the voltage/current output of the power supply. Current and voltage measurements are made at the output of each power supply and the outputs are adjusted precisely to maintain the voltages and currents as per user settings. Voltage measurements are also made across the power terminals of the thyristor.
The integrated study and test arrangement also includes a user interface with tactile switches and encoders for digital control of power supplies. The voltage and current values are displayed in a colour graphics LCD. Facility for automatic plotting of output V-l characteristics for different values of gate currents is provided for quick study and testing of the thyristor under test.
The difficulty of controlling the gate current in prior art is explained in where the gate current change is plotted when the voltage source power supply 1 is increased from zero while the voltage source power supply 2 which powers up the gate is held at a constant value. As the terminal voltage is increased, the gate current decreases abruptly a bit when it reaches point 'a', which is the biasing voltage of a silicon PN junction. Then, the gate current decreases gradually as the voltage increases(region 'b'). When the voltage is increased further, the gate current falls rapidly just before the thyristor gets triggered (point 'c') and the current continues to decrease further. This changing gate current makes it almost impossible to manually maintain the gate current at constant value for study and characterization.
The below diagrams describes the circuit arrangement for the study and test of thyristors with single gate terminal (SCR, TRIAC, GTO and IGCT) and dual gate terminals comprising a digitally controlled bidirectional current source power supply powering up the gate and a digitally controlled voltage source power supply for powering up the power terminals. The thyristors can be tested for dual and any number of gate terminals. A current limiting resistor is connected in series with the voltage source to limit current flowing into the power terminals of the thyristor under test.
Arrangement for the study and test of thyristors with single gate terminal
Arrangement for the study and test of thyristors with dual gate terminal
The complete integrated arrangement for study and test of a single gate thyristor device (SCR, TRIAC, GTO and IGCT) is represented below diagrammatically. The two power supplies are controlled digitally by an integrated, on-board microprocessor which
precisely controls the voltage/current output of the power supplies. Current and voltage measurements are made at the output of each power supply and the outputs are adjusted precisely to maintain the voltages and currents as per user settings.
Complete integrated arrangement for study and test of a single gate thyrrstor
device
The below diagram describes the gate current value when the voltage source is
varied from zero to maximum value for the arrangements. There is no change in the
gate current when the voltage source is varied. The use of the bidirectional digitally
controlled current source ensures the maintenance of a constant gate current in order to
ensure predictable and reliable triggering of the thyristor- -• -
Working Principle - Detailed Circuit Arrangement
The circuit arrangement is designed to get the required integrated facility to study, test and get insights on using thyristors with single gate terminals (SCR, TRIAC, GTO and IGCT) in a stand-alone environment. The circuit extensively use the microcontroller which comes with a built-in microprocessor (101), keeping its operating program in a flash memory(102) with the help of RAM area(103). The microcontroller also contains other useful blocks; PWM timer(104) controlling the pulse width of the square wave signals required for controlling the output of the voltage source(200) meant for powering up the thyristor device. The microcontroller also contains digital to analog converter device (105 and 106) required to feed the current source amplifier(301). The microcontroller collects all the analog sample waveforms from the voltage and current sources through the analog mux(107) and gets the digital data representing the analog samples by using the built-in analog to digital converter(108). The microcontroller gets a reference voltage to make accurate voltage and current readings from an external voltage reference(110). The microcontroller's general purpose input and output lines and interrupts(109) are used to interface user interacting peripherals like colour
graphics LCD(111), tactile switches(112) and encoders(113). User uses these peripherals to define the required operating conditions for the power device under test.
The voltage source(200) is used to maintain a constant operating voltage at the power terminal and is operating as a DC-DC step down converter producing the user defined operating voltage from a higher voltage. This step down converter uses a suitable inductor to produce an user defined operating voltage to the device under test. A current sensor(203) is used to measure the current output of the DC-DC converter. The current readings are amplified by the amplifier (204) and connected to the analog mux(107) of the microcontroller. Likewise the output voltage is also monitored by the microcontroller through another amplifier(205). The current flowing through the thyristor device is limited by the current limiting resistor(206) to safeguard the device. The power terminal voltage of the device is monitored by the microcontroller using another amplifier(207).
These family of devices have a single gate for their operation and the gate current shall be kept constant to generate ideal study and test conditions and this current shall be maintained in a constant value by the current source (300).
The current source gets its reference voltage to its input amplifier(301) from the DAC(105) of the microcontroller. This reference voltage is converted into required output current using a Power Amplifier(302) and is measured for accuracy using a current sensor(303). The output of this sensor is conditioned by the amplifier(305) and then applied to the analog mux of the microcontroller. A current limiting resistor is used for powering up the gate and voltage source power supply.
Thus a circuit arrangement with digitally controlled bidirectional current sources is developed to maintain a constant gate current even under varying power terminal voltage conditions.
I claim
. An arrangement for study and test of thyristors using digitally controlled gate current source, comprising: a voltage source{200), current sources (300,400) and a microcontroller(100) for monitoring the output voltage through an amplifier(207).
The arrangement for study and test of thyristors using digitally controlled gate current source as claimed in claim 1, wherein the said voltage source(200) maintains a constant operating voltage at the power terminal and operates as a DC-DC step down converter producing a user defined operating voltage from a higher voltage, comprising a step down converter using a suitable inductor to produce the user defined operating voltage to the device under test.
The arrangement for study and test of thyristors using digitally controlled gate current source as claimed in claim 1, wherein the said voltage source(200) comprising:
a current sensor(203) for measuring the current output of the DC-DC converter;
amplifiers (204, 205) connected to an analog mux(107) of the said microcontroller(IOO) for amplifying the current readings;
a.current limiting resistor(206) connected in series with the voltage source(200) to safeguard the device by limiting the current flow through the thyristor device; and
an integrated onboard processor for controlling the voltage or current output of the power supply.
The arrangement for study and test of thyristors using digitally controlled gate current source as claimed in claim 1, wherein the said current sources(300, 400) comprising:
a system comprising an user interface with tactile switches and encoders for digital control of power supplies;
an input amplifier{301) from the DAC(105) of the microcontroller for getting its reference voltage wherein the reference voltage is converted into required output current using a Power Amplifier(302) which is measured for accuracy using a current sensor(303), such that the output of the sensor is conditioned by the amplifier(305) and then applied to the analog mux{107) of the microcontroller(IOO).
5. The arrangement for study and test of thyristors using digitally controlled gate current
source as claimed in claim 1, wherein the microcontroller(IOO) comprises:
a built-in microprocessor (101), keeping its operating program in a flash memory(102) with the help of RAM area(103);
a PWM timer(104) for controlling the pulse width of the square wave signals required for controlling the output of the voltage source(200) meant for powering up the thyristor device;
digital to analog converter devices{105,106) required to feed the current source amplifier(301)
an analog mux{107) for collecting all the analog sample waveforms from the voltage and current sources;
a built-in analog to digital converted 108) for getting the digital data representing the analog samples;
an external voltage referenced 10) for getting the reference voltage to make accurate voltage and current readings.
a general purpose input and output lines and interrupts{109) that interface user interacting peripherals like colour graphics LCD(111), tactile switches(112) and encoders(113) such that an user may use these peripherals to define the required operating conditions for the power device under test.
6. The arrangement for study and test of thyristors using digitally controlled gate current
source as claimed in claim 1, wherein an additional digitally controlled current source{400) with all associated circuit components have been added to power up an additional gate.
7. The arrangement as claimed in claim 1, is automated for plotting of output V-l characteristics for different values of gate current.
8. The arrangement as claimed in claim 1, can be implemented in thyristor devices with single gate or dual gate or any number of gates.
9. The arrangement as claimed in claim 1, can be used for the study and test of static characteristics of thyristor devices like SCR, TRIAC, SCS, IGCT and GTO used by educational trainers and industrial testing applications.
| # | Name | Date |
|---|---|---|
| 1 | 202041025243-8(i)-Substitution-Change Of Applicant - Form 6 [29-01-2022(online)].pdf | 2022-01-29 |
| 1 | 202041025243-Correspondence-250225.pdf | 2025-03-04 |
| 1 | 202041025243-Form9_Early Publication_16-06-2020.pdf | 2020-06-16 |
| 1 | 202041025243-IntimationOfGrant21-03-2025.pdf | 2025-03-21 |
| 1 | pdfviewer.pdf | 2024-12-27 |
| 2 | 202041025243-ASSIGNMENT DOCUMENTS [29-01-2022(online)].pdf | 2022-01-29 |
| 2 | 202041025243-Form 13-161224.pdf | 2024-12-19 |
| 2 | 202041025243-Form 6 supportive documents-29012025.pdf | 2025-01-29 |
| 2 | 202041025243-Form5_As Filed_16-06-2020.pdf | 2020-06-16 |
| 2 | 202041025243-PatentCertificate21-03-2025.pdf | 2025-03-21 |
| 3 | 202041025243-COMPLETE SPECIFICATION [29-01-2022(online)].pdf | 2022-01-29 |
| 3 | 202041025243-Correspondence-250225.pdf | 2025-03-04 |
| 3 | 202041025243-Form 6 uploaded documents-29012025.pdf | 2025-01-29 |
| 3 | 202041025243-Form 6-161224.pdf | 2024-12-19 |
| 3 | 202041025243-Form2 Title Page_Complete_16-06-2020.pdf | 2020-06-16 |
| 4 | 202041025243-DRAWING [29-01-2022(online)].pdf | 2022-01-29 |
| 4 | 202041025243-Form 6 supportive documents-29012025.pdf | 2025-01-29 |
| 4 | 202041025243-Form1_As Filed_16-06-2020.pdf | 2020-06-16 |
| 4 | 202041025243-Hearing Written Submssion-161224.pdf | 2024-12-19 |
| 4 | pdfviewer.pdf | 2024-12-27 |
| 5 | 202041025243-US(14)-HearingNotice-(HearingDate-03-12-2024).pdf | 2024-11-21 |
| 5 | 202041025243-Form18_Examination request _16-06-2020.pdf | 2020-06-16 |
| 5 | 202041025243-Form 6 uploaded documents-29012025.pdf | 2025-01-29 |
| 5 | 202041025243-Form 13-161224.pdf | 2024-12-19 |
| 5 | 202041025243-FER_SER_REPLY [29-01-2022(online)].pdf | 2022-01-29 |
| 6 | pdfviewer.pdf | 2024-12-27 |
| 6 | 202041025243-Form 6-161224.pdf | 2024-12-19 |
| 6 | 202041025243-FORM 3 [29-01-2022(online)].pdf | 2022-01-29 |
| 6 | 202041025243-Drawing_As Filed_16-06-2020.pdf | 2020-06-16 |
| 6 | 202041025243-8(i)-Substitution-Change Of Applicant - Form 6 [29-01-2022(online)].pdf | 2022-01-29 |
| 7 | 202041025243-ASSIGNMENT DOCUMENTS [29-01-2022(online)].pdf | 2022-01-29 |
| 7 | 202041025243-Description Complete_As Filed_16-06-2020.pdf | 2020-06-16 |
| 7 | 202041025243-Form 13-161224.pdf | 2024-12-19 |
| 7 | 202041025243-Hearing Written Submssion-161224.pdf | 2024-12-19 |
| 7 | 202041025243-PA [29-01-2022(online)].pdf | 2022-01-29 |
| 8 | 202041025243-COMPLETE SPECIFICATION [29-01-2022(online)].pdf | 2022-01-29 |
| 8 | 202041025243-Correspondence_16-06-2020.pdf | 2020-06-16 |
| 8 | 202041025243-FER.pdf | 2021-10-18 |
| 8 | 202041025243-Form 6-161224.pdf | 2024-12-19 |
| 8 | 202041025243-US(14)-HearingNotice-(HearingDate-03-12-2024).pdf | 2024-11-21 |
| 9 | 202041025243-8(i)-Substitution-Change Of Applicant - Form 6 [29-01-2022(online)].pdf | 2022-01-29 |
| 9 | 202041025243-Abstract_As Filed_16-06-2020.pdf | 2020-06-16 |
| 9 | 202041025243-Claims_As Filed_16-06-2020.pdf | 2020-06-16 |
| 9 | 202041025243-DRAWING [29-01-2022(online)].pdf | 2022-01-29 |
| 9 | 202041025243-Hearing Written Submssion-161224.pdf | 2024-12-19 |
| 10 | 202041025243-Abstract_As Filed_16-06-2020.pdf | 2020-06-16 |
| 10 | 202041025243-ASSIGNMENT DOCUMENTS [29-01-2022(online)].pdf | 2022-01-29 |
| 10 | 202041025243-Claims_As Filed_16-06-2020.pdf | 2020-06-16 |
| 10 | 202041025243-FER_SER_REPLY [29-01-2022(online)].pdf | 2022-01-29 |
| 10 | 202041025243-US(14)-HearingNotice-(HearingDate-03-12-2024).pdf | 2024-11-21 |
| 11 | 202041025243-8(i)-Substitution-Change Of Applicant - Form 6 [29-01-2022(online)].pdf | 2022-01-29 |
| 11 | 202041025243-COMPLETE SPECIFICATION [29-01-2022(online)].pdf | 2022-01-29 |
| 11 | 202041025243-Correspondence_16-06-2020.pdf | 2020-06-16 |
| 11 | 202041025243-FER.pdf | 2021-10-18 |
| 11 | 202041025243-FORM 3 [29-01-2022(online)].pdf | 2022-01-29 |
| 12 | 202041025243-PA [29-01-2022(online)].pdf | 2022-01-29 |
| 12 | 202041025243-DRAWING [29-01-2022(online)].pdf | 2022-01-29 |
| 12 | 202041025243-Description Complete_As Filed_16-06-2020.pdf | 2020-06-16 |
| 12 | 202041025243-ASSIGNMENT DOCUMENTS [29-01-2022(online)].pdf | 2022-01-29 |
| 13 | 202041025243-COMPLETE SPECIFICATION [29-01-2022(online)].pdf | 2022-01-29 |
| 13 | 202041025243-Drawing_As Filed_16-06-2020.pdf | 2020-06-16 |
| 13 | 202041025243-FER.pdf | 2021-10-18 |
| 13 | 202041025243-FER_SER_REPLY [29-01-2022(online)].pdf | 2022-01-29 |
| 13 | 202041025243-FORM 3 [29-01-2022(online)].pdf | 2022-01-29 |
| 14 | 202041025243-Abstract_As Filed_16-06-2020.pdf | 2020-06-16 |
| 14 | 202041025243-DRAWING [29-01-2022(online)].pdf | 2022-01-29 |
| 14 | 202041025243-FER_SER_REPLY [29-01-2022(online)].pdf | 2022-01-29 |
| 14 | 202041025243-FORM 3 [29-01-2022(online)].pdf | 2022-01-29 |
| 14 | 202041025243-Form18_Examination request _16-06-2020.pdf | 2020-06-16 |
| 15 | 202041025243-PA [29-01-2022(online)].pdf | 2022-01-29 |
| 15 | 202041025243-Form1_As Filed_16-06-2020.pdf | 2020-06-16 |
| 15 | 202041025243-FER_SER_REPLY [29-01-2022(online)].pdf | 2022-01-29 |
| 15 | 202041025243-DRAWING [29-01-2022(online)].pdf | 2022-01-29 |
| 15 | 202041025243-Claims_As Filed_16-06-2020.pdf | 2020-06-16 |
| 16 | 202041025243-COMPLETE SPECIFICATION [29-01-2022(online)].pdf | 2022-01-29 |
| 16 | 202041025243-Correspondence_16-06-2020.pdf | 2020-06-16 |
| 16 | 202041025243-FER.pdf | 2021-10-18 |
| 16 | 202041025243-FORM 3 [29-01-2022(online)].pdf | 2022-01-29 |
| 16 | 202041025243-Form2 Title Page_Complete_16-06-2020.pdf | 2020-06-16 |
| 17 | 202041025243-PA [29-01-2022(online)].pdf | 2022-01-29 |
| 17 | 202041025243-Form5_As Filed_16-06-2020.pdf | 2020-06-16 |
| 17 | 202041025243-Description Complete_As Filed_16-06-2020.pdf | 2020-06-16 |
| 17 | 202041025243-ASSIGNMENT DOCUMENTS [29-01-2022(online)].pdf | 2022-01-29 |
| 17 | 202041025243-Abstract_As Filed_16-06-2020.pdf | 2020-06-16 |
| 18 | 202041025243-Claims_As Filed_16-06-2020.pdf | 2020-06-16 |
| 18 | 202041025243-Drawing_As Filed_16-06-2020.pdf | 2020-06-16 |
| 18 | 202041025243-FER.pdf | 2021-10-18 |
| 18 | 202041025243-Form9_Early Publication_16-06-2020.pdf | 2020-06-16 |
| 18 | 202041025243-8(i)-Substitution-Change Of Applicant - Form 6 [29-01-2022(online)].pdf | 2022-01-29 |
| 19 | 202041025243-Abstract_As Filed_16-06-2020.pdf | 2020-06-16 |
| 19 | 202041025243-Correspondence_16-06-2020.pdf | 2020-06-16 |
| 19 | 202041025243-Form18_Examination request _16-06-2020.pdf | 2020-06-16 |
| 19 | 202041025243-US(14)-HearingNotice-(HearingDate-03-12-2024).pdf | 2024-11-21 |
| 20 | 202041025243-Hearing Written Submssion-161224.pdf | 2024-12-19 |
| 20 | 202041025243-Form1_As Filed_16-06-2020.pdf | 2020-06-16 |
| 20 | 202041025243-Description Complete_As Filed_16-06-2020.pdf | 2020-06-16 |
| 20 | 202041025243-Claims_As Filed_16-06-2020.pdf | 2020-06-16 |
| 21 | 202041025243-Correspondence_16-06-2020.pdf | 2020-06-16 |
| 21 | 202041025243-Drawing_As Filed_16-06-2020.pdf | 2020-06-16 |
| 21 | 202041025243-Form 6-161224.pdf | 2024-12-19 |
| 21 | 202041025243-Form2 Title Page_Complete_16-06-2020.pdf | 2020-06-16 |
| 22 | 202041025243-Description Complete_As Filed_16-06-2020.pdf | 2020-06-16 |
| 22 | 202041025243-Form 13-161224.pdf | 2024-12-19 |
| 22 | 202041025243-Form18_Examination request _16-06-2020.pdf | 2020-06-16 |
| 22 | 202041025243-Form5_As Filed_16-06-2020.pdf | 2020-06-16 |
| 23 | 202041025243-Drawing_As Filed_16-06-2020.pdf | 2020-06-16 |
| 23 | 202041025243-Form1_As Filed_16-06-2020.pdf | 2020-06-16 |
| 23 | 202041025243-Form9_Early Publication_16-06-2020.pdf | 2020-06-16 |
| 23 | pdfviewer.pdf | 2024-12-27 |
| 24 | 202041025243-Form 6 uploaded documents-29012025.pdf | 2025-01-29 |
| 24 | 202041025243-Form18_Examination request _16-06-2020.pdf | 2020-06-16 |
| 24 | 202041025243-Form2 Title Page_Complete_16-06-2020.pdf | 2020-06-16 |
| 25 | 202041025243-Form 6 supportive documents-29012025.pdf | 2025-01-29 |
| 25 | 202041025243-Form1_As Filed_16-06-2020.pdf | 2020-06-16 |
| 25 | 202041025243-Form5_As Filed_16-06-2020.pdf | 2020-06-16 |
| 26 | 202041025243-Correspondence-250225.pdf | 2025-03-04 |
| 26 | 202041025243-Form2 Title Page_Complete_16-06-2020.pdf | 2020-06-16 |
| 26 | 202041025243-Form9_Early Publication_16-06-2020.pdf | 2020-06-16 |
| 27 | 202041025243-PatentCertificate21-03-2025.pdf | 2025-03-21 |
| 27 | 202041025243-Form5_As Filed_16-06-2020.pdf | 2020-06-16 |
| 28 | 202041025243-IntimationOfGrant21-03-2025.pdf | 2025-03-21 |
| 28 | 202041025243-Form9_Early Publication_16-06-2020.pdf | 2020-06-16 |
| 29 | 202041025243-Renewel 6 th Year-220925.pdf | 2025-09-23 |
| 30 | 202041025243-Form 4-220925.pdf | 2025-09-23 |
| 31 | 563264-Renewel 9th Year-061025.pdf | 2025-10-07 |
| 1 | SearchHistory_202041025243AE_02-09-2022.pdf |
| 1 | Searchstrategy_202041025243E_29-07-2021.pdf |
| 2 | SearchHistory_202041025243AE_02-09-2022.pdf |
| 2 | Searchstrategy_202041025243E_29-07-2021.pdf |