Invention]
INTEGRATED CIRCUIT
[Technical Field]
[0001]
5 The present invention relates to technology for controlling semiconductor
integrated circuit operating speeds, and in particular to technology for improving
transistor operating speeds.
[Background Art]
[0002]
10 Regarding methods for raising the operating speed of semiconductor
integrated circuits, there are many options, for example by devising ways of
implementing a circuit, by changing circuit architecture, etc., Any of the methods
address the most fundamental issue of improving transistor operating speeds. By
doing so, the speed of any kind of circuit may be improved.
15 [0003]
Raising the transistor power supply voltage, or lowering the transistor
threshold voltage are both known methods for improving the operating speed of
transistors- For example, Non--Patent Literature 1 describes formulae which show the
rise time and fall time of a signal outputted by a C\QOS integrated circuit As is
20 made evident by these formulae, transistors operate faster when their power supply
voltages are higher or their threshold voltages are lower.
[0004]
The method disclosed in Patent Literature I is a known example among
methods for controlling transistor operating speeds by adjusting transistor power
25 supply voltages. With this method, power supply voltages are adjusted individually
for combined circuits separated by a plurality of flip-flops. Especially in a combined
circuit which includes a critical path, the power supply voltage of every logic
element is kept high. Due to this, the operation speed of the combined circuit
1
increases. Here, "critical path" refers to a pathway in a circuit that needs the most
amount of time to transmit a signal, or to an important pathway that must absolutely
transmit a signal within a provided time, In the method described in Patent
Literature 1, a power supply system is established individually for each combined
5 circuit, and therefore the number of power supply systems is great. However, since it
is possible to regulate a power supply voltage individually in each combined circuit,
power supply voltages can be kept low for combined circuits with a small number of
logic stages and lenient speed restrictions. As a result, not only the operating speed
of a combined circuit which includes a critical path can be kept at a high level, but
10 also the electric power consumption of the entire circuit can be suppressed.
[0005]
DVFS (Dynamic Voltage and Frequency Scaling) and AVS (Adaptive
Voltage Scaling) are other known technologies. With these technologies, the power
supply voltage of a circuit is dynamically adjusted in keeping with operating
15 frequency fluctuations. Specifically, when slow circuit operations are acceptable, the
operating frequency is kept at a usual level, and accordingly, the power supply
voltage also is kept at a usual level. Alternatively, when fast circuit operations are
necessary, the operating frequency is set higher than the usual level, and accordingly,
the power supply voltage is adjusted higher than the usual level- In this ww, these
20 technologies achieve both an improvement in operating speeds and a reduction in
electric power consumption.
[0006]
The method disclosed in Patent Literature 2 is a known example of a
method for controlling transistor operating speeds by adjusting transistor threshold
25 voltages. With this method, transistor threshold voltages are adjusted by heating
transistors. Specifically, a heater is provided next to an analog circuit such as a
differential amplifier, and the amount of heat produced by the heater is adjusted in
accordance with the environmental temperature. Here, when the temperature of a
2
transistor is higher, the threshold voltage of the transistor is lower. When the
environmental temperature falls, the heater heats the analog circuit to prevent
transistors included in the analog circuit from cooling down. By doing so, the
threshold voltages of the transistors are kept low, and their operation speeds kept
5 high. In this way, even at low temperatures, the analog circuit operates stably.
Changing the bias voltage of a transistor is another known method for controlling
transistor operating speeds by adjusting transistor threshold voltages.
[0007]
Furthermore, known technology exists for a design to lower the threshold
10 voltages of those transistors which are desired to have high operating speeds. For
example, in the semiconductor integrated circuit layout design method disclosed in
Patent Literature 3, a library (1-Ivt Cell Library) made up of transistors with high
threshold voltages (Idvt cell), and a library (Lvt Cell Library) made up of transistors
with low threshold voltages (Lvt cell) are used together. Specifically, first a netlist
15 which uses only the Lvt cell library is created, or a netlist having a portion thereof
forcibly replaced with the Hvt cell library is, created. Next, layout data is created in
accordance with the netlist. Delay time is then calculated for every pathway included
in the layout data. If timing errors are detected in the results of the calculation, then
cell resizing, buffer insertion, or cell replacement is performed, after which the delay
20 time of each pathway is calculated again. 't'his operation is repeated until no more
timing errors are detected. As a result, transistors placed on a critical path will be
made of Lvt cells, and all other transistors will be made of Hvt cells. In other words,
transistors that ought to operate at high speeds will have low threshold voltages
despite electric power consumptions being high, and transistors which may
25 acceptably run at slow speeds will have low electric power consumptions despite the
threshold voltages being high. In this way, with the electric power consumption of
the entire circuit being kept low, the transistors placed on the critical path will run at
high speeds.
3
[Citation List]
[Patent Literature]
[0008]
[Patent Literature I ]
5 Japanese Patent Application Publication No. 147-249067
[Patent Literature 2]
Japanese Patent Application Publication No. 2001345420
[Patent Literature 3]
Japanese Patent Application Publication No. 2006-146601
10 [Non-Patent Literature]
[0009]
[Non-Patent Literature 1]
Atsushi Iwata, "CMOS Shuselci-ICairo no Kiso," (in Japanese) I{agalku
Gijutsu Shuppan
15 [Summary of Invention]
[Technical Problem]
[0010]
With the demand for power conservation, power supply voltages have been
reduced in integrated circuits of recent years. In particular, along with thr further
20 miniaturization of circuit elements and traces, static electric power consumption,
namely, electric power consumption caused by leakage current, is growing. Due to
the factthat the leakage current increases in proportion to a power supply voltage,
greatly raising the power supply voltage is not desirable. Also, dynamic electric
power consumption, namely, electric power necessary for switching operation of a
25 transistor, is proportional to the power supply voltage squared. Accordingly, for
controlling transistor operating speeds while electric power consumption is kept
low, there is a need for technology that dynamically adjusts not just power supply
voltages, but transistor threshold voltages as well.
[0011]
However, the method described in Patent Literature 3 determines the
threshold voltage of each individual transistor at the design stage, so it is not
possible to dynamically adjust transistor threshold voltages. Alternatively, even
5 though the method described in Patent Literature 2 can keep the temperature of the
entire analog circuit constant despite a decrease in environmental temperature, it
would be difficult to go as far as to control the temperature of each individual
transistor to dynamically adjust its threshold voltage.
[0012]
10 It is an aim of the present invention to solve the above problems, and in
particular to provide an integrated circuit that reliably raises the operating speeds of
transistors by dynamically adjusting the threshold voltages of the transistors while
keeping electric power consumption low.
[Solution to Problem]
15 [0013]
An integrated circuit according to one aspect of the present invention is an
integrated circuit comprising a substrate , an electrode, two diffusion areas, and a
resistance heater. The substrate includes a first surface and a second surface that are
substantially parallel to each other. The electrode is laminated onto the first surface
20 of the substrate . The two diffusion areas are disposed within the substrate in the
vicinity of an electrode to form one transistor with the electrode. The resistance
heater is located on an area of the second surface across the substrate from the
electrode. The resistance heater is configured to produce heat by allowing electric
current to flow.
25 [0014]
In another aspect of the present invention, an integrated circuit comprises a
first substrate, an electrode, two diffusion areas, a second substrate and a resistance
heater. The first substrate includes a first surface and a second surface that are
5
substantially parallel to each other. The electrode is laminated onto the first surface
of the first substrate. The two diffusion areas are disposed within the first substrate
in the vicinity of an electrode to form one transistor with the electrode. The second
substrate is bonded to the second surface of the first substrate. The resistance heater
5 is located on an area of the second substrate opposite to an area of the second
surface across the first substrate from the electrode. The resistance heater is
configured to produce heat by allowing electric current to flow.
[Advantageous Effects of Invention]
[0015]
10 Both integrated circuits of the present invention use a resistance heater to
heat the transistors. By doing so, the integrated circuits can individually control the
temperatures of the transistors to dynamically adjust the threshold voltages thereof.
In this way, the integrated circuits can reliably raise the operating speeds of the
transistors higher whilst keeping electric power consumption low.
15 [Brief Description of Drawings]
[0016]
Fig. 1 is a layout diagram of a transistor and its-surroundings included in an
integrated circuit of Embodiment I of the present invention;
Fig. 2 is across-sectional diagram taken along the line I1- II shown in Fig. 1;
20 Fig. 3 is a graph which shows the relationship between the threshold voltage
and channel area temperature of a. typical MOS transistor;
Fig. 4A is a cross-sectional diagram showing the process of forming TSVs
121 in a substrate 110; Fig. 4B is a cross-sectional diagram showing the process of
laminating gate oxide films 103 and gate electrodes 103 onto a first surface 111 of
25 the substrate 110; Fig. 4C is a cross-sectional diagram showing the process of
forming diffusion areas;
Fig. 5A is a cross-sectional diagram showing the process of forming
sidewalls 105 and an interlayer insulating film 201. Fig. SB is a cross-sectional
6
diagram showing the process of forming contact holes 106, 107 and 122 in the
interlayer insulating film 201. Fig. 5C is a cross-sectional diagram showing the
process of forming multilayer traces 108, 109 and 123;
Fig. 6A is a cross-sectional diagram showing the process of polishing a
5 second surface 112 of the substrate 110; Fig. 6B is a cross-sectional diagram
showing the process of forming an insulating film 205 on the second surface 112 of
the substrate 110; Fig. 6C is a cross-sectional diagram showing the process of
forming a resistance heater 120 on the second surface 112 of the substrate 110;
Fig. 7 is a block diagram of an integrated circuit 700 of Embodiment 1 of
10 the present invention;
Fig. 8 is a flow chart for a situation where the integrated circuit 700 of
Embodiment 1 of the present invention controls the operating speed of each core
circuit;
Fig. 9 is a layout diagram of a transistor and its surroundings included in an
15 integrated circuit of Embodiment 2 of the present invention;
Fig. 10 is a cross-sectional diagram taken along the line X-X shown in Fig.
9;
Fig. 11A is a cross-sectional diagram showing the process of forming TSNs
121 in a substrate 1 10, Fig. 1 I B is a cross-sectional diagram showing the pr e css of
20 forming thermal insulators 130 in the substrate 110; Fig. 1IC is a cross-sectional
diagram showing the process of laminating gate oxide films 103 and gate electrodes
104 onto a first surface 111 of the substrate 110; Fig. III) is a cross-sectional
diagram showing the process of forming diffusion areas;
Fig. 12A is a cross-sectional diagram showing the process of forming
25 sidewalls 105 and an interlayer insulating film 201; Fig. 12B is a cross-sectional
diagram showing the process of forming contact holes 106, 107 and 122 in the
interlayer insulating film 201; Fig. 12C is a cross-sectional diagram showing the
process of forming multilayer traces 108, 109 and 123;
7
Fig. 13A is a cross-sectional diagram showing the process of polishing a
second surface 112 of the substrate 110; Fig. 13B is a cross-sectional diagram
showing the process of forming an insulating film 205 on the second surface 112 of
the substrate 110; Fig. 13C is a cross-sectional diagram showing the process of
5 forming a resistance heater 120 on the second surface 112 of the substrate 110;
Fig. 14 is a block diagram of an integrated circuit 900 of Embodiment 3 of
the present invention;
Fig. 15 is a flow chart for a situation where the integrated circuit 900 of
Embodiment 3 of the present invention controls the operating speed of each core
10 circuit;
Fig. 16 is a cross-sectional diagram showing the laminated structure of
transistors and their surroundings included in an integrated circuit of Embodiment 4
of the present invention;
Fig. 17A is a cross-sectional diagram showing the process of laminating
15 gate oxide films 103 and gate electrodes 104 onto a first surface 1111 of a first
substrate 1110; Fig. 17B is a cross-sectional diagram showing the process of
forming diffusion areas; Fig. 17C is a cross-sectional diagram showing the process
of forming sidewalk 105 and an interlayer insulating film 201;
Fig. 18A is a crass-sectional diagram showing the process of Inrming
20 contact holes 106, 107 and 122 in the interlayer insulating film 201; Fig, 18B is a
cross-sectional diagram showing the process of forming multilayer traces 108, 109
and 123; Fig, I8C is a cross-sectional diagram showing the process of polishing a
second surface 1112 of the first substrate 1110;
Fig. 19A is a cross-sectional diagram showing the process of forming a
25 resistance heater 1130 on a third surface 1121 of a second substrate 1120; Fig. 19B
is a cross-sectional diagram showing the process of forming an insulating film 1210
on the third surface 1121 of the second substrate 1120; Fig. 19C is a cross-sectional
diagram showing the process of forming TSVs 1131 in the second substrate 1120;
8
Fig. 1919 is a cross-sectional diagram showing the process of forming an interlayer
insulating film 1220 on a fourth surface 1122 of the second substrate 1120; Fig. HE
is a cross-sectional diagram showing the process of forming third contact holes 1132
and third traces 1133 on the interlayer insulating film 1220;
5 Fig. 20 is a cross-sectional diagram showing the laminated structure of
transistors and their surroundings included in an integrated circuit of Embodiment 5
of the present invention;
Fig. NA is a cross-sectional diagram showing the process of forming first
thermal insulators 130 in a first substrate 1110; Fig. 21B is a cross-sectional diagram
10 showing the process of laminating gate oxide films 103 and gate electrodes 104 onto
the first surface 1111 of the first substrate 1110; Fig. 21C is a cross-sectional
diagram showing the process of forming diffusion areas; Fig. 211 is a
cross-sectional diagram showing the process of forming sidewalls 105 and an
interlayer insulating film 201;
15 Fig. 22A is a cross-sectional diagram showing the process of forming
contact holes 106, 107 and 122 in the interlayer insulating film 201; Fig. 22B is a
cross-sectional diagram showing the process of forming 'multilayer traces 108, 109
and 123; Fig. 22C is a cross-sectional diagram showing the process of polishing the
second surface 1112 oFthefirst substrate 1110;
20 Fig. 23A is a cross-sectional diagram showing the process of forming a
resistance heater 1130 on a third surface 1121 of a second substrate 1120; Fig. 23B
is a cross-sectional diagram showing the process of forming an insulating film 1210
on the third surface 1121 of the second substrate 1120; Fig. 23C is a cross-sectional
diagram showing the process of forming second thermal insulators 1140 in the
25 second substrate 1120; Fig. 23D is a cross-sectional diagram showing the process of
forming TSVs 1131 in the second substrate 1120; Fig. 23E is a cross-sectional
diagram showing the process of forming an interlayer insulating film 1220 on a
fourth surface 1122 of the second substrate 1120; Fig. 23F is a cross-sectional
9
diagram showing the process of forming contact holes 1132 and third traces 1133 in
the interlayer insulating film 1220.
[Description of Embodiments]
[0017]
5 Embodiments of the present invention are described below with reference to
the drawings.
[0018]
[Embodiment 1]
[0019]
10 Transistor structure
[0020]
Fig. I is a layout diagram of a transistor and its surroundings included in an
integrated circuit of Embodiment 1 of the present invention. Fig. 2 shows a cross
section taken along the line It- 11 shown in Fig. 1. A transistor 100 is a MOS (Metal
15 Oxide Semiconductor) transistor. A distinguishing feature of the structure shown in
Figs. 1 and 2 is that a resistance heater 120 is placed across a substrate 110 from its
surface area where the transistor 100 is laminated.
[0021]
Referring to Fie. 2, the substrat e 110 includes a first surface 111 and second
20 surface 112 (the upper surface and lower surface respectively, in Fig. 2) that are
substantially parallel to each other. The transistor 100 is laminated to the first
surface Ill and includes a first diffusion area 101, a second diffusion area 102, a
gate oxide film 103, a gate electrode 104, sidewalls 105, a first contact hole 106, a
second contact hole 107, a first trace 108 and a second trace 109. The substrate 110
25 is formed of silicon (Si). The first diffusion area 101 and second diffusion area 102
are impurity-ion-doped areas in the first surface 1 I 1 of the substrate 110. One of the
diffusion areas is used as a drain and the other as a source. When the transistor 100
is an N type, donor impurities such as phosphor (P) are doped, and when the
10
transistor 100 is a P type, acceptor impurities such as boron (B) are doped. As
shown in Fig. 1, the diffusion areas 101 and 102 are rectangle-shaped, and as shown
in Fig. 2, a gap exists between them. This gap is covered by the gate oxide film 103.
The gate oxide film 103 is formed of silicon oxide (Si02) or high-dielectric constant
5 (1-ligh-1c) material. The gate electrode 104 is positioned on top of the gate oxide film
103, which electrically separates the gate electrode 104 from the diffusion areas 101
and 102. The gate electrode 104 is formed of polysilicon or metal material. As
shown in Fig. 1, the gate electrode 104 extends between the first diffusion area 101
and the second diffusion area 102, and is connected to an external power source (not
10 shown in Figs. 1 and 2). Referring to Fig. 2, the sidewalls 105 cover the sides of the
gate oxide film 103 and the gate electrode 104, and in particular electrically separate
the gate electrode 104 from the diffusion areas 101 and 102. The sidewalls 105 are
formed of silicon nitride (Si3N4). The first diffusion area 101, the second diffusion
area 102, the gate oxide film 103, the gate electrode 104, and the sidewalls 105 are
15 covered by interlayer insulating films 201, 202, 203 and 204. The interlayer
insulating films 201-204 are formed of silicon oxide or low-dielectric constant
(Low-k) material. The first contact hole 106 exposes the first diffusion area 101, and
the second contact hole 107 exposes the second diffusion area 102. The firs( trace
1 OS is connected to fhc first diffusion area 101 through the first contact hale 106,
20 and the second trace 109 is connected to the second diffusion area 102 through the
second contact hole 107. Note that in Fig. 1, the traces 10$ and 109 are shown by
dotted lines. The first trace 108 and the second trace 109 are made of aluminium or
copper. One of them is used as a drain electrode and the other one is used as a source
electrode.
25 [0022]
Referring further to Fig. 2, the second surface 112 of the substrate 110 is
covered with an insulating film 205. The insulating film 205 is formed of silicon
oxide. The resistance heater 120 is laminated to a part of the insulating film 205
1.1
covering the second surface 112. The part is positioned underneath the transistor 100.
The resistance heater 120 is formed of polysilicon or non-doped silicon with high
sheet resistance. As shown in Fig. 1, the resistance heater 120 has a long, thin
rectangular form which extends in a direction perpendicular to the gate electrode
5 104. Furthermore, two resistance heaters 120 are provided to one transistor 100. As
shown in Fig. 2, one TSV (Through-Silicon Via) 121 is formed on a part of the
substrate 110 facing each longitudinal end of the resistance heater 120. The TSVs
121 are filled with polysilicon. At the first surface I1 I of the substrate 110, the end
of the TSV 121 is exposed by a third contact hole 122. A third trace 123 is
10 connected to the TSV 121 through the third contact hole 122. The third trace 123 is
formed of aluminium or copper. Note that in Fig. 1, the third trace 123 is shown by
dotted lines. Because the resistance value of the resistance heater 120 is greater than
that of the third trace 123, a comparatively great Joule beat arises when electric
current flows to the resistance heaters 120 by way of the third trace 123. In this way,
15 it is possible to heat the transistor 100, in particular its channel area, by using the
resistance heaters 120.
[0023]
The resistance heaters 120 are placed underneath those transistors 100
which belong to a critical path. This enables those transistors to be selectively heated
ieir te.nip^, it^^.:, ^_ha :` ^I,osc ,^l'o her ( m -^slors. kt'e, +.^<< i«uv
speaking, transistors under a high temperature condition have lower threshold
voltages than transistors under a low temperature condition. Fig. 3 is a graph which
shows the relationship between the threshold voltage and channel area temperature
of a typical MOS transistor. Referring to Fig. 3, the threshold voltage falls roughly
25 in proportion to the rising of the channel area temperature. For example, the
threshold voltage Vth2 at 100 degrees Celsius is lower than the threshold voltage
Vthl at 0 degrees Celsius. (Both threshold voltages Vthl and Vth2 are around
IV-3V.) Due to this characteristic, raising the temperature of transistors on a critical
12
path higher than the temperature of other transistors enables the transistors on the
critical path to operate at faster speeds than the other transistors even though all the
transistors share a common power supply voltage. Furthermore, by allowing electric
current to flow to the resistance heaters only during the time period when high speed
5 operation is necessary, it is possible to suppress the increase of electric power
consumption to the minimum requirement. In this way, by using the structure shown
in Figs. 1 and 2, it is possible to dynamically adjust the transistor threshold voltages.
Note that a dutailed description of the adjustment method will be described later.
[0024]
10 Transistor laminating process
[0025]
Figs. 4-6 show the laminating process of the structure shown in Figs. I and
2. All transistors included in the integrated circuit of Embodiment 1 of the present
invention have been laminated with a similar process.
15 [0026]
Fig. 4A is a cross-sectional diagram showing the process of forming the
TSVs 121 in the substrate 110. First, the first surface 111 of the substrate 110 is
covered with a photoresist 401, which is exposed to light in the pattern of the TSVs
121. As a result, parts of the photoresist are removed from the areas where the TSVs
20 121 are to be formed , and then holes 402 appear. Next, using the remaining
t 4Ul. as l ma sk, f 1^. (1''e Ctive TOR itching) is p ert rm.'ad n.,is
of the substrate 110 which are exposed vias the holes 402 of the photoresist and then
form vias 403 (Refer to the dotted line sections of Fig. 4A ). The arrows RI1 shown
in Fig. 4A indicate ion current used in the RIE. Following that, after the photoresist
25 401 are removed from the entirety of the first surface 1 1 1, an insulating film is
formed by using CVD (Chemical Vapor Deposition) to coat the inner surfaces of the
vias 403 with silicon oxide . Subsequently, CVD is further used to fill the vias 403
with polysilicon . At this point, polysilicon will be protruding out from the upper
ends of the vias 403. Accordingly , after the vias 403 are filled with polysilicon, the
13
first surface 111 is polished with CMP (Chemical Mechanical Polish), which
removes the polysilicon protruding from the upper ends of the vias 403 to flatten the
first surface 111. In this way, the TSVs 121 are formed.
[0027]
5 Fig. 4B is a cross-sectional diagram showing the process of laminating the
gate oxide films 103 and gate electrodes 104 onto the first surface 111 of the
substrate 110. After the TSVs 121 are formed, first the entirety of the first surface
111 is thermally oxidized to be covered with a layer of silicon oxide. Next,
polysilicon is accumulated on the entirety of the silicon oxide layer by 1.PCVD
10 (Low Pressure CVD). Following that, the entirety of this polysilicon layer is coated
with a photoresist and exposed to light in the pattern of the gate electrodes 104. With
this, the photoresist is removed from all but the areas where the gate electrodes
104 are to be formed. Next, using the remaining photoresist as a mask, RIB is
performed to remove the superfluous silicon oxide and polysilicon from the first
15 surface 111, and then form the gate oxide films 103 and the gate electrodes 104.
Finally, the remaining photoresist is removed.
[0028]
Fig. 4C is a cross-sectional diagram showing the process of forming the
diffusic,n areas. With this process, the gate electrodes 104 are used as a mask, and
20 impurity ions such as boron or phosphor are infused into the first surface I I1 of the
substrate 110. The arrows IMP shown in Fig. 4C indicate the infusion ion current. In
this way, the diffusion areas 101 and 102 are thinly formed on either side of each of
the gate electrodes 104.
[0029]
25 Fig. 5A is a cross-sectional diagram showing the process of forming the
sidewalls 105 and the interlayer insulating film 201. After the diffusion areas 101
and 102 are formed, first the entirety of the first surface l I l of the substrate 110 is
covered with a layer of silicon nitride by LPCVD. Next, anisotropic etching is
14
performed so that the silicon nitride layer remains only on the sides of the gate oxide
films 1.03 and the gate electrodes 104. By doing so, the sidewalls 105 are formed.
Following that, using the gate electrodes 104 and the sidewalls 105 as a mask,
impurity ions such as boron or phosphor are additionally infused into the first
5 surface 111. As a result, the thickness of the diffusion areas 101 and 102 increases
on the outer sides of the sidewalls 105 . In this way, the sidewalls 105 function as a
spacer to reliably separate the diffusion areas 101 and 102 from the gate electrode
104. After the impurity ions are infused, the entirety of the first surface 111 is
covered with a silicon oxide coating to form the interlayer insulating film 201
10 [0030]
Fig. 5B is a cross-sectional diagram showing the process of forming the
contact holes 106, 107 and 122 in the interlayer insulating film 201. First, the
entirety of the interlayer insulating film 201 is covered with a photoresist, and
exposed to light in the pattern of the contact holes 106, 107 and 122. By doing so,
15 parts of the photoresist are removed from the areas where the contact holes 106, 107
and 122 should be formed, and then holes appear. Next, using the remaining
photoresist as a mask, RIE is performed to remove parts of the interlayer insulating
film 201 which are exposed through the holes of the photoresist and then deepen the
holes. Following that, CVD is used to lilt the insides of the holes with aluminium,
20 tungsten, or copper. At this point, the metal will be protruding out from the upper
ends of the holes. Accordingly, after the holes are filled with the metal, the surface
of the interlayer insulating film 201 is polished with CMP, which removes the metal
protruding from the upper ends of the holes to flatten the surface of the interlayer
insulating film 201. In this way, the contact holes 106, 107 and 122 are formed.
25 [0031]
Fig. 5C is a cross-sectional diagram which shows the process of forming
multilayer traces 108, 109 and 123. First, the entirety of the interlayer insulating film
201 is covered with a silicon oxide layer 202 by CVD. Next, the entirety of the
15
silicon oxide layer 202 is covered with a photoresist, and is exposed to light in the
pattern of the traces 108, 109 and 123 as indicated by the dotted lines shown in Fig.
1. By doing so, parts of the photoresist are removed from the areas where the traces
108, 109 and 123 should be formed, and then holes appear. Next, using the
5 remaining photoresist as a mask, RIE is performed to remove the parts of the silicon
oxide layer 202 which are exposed vias the holes of the photoresist and then deepen
the holes. Following that, plating or spattering is used to fill the insides of the holes
with aluminium or copper. At this point, the metal will be protruding out from the
upper ends of the holes. Accordingly, after the holes are filled with the metal, the
10 surface of the silicon oxide layer 202 is polished with CMP, which removes the
metal protruding from the upper ends of the holes to flatten the surface of the silicon
oxide layer 202. By doing so, the traces 108, 109 and 123 within the silicon oxide
layer 202 are formed. After that, each time one of the silicon oxide layers 203 and
204 are newly laminated, a similar process is repeated. In this way, the multilayer
15 traces shown in Fig. 5C are formed,
[0032]
Fig. 6A is a cross-sectional diagram showing the process of polishing the
second surface 112 of the substrate 110 . After formation of the structure on the first
surface 111 of the suhstrate 110 as shown in Fig. 5C is completed, polishinh of the
20 second surface 112 is carried out with CMF. 'I he arrows CMF shown in Fig. 6A
show the direction in which the thickness of the substrate 110 changes with the CMF.
The CMP is repeated several times while the roughness of the polishing is altered in
several steps. With this, the thickness of the substrate 110 decreases to a range of
several micrometers to several dozens of micrometers . As a result, the TSVs 121 are
25 exposed at the second surface 112 as shown in Fig. 6A.
[0033]
Fig. 6B is a cross-sectional diagram showing the process of forming the
insulating film 205 on the second surface 112 of the substrate 110. After the
16
polishing process shown in Fig. 6A is completed, first a silicon oxide layer 205 is
accumulated on the entirety of the second surface 112 with CVD. Next, the entirety
of the silicon oxide layer 205 is covered with a photoresist and exposed to light in
the pattern of the TSVs 121. By doing so, parts of the photoresist are removed from
5 the areas where the ends of the TSVs 121 were exposed, and then holes are formed.
Next, using the remaining photoresist as a mask, RIE is performed to remove the
parts of the silicon oxide layer 205 exposed vias the holes in the photoresist and then
deepen the holes. Following that, the insides of the holes are filled with polysilicon
by CVD. At this point, polysilicon will be protruding out from the upper ends of the
10 holes. Accordingly, after the holes are filled with polysilicon, the surface of the
silicon oxide layer 205 is polished with CVIP, which removes the polysilicon
protruding from the upper ends of the holes to flatten the surface of the silicon oxide
layer 205. By doing so, the ends of the TSVs 121 are re-exposed along with the
formation of the insulating film 205.
15 [0034]
Fig. 6C is a cross-sectional diagram that shows the process of forming the
resistance heaters 120 on the second surface 112 of the substrate 110. First,
polysilicon is accumulated on the entirety of the insulating film 205 with LPCVD.
Next, the entirety of the polysilicon layer is covered with a photoresist, which is
20 exposed to light in the pattern of the resistance heaters 120 . By doing so, the
photoresist is removed from the entire polysilicon layer except where the resistance
heaters 120 should be formed. Next, using the remaining photoresist as a mask, RIE
is performed to remove superfluous polysilicon from the surface of the insulating
film 205 and then form the resistance heaters 120. Finally, the remaining photoresist
25 is removed.
[0035]
'The transistors to be heated with the resistance heaters 120 are selected by a
simulation at the layout design stage. The reason for this is as follows. As shown in
1'7
Fig. 3, generally when the temperature of a transistor is higher, the threshold voltage
thereof is lower. However, since the electron mobility is lower when the temperature
is higher, it is not necessarily true that, if the temperature of a transistor is high, its
operating speed is bound to rise, in view of the power supply voltage and circuit
5 structure, etc., of the transistor. Accordingly, after an actual simulation, only
transistors whose operating speeds actually rise with rise in temperature are selected.
One specific example is series P-type MOS transistors. Note that a resistance heater
may be placed on the back side of every transistor without carrying out any
simulations.
10 [0036]
Integrated circuit structure
[0037]
Fig. 7 is a block diagram of an integrated circuit 700 of Embodiment 1 of
the present invention. The integrated circuit 700 is a system LSI of a digital
15 television. Alternatively, the integrated circuit 700 may be a system LSI
implemented in one of various electronic equipments such as BD (Blu-ray Disc)
recorders, digital cameras, cellular telephones, etc., Referring to Fig. 7, the
integrated circuit 700 is broadly divided into a core circuit assembly 710 and a
control system 720-760. These are implemented in a single substrate. Each of the
20 1-ru oirc site 70 r /0 , 7uJ', 1s Iuo c uitli di_g an i ,itvhlua eu n
incorporated as a general-purpose processor or specialized hardware. The core
circuits may be, for example, a decoder 701, a digital signal processor (DSP) 702, a
CPU, a GPU, etc., Among transistors which make up the core circuits 701, 702,
703, ..., the transistors which belong to a critical path have the structure shown in
25 Figs. 1 and 2, especially including resistance heaters 704 and 705. The control
system 720-760 is a circuit group for operating the core circuits '701, 702, 703, ...
appropriate to use cases, and comprises a system control unit 720, a memory control
unit '730, a frequency control unit 740, a heater control unit '750, and a temperature
18
detection unit 760.
[0038]
The system control unit 720 is composed of a general-purpose CPU and
operates a core circuit appropriate to a use case at appropriate settings. Specifically,
5 the system control unit 720 first either monitors signals UO which show user
operation such as remote control operation, etc., or use a stream parser to analyze
stream data VS of images, etc., inputted from outside. When the system control unit
720 detects -arequest for changing use cases from user operation or the results of the
stream parser analysis, the system control unit 720 sends instructions INS to various
10 core circuits. For example, let us suppose that a user changes a viewing target 'from a
terrestrial digital television broadcasting program to online video content. When the
user presses the network switch on a remote control during viewing of the program,
the system control unit 720 detects a signal UO from the remote control and
performs the following series of processes. First, the system control unit 720 selects
15 and activates a network interface circuit from within the core circuit assembly 710
and begins preparations for receiving the video content from a network. Next, the
system control unit 720 stops a stream processing circuit within the core circuit
assembly 710; the stream processing circuit is used for displaying the
aforementioned program. Furthermore, the system control unit 720 cmccs the
20 memory control unit 730 to alter a bandwidth of the external memory MR that
should be allocated to each core circuit. Here, the external memory MR is a memory
element attached to the integrated circuit 700, and includes a frame memory in
particular.
[0039]
25 The memory control unit 730 mediates access to the external memory MR
by each core circuit '701, 702, 703, ... In particular, the memory control unit 730
complies with instructions from the system control unit 720 to adjust, according to
use cases, a bandwidth of the external memory MR that should be allocated to each
19
core circuit.
[0040]
The frequency control unit 740 complies with instructions from the system
control unit 720 to control the operating frequency of each core circuit according to
5 use cases. For example, if only displaying of a recorded program is to be performed,
the frequency control unit 740 sets the operating frequency of the decoder 701 to
100 MHz. If transcode recording of one and two background programs is to be
performed along with the displaying of a recorded program, then the frequency
control unit 740 sets the operating frequency of the decoder 701 to 200 MHz and
10 300 MHz, respectively. Alternatively, if a viewing target is changed from HD
(High-Definition) images of terrestrial digital television broadcasting to 4K2K
images distributed over networks, the frequency control unit 740 raises the operating
frequencies of both the decoder 701 and the DSP 702. Because 4K2K resolution is
four times as high as HD resolution, 4K2K processing necessitates higher operating
15 speeds for the decoder 701 and DSP 702, compared to HD processing. The
relationship between the use cases and the operating frequencies is tabulated and
saved in advance in the frequency control unit 740. The frequency control unit 740
also includes a timer 741, and using this, determines timings for actually altering
operating frequencies,
20 [0041]
The heater control unit 750 applies electric current to the resistance heaters
704 and 705 within each of the core circuits 701, 702, 703, ..., and adjusts the
amount of that electric current in accordance with use cases . Here, electric current
flowing to each resistance heater within a single core circuit is maintained at the
25 same level. The heater control unit 750 includes a use case change monitoring unit
751, a current source 752, a plurality of switches 753A, 753B, 7530, ..., and a
temperature monitoring unit 754.
[0042]
20
The current source 752 uses a fixed power supply voltage to generate
electric current to a predetermined amount. The amount of the electric current may
be fixed or adjustable. The plurality of switches 753A, 753B, 753C, ... are connected
individually to different core circuits. The switches either allow or block
5 connections between the current source 752 and the resistance heaters 704 and 705
within the core circuits. In the example shown in Fig. 7, while the first switch 753A
is ON, electric current flows between the current source 752 and the resistance
heater 704 within the decoder 701. While the second switch 753B is ON, electric
current flows between the current source 752 and the resistance heater 705 within
10 the DSP 702.
[0043]
The use case change monitoring unit 751 monitors the instructions INS sent
from the system control unit 720 to the core circuit assembly 710 and analyzes the
use case change pattern from the instructions INS. Based on the results of the
15 analysis, the use case change monitoring unit 751 furthermore selects a core circuit
where electric current should flow to resistance heaters. For example, if the viewing
target is changed from HD images of terrestrial digital television broadcasting to
41(2K images distributed over networks, the decoder 701 and DSP 702 should be
selected. The relationship between use cases and core circuits to be selected is
20 tabulated and saved in advance in the use case change monitoring unit 751. 'the use
case change monitoring unit 751 next turns ON, among the switches 753A, 753B,
753C, the switch that is connected to the selected core circuit. With this, electric
current flows between the resistance heaters within the selected core circuit and the
current source 752. When the current source 752 maintains the amount of the
25 electric current at a fixed level, the use case change monitoring unit 751 controls the
duty ratio of the switch (the ratio of ON time to the total time) to regulate the
amount of the time when the electric current is flowing continuously to the
resistance heaters. With this, the average amount of the electric current flowing to
21
the resistance heaters can be regulated. Alternatively, when the current source 752
can vary the amount of electric current, the use case change monitoring unit 751
adjusts the amount of the electric current flowing to the resistance heaters using the
current source 752. In this way, the amount of the electric current flowing to the
5 resistance heaters is adjusted.
[0044]
At the same time as turning one of the switches ON, the use case change
monitoring unit 751 also sets the timer 741 in the frequency control unit 740 to a
preheating time Tth, and starts up the timer 741. The preheating time Tth is the time
10 required for the resistance heater in the selected core circuit to raise the temperature
of a transistor to reach a desired value from the moment the switch is turned ON.
For example, in the case that only displaying of a recorded program is to be
performed, the use case change monitoring unit 751 sets the preheating time Tth to
500 milliseconds. With this, the transistor temperature reaches 50 degrees Celsius.
15 In the case that, alongside displaying of a recorded program, recording of one and
two other background programs is to be performed, the use case change monitoring
unit 751 sets the preheating time Tth to 700 milliseconds and 1000 milliseconds,
respectively. With this, the transistor temperature reaches 60 degrees Celsius and 70
degrees Celsius, respectively. The relationship between the use case chane*r pattern
20 and the preheating time l'th is tabulated and saved in advance in the use case change
monitoring unit 751. When the frequency control unit 740 detects the elapse of the
preheating time Tth with the timer 741, it raises the operating frequency of the core
circuit selected by the use case change monitoring unit 751. At this time, the
temperature of transistors on a critical path of the core circuit will be sufficiently
25 high, and thus the operating speeds of the transistors will be sufficiently high.
Accordingly, the core circuit will reliably have a high operating speed.
[0045]
The temperature monitoring unit 754 monitors the temperature of each part
22
of the core circuit assembly 710 detected by the temperature detection unit 760.
Furthermore, in the case that the temperature of the core circuit selected by the use
case change monitoring unit 751 or the temperature of its surrounding area exceeds a
predetermined pennissible range, the temperature monitoring unit 754 turns the
5 switch connected to that core circuit OFF. Subsequently, when the temperature falls
below the permissible range, the switch connected to that core circuit is turned ON
again . Here, the permissible range is set by the use case change monitoring unit 751
in accordance with use cases. For example, in the case that only displaying of a
recorded program is to be performed , the permissible range is set at 50 degrees
10 Celsius plus or minus a few degrees. In the case that, along with the displaying of a
recorded program, recording of one and two other background programs is to be
performed, the permissible range is set at 60 degrees Celsius plus or minus a few
degrees, and 70 degrees Celsius plus or minus a few degrees, respectively. The
relationship between use cases and the permissible range is tabulated and saved in
15 advance in the temperature monitoring unit 754.
[0046]
The temperature detection unit 760 is installed in each part of the core
circuit assembly 710 and detects the temperature therein. Specifically, the
temperature detection unit 760 includes resistors embedded in or around Ow core
20 circuits 701, 702, 703, ..., a power source which sends electric current to each
resistor individually, and a circuit which measures the amount of the electric current
which flows to each resistor. Because the amount of the electric current changes
according to the temperature of the resistor, the temperature detection unit 760
determines the temperature of the resistor from the measured value of the electric
25 current.
[0047]
Control of core circuit operating speeds
[0048]
23
Fig. 8 is a flow chart for a situation where the integrated circuit 700 of
Embodiment 1 of the present invention controls the operating speed of each core
circuit. This control is begun when the system control unit 720 detects a use case
change request from user operation or a stream parser analysis result.
5 [0049]
In step S801, the use case change monitoring unit 751 monitors instructions
INS which are sent from the system control unit 720 to each core circuit. The use
case change monitoring unit 751 determines from the instructions INS whether or
not a use case change request shows a change of a viewing target from a terrestrial
10 digital television broadcasting program to online video content. If the use case
change request shows such a change, the process proceeds to step 5802. If the use
case change request does not show this kind of change, the process repeats step
5801 again.
[0050]
15 In step 5802, the use case change monitoring unit 751 turns the switch
753A connected to the decoder 701 ON. With this, electric current begins to flow
between the current source 752 and the resistance heater 704 within the decoder 701.
Subsequently, the process proceeds to step S803.
[0051]
20 In step 5803, the use case change monitoring unit 751 retrieves from the
table a preheating time Tth for the startup of the decoder 701, and sets the timer 741
to the preheating time Tth. The use case change monitoring unit 751 then starts the
timer 741. With this, the timer 741 starts timing. Subsequently, the process proceeds
to step S804.
25 [0052]
In step S804, the frequency control unit 740 monitors the output of the timer
741. When the output shows the elapse of the preheating time Tth from the moment
of startup, the process proceeds to step S805.
24
[0053]
In step 5805, the frequency control unit 740 raises the operating frequency
of the decoder 701. With this, the operating speed of the decoder 701 rises.
Subsequently, the process proceeds to step S806.
5 [0054]
In step 5806, the temperature monitoring unit 754 monitors the temperature
of the decoder 701 or its surrounding area. If the temperature exceeds the
permissible range, the process proceeds to step S807. If the temperature does not
exceed the permissible range, the process proceeds to step S808.
10 [0055]
In step S807, the temperature monitoring unit 754 turns the switch 753A
that is connected to the decoder 701 OFF to stop electric current flowing to the
resistance heaters 704 within the decoder 701. Alternatively, the temperature
monitoring unit 754 lowers the duty ratio of the switch 753A to reduce the electric
15 current flowing to the resistance heaters '704. Subsequently, the process proceeds to
step 5810.
[0056]
In step S808, the temperature monitoring unit 754 determines whether or
not the temperature of the decoder 701 or its surrounding area has fallen below the
20 permissible range. If the temperature has fallen below the permissible range, the
process proceeds to step S809 . If the temperature is within the permissible range, the
process proceeds to step S810.
[0057]
In step S809, the temperature monitoring unit 754 turns the switch 753A
25 that is connected to the decoder 701 ON to allow electric current to flow once again
to the resistance heaters 704 within the decoder 701. Alternatively, the temperature
monitoring unit 754 raises the duty ratio of the switch 753A to increase the amount
of electric current flowing to the resistance heaters 704 within the decoder 701.
25
Subsequently, the process proceeds to step 5810.
[0058]
In step 5810, the system control unit 720 determines whether or not to
continue the operation of each core circuit. If the operation is to be continued, the
5 process is repeated from step S806. If the operation is to be ceased, the system
control unit 720 ceases the operation of the frequency control unit 740 and the heater
control unit 750. With this, the process ends.
[0059]
The integrated circuit 700 of Embodiment 1 of the present invention adjusts,
10 using the resistance heaters, the temperature of a core circuit, in particular the
temperature of transistors on a critical path, to a suitable value in accordance with
use cases, as shown above. As a result , the threshold voltages of the transistors are
adjusted to a suitable value; therefore it is possible to balance the operating speed
and electric power consumption of the core circuit. For example, the integrated
15 circuit raises the operating frequencies of the decoder 701 and the DSP 702 higher
when displaying online video content than when displaying a terrestrial digital
television broadcast, and accordingly allows electric current to flow to resistance
heaters of the decoder 701 and the DSP 702. Thus, the temperature of transistors on
critical paths of the decoder 701 and the DSP 702 increases and accordingly their
20 threshold voltages decrease, and therefore their operating speeds reliably rise. On the
other- hand , the integrated circuit keeps the operating frequencies of the decoder 701
and the DSP 702 comparatively low when displaying a terrestrial digital television
broadcast, and accordingly stops the electric current flowing to resistance heaters of
the decoder 701 and the DSP 702. Thus, the temperature of the critical path
25 transistors is kept comparatively low, and their threshold voltages are kept
comparatively high. As a. result, leakage current reduces, and therefore it is possible
to suppress the electric power consumption of the decoder 701 and the DSP 702. In
this way, the integrated circuit 700 dynamically controls the operating speeds of the
26
core circuits to achieve both a reduction in electric power consumption and an
increase in operating speed.
[0060]
[Embodiment 2]
5 [0061]
Fig. 9 is a layout diagram of a transistor and its surrounding area included in
an integrated circuit of Embodiment 2 of the present invention. Fig. 10 is a
cross-sectional diagram taken along the line X-X shown in Fig. 9. The structure
shown in Figs. 9 and 10 differs from the structure of Embodiment I shown in Figs. 1
10 and 2 in that a transistor 100 is surrounded by a thermal insulator 130 and thermally
isolated from its external areas. Since other elements of Embodiment 2 are similar to
those of Embodiment 1, the following explanation will mainly describe
modifications from Embodiment 1. A description about the similar elements may be
found in the explanation about Embodiment 1.
15 [0062]
Referring to Fig. 9, the transistor 100 is surrounded by the rectangular
frame-shaped thermal insulator 130. Referring to Fig. 10, the thermal insulator 130
is placed between each of the diffusion areas 101 and 102 and each of the TSVs 121
so as to separate the substrate 110. The thermal insulator 130 is formed of material
20 such as silicon oxide that has lower conductivity than silicon and aluminium, and
does not pollute peripheral materials (in other words, does not cause any
contamination of the peripheral materials). The thermal insulator 130 may
alternatively be in a region where air or nanomaterials have been trapped in the
substrate 110. Joule heat produced by the resistance heater 120 is blocked by the
25 thermal insulator 130, and thus hardly propagates to the outside. Accordingly, it is
possible to further improve efficiency when selectively heating the transistor 100 by
using the resistance heater 120.
[0063]
27
Transistor laminating process
[0064]
Figs 11-13 show the laminating process of the structure shown in Figs. 9
and 10. All transistors included in the integrated circuit of Embodiment 2 of the
5 present invention have been laminated with a similar process.
[0065]
Fig. I I A is a cross-sectional diagram showing the process of forming the
TSVs 121 in the substrate 110. The process shown in Fig. I IA is similar to that
shown in Fig. 4A. First, the first surface 111 of the substrate 1 10 is covered with a
10 photoresist 401, which is exposed to light in the pattern of the TSVs 121 to include
holes 402. Next, using the remaining photoresist as a mask, RTE is performed to
remove parts of the substrate 110 which are exposed through the holes 402 of the
photoresist and then vias 403 are formed. Following that, after the photoresist 401
are removed from the entirety of the first surface 111, OLD is used to form
15 insulating films by coating the inner surfaces of the vias 403 with silicon oxide.
Subsequently, CVD is further used to fill the vial 403 with polysilicon. Next, the
first surface 111 is polished with CMP, which removes the polysilicon protruding
from the upper ends of the vias 403 and to flatten the first surface I1 1. In this way,
the TSVs 121 are formed.
20 [0066]
Fig. 11B is a cross-sectional diagram showing the process of forming the
thermal insulators 130 in the substrate 110. After the TSVs 121 are formed, the first
surface tll of substrate 110 is first covered again with the photoresist 404 and
exposed to light in the pattern of the thermal insulators 130. Then, parts of the
25 photoresist 404 are removed from the areas where the thermal insulators 130 are to
be formed, and thus holes 405 appear. Next, using the remaining photoresist as a
mask, RIE is performed to remove parts of the substrate 110 which are exposed
through the holes 404 and then form trench-shaped vias 406 (see the dotted line
28
sections of Fig 1113). The arrows R12 shown in Fig. 1113 indicate ion current used in
the RIE. Subsequently, after the photoresist 404 are removed from the entirety of the
first surface 111, the insides of the vias 406 are filled with silicon oxide by CVD. At
this point, silicon oxide will be protruding out of the upper ends of the vias 406.
5 Accordingly, after the vias 406 are filled with silicon oxide, the first surface 111 is
polished with CMP, which removes the silicon oxide protruding from the upper ends
of the vias 406 to flatten the first surface 111. In this way, the thermal insulators 130
are formed.
[0067]
10 Fig. 11 C is a cross-sectional diagram showing the process of laminating the
gate oxide films 103 and the gate electrodes 104 onto the first surface I I I of
substrate 110. The process shown in Fig. I IC is similar to that shown in Fig. 4B.
After the thermal insulators 130 are formed, first the entirety of the first surface 111
is thermally oxidized to be covered with a layer of silicon oxide. Next, polysilicon is
15 accumulated on the entirety of the silicon oxide layer by LPCVD. Following that,
the entirety of this polysilicon layer is coated with a photoresist, and exposed to light
in the pattern of the gate electrodes 104. By doing so; the photoresist is removed
from all but the areas where the gate electrodes 104 should be formed. Using the
remaining photoresist as a mask, RTE is performed to remove the superfluous silicon
20 oxide and polysilicon from the first surface I11, and then form the gate oxide films
103 and the gate electrodes 104. Finally, the remaining photoresist is removed.
[0068]
Fig. 11D is a cross-sectional diagram showing the process of forming the
diffusion areas. The process shown in Fig. I ID is similar to that shown in Fig. 4C.
25 The gate electrodes 104 are used as a mask, and impurity ions such as boron or
phosphor are infused into the first surface I11 of the substrate 110. In this way, the
diffusion areas 101 and 102 are thinly formed on either side of each of the gate
electrodes 104.
29
[0064]
Fig. 12A is a. cross-sectional diagram showing the process of forming the
sidewalls 105 and the interlayer insulating films 201. She process shown in Fig. 12A
is similar to that shown in Fig. 5A. After the diffusion areas 101 and 102 are formed,
5 first the entirety of the first surface 111 of the substrate 110 is covered with a layer
of silicon nitride by LPCVD. Next, anisotropic etching is performed so that the
silicon nitride layer remains only on the sides of the gate oxide films 103 and the
gate electrodes 104. By doing so, the sidewalls 105 are formed. Following that,
using the gate electrodes 104 and the sidewalls 105 as a mask, impurity ions such as
10 boron or phosphor are additionally infused into the first surface 111. As a result, the
thickness of the diffusion areas 101 and 102 increases on the outer sides of the
sidewalls 105. After the impurity ions are infused, the entirety of the first surface
111 is covered with a silicon oxide coating to form the interlayer insulating film
201.
15 [0070]
Fig. 12B is a cross-sectional diagram showing the process of forming the
contact holes 106, 107 and 122 in the interlayer insulating film 201. The process
shown in Fig. 12B is similar to that shown in Fig. 5B. First, the entirety of the
interlayer insulating Film 201 is covered with a photoresist, and exposed to light in
20 the pattern of the contact holes 106, 107 and 122, and then holes are formed. Next,
using the remaining photoresist as a mask, RIB is performed to remove parts of the
interlayer insulating film 201 which are exposed through the holes of the photoresist
and then deepen the holes. Following that, CVD is used to fill the insides of the
holes with aluminum, tungsten, or copper. Afterwards, the surface of the interlayer
25 insulating film 201 is polished with CMP, which removes the polysilicon protruding
from the upper ends of the holes to flatten the surface of the interlayer insulating
film 201. In this way, the contact holes 106, 107 and 122 are formed.
[0071]
30
Fig. 12C is a. cross-sectional diagram showing the process of forming the
multi layer traces 108, 109 and 123. The process shown in Fig. 12C is similar to that
shown in Fig.. SC. First, the entirety of the interlayer insulating film 201 is covered
with a silicon oxide layer 202 by CVl3. Next, the entirety of the silicon oxide layer
5 202 is covered with a photoresist, and is exposed to light in the pattern of the traces
108, 109 and 123 as indicated by the dotted lines shown in Fig. 1, and then holes are
formed. Next, using the remaining photoresist as a mask, RIE is performed to
remove the parts of the silicon oxide layer 202 which are exposed through the holes
of the photoresist and then deepen the holes. Following that, plating or spattering is
10 used to fill the insides of the holes with aluminum or copper. Afterwards, the surface
of the silicon oxide layer 202 is polished with CMP, which removes the metal
protruding from the upper ends of the holes to Fatten the surface of the silicon oxide
layer 202. In this way, the traces 108, 109 and 123 within the silicon oxide layer 202
are formed. After that, each time one of the silicon oxide layers 203 and 204 are
15 newly laminated, a similar process is repeated. In this way, the multilayer traces
shown in Fig. 12C are formed.
[0072]
Fig. 13A is a cross-sectional diagram showing the process of polishing the
second .surface 112 of the substrate 110. The process shown in Fig. 13A. is similar to
20 that shown in Fig. 6A. After formation of the structure on the first surface 111 of the
substrate 110 shown in Fig. 12C is completed, polishing of the second surface 112 is
carried out with CMP. With this, the thickness of the substrate I10 decreases to a
range of several micrometers to several dozens of micrometers . As a result, the
TSVs 121 and the thermal insulators 130 are exposed at the second surface 112 as
25 shown in Fig. 13A.
[0073]
Fig. 13B is a cross-sectional diagram showing the process of forming the
insulating film 205 on the second surface 112 of the substrate I10. The process
31
shown in Fig. 13B is similar to that shown in Fig. 613. After the polishing process
shown in Fig. 13A is completed, first a silicon oxide layer 205 is accumulated on the
entirety of the second surface 112 with CVD. Next, the entirety of the silicon oxide
layer 205 is covered with a photoresist and exposed to light in the pattern of the
5 TSVs 121, and then holes are formed. Next, using the remaining photoresist as a
mask, RIE is performed to remove the parts of the silicon oxide layer 205 exposed
through the holes in the photoresist and then deepen the holes. Following that, the
insides of the holes are filled with polysilicon by CVD. Afterwards, the surface of
the silicon oxide layer 205 is polished with CMP, which removes the polysilicon
10 protruding from the upper ends of the holes to flatten the surface of the silicon oxide
layer 205. In this way, the ends of the TSVs 121 are re-exposed along with the
formation of the insulating film 205.
[0074]
Fig. 13C is a cross-sectional diagram that shows the process of forming the
15 resistance heaters 120 on the second surface 112 of the substrate 110. The process
shown in Fig. 13C is similar to that shown in Fig, 6C. First, polysilicon is
accumulated on the entirety of the insulating film 205 with LPCVD. Next, the
entirety of the polysilicon layer is covered with a photoresist, which is exposed to
light in the pattern o(- he resistance heaters 120. Then, the photoresist is removed
20 from all of the polysilicon layer except the parts where the resistance heaters 120
should be formed. Next, using the remaining photoresist as a mask, RIE is
performed to remove superfluous polysilicon from the surface of the insulating film
205 and then form the resistance heaters 120. Finally, the remaining photoresist is
removed.
25 [0075]
[Embodiment 3]
[0076]
Fig. 14 is a block diagram of an integrated circuit 900 of Embodiment 3 of
32
the present invention. The integrated circuit 900 differs from the integrated circuit
700 of Embodiment I shown in Fig. 7 in that the heater- control unit 750 is provided
with a memory access monitoring unit 951 instead of the use case change
monitoring unit 751. Other elements are similar to those of the integrated circuit 700
5 shown in Fig. 7. Accordingly, the following explanation will mainly describe
additions and modifications from Embodiment 1. A description of the similar
elements may be found in the explanation about Embodiment 1.
[0077]
The memory access monitoring unit 951 monitors requests for access to the
10 external memory MR which the memory control unit 730 receives from each core
circuit 701, 702, 703, ... In particular, the memory access monitoring unit 951
detects the frequency of access to the external memory MR by each core circuit, in
other words, the bandwidth of the external memory MR allocated to each core
circuit, The memory access monitoring unit 951 furthermore selects a core circuit
15 which has been allocated a comparatively high bandwidth. The memory access
monitoring unit 951 next turns ON, among the switches 753A, 753B, 7530, ..., the
switch that is connected to the selected core circuit. By doing so, electric current
flows between the resistance heaters within the selected core circuit and the current
source 752. When the current source 752 maintains the amount of the electric
20 current at a fixed level, the memory access monitoring unit 951 controls the duty
ratio of the switch to regulate the amount of the time when the electric current is
flowing continuously to the resistance heaters, With this, the average amount of the
electric current flowing to the resistance heaters can be regulated. Alternatively,
when the current source 752 can vary the amount of electric current, the memory
25 access monitoring unit 951 adjusts the amount of the electric current flowing to the
resistance heaters using the current source 752. By doing so, the amount of the
electric current flowing to the resistance heaters is adjusted.
[0078]
33
Note that, instead of measuring the frequency of actual access to the
memory by the memory control unit 730 as above, the memory access monitoring
unit 951 may detect a bandwidth of the external memory MR allocated to each core
circuit, i.e., a bandwidth limit value.
5 [0079]
At the same time as turning one of the switches ON, the memory access
monitoring unit 951 also sets the timer 741 in the frequency control unit 740 to a
preheating time Tth, and starts up the timer 741. For example, when a bandwidth of
the external memory MR allocated to the decoder 701 is at 500 MB/s, 1000 MB/s,
10 and 1500 MB/s, the memory access monitoring unit 951 sets the preheating time Tth
to 2 seconds, 5 seconds, and 10 seconds, respectively. The relationship between
bandwidths of the external memory MR allocated to the selected core circuit and the
preheating time Tth is tabulated and saved in advance in the memory access
monitoring unit 951. When the frequency control unit 740 detects the elapse of the
15 preheating time Tth with the timer 741, it raises the operating frequency of the core
circuit selected by the memory access monitoring unit 951. At this time, the
temperature of transistors on a critical path of the core circuit will be sufficiently
high, and thus the operating speeds of the transistors will be sufficiently high.
Accordingly, the core circuit will reliably have a high operating speed.
20 [0080]
Control of core circuit operating speeds
[0081]
Fig. 15 is a flow chart for a situation where the integrated circuit 900 of
Embodiment 3 of the present invention controls the operating speed of each core
25 circuit. This control is begun when the system control unit 720 determines the
change of a viewing target from a terrestrial digital television broadcasting program
to online video content in response to user operation or a stream parser analysis
result.
34
[0082]
In step 51000, the system control unit 720 detects, from the signal UO from
a remote control or from the stream data VS, a request that the viewing target should
be changed from the terrestrial digital television broadcasting program to online
5 video content. The system control unit 720 then initiates displaying of the content.
In more detail, the system control unit 720 first selects and starts a network interface
circuit from among the core circuit assembly 710, and begins preparations to receive
the video content from a network. The system control unit 720 next stops the
operation of the stream processing circuit in the core circuit assembly 710, which is
10 used for displaying the aforementioned program. The system control unit 720
furthermore causes the memory control unit 730 to change a bandwidth of the
external memory MR that is to be allocated to each core circuit. Subsequently, the
process proceeds to step 51001.
[0083]
15 in step 51001, the memory access monitoring unit 951 monitors requests for
access to the external memory MR received by the memory control unit 730 from
the core circuits 701, 702, 703, ... In particular, the memory access monitoring unit
951 detects the frequency of access to the external memory MR by the decoder 701,
in other words, the bandwidth of the external memory MR allocated to the decoder
20 701. The memory access monitoring unit 951 furthermore checks whether or not the
bandwidth exceeds a predetermined threshold value Bth. If the bandwidth exceeds
the threshold value Bth, the process proceeds to step 51002, and if it does not, the
process repeats step S 1001 again.
[0084]
25 In step 51002, the memory access monitoring unit 951 turns the switch
753A connected to the decoder 701 ON. By doing so, electric current starts to flow
between the current source 752 and the resistance heaters 704 within the decoder
707. Subsequently, the process proceeds to step S1003.
35
[0085]
In step 51003, the memory access monitoring unit 951 retrieves, from the
table, a preheating time Tth to be used when the bandwidth of the external memory
MR allocated to the decoder 701 exceeds the threshold value Bth, and sets the timer
5 741 to the preheating time Tth. The memory access monitoring unit 951 then starts
the timer 741. With this, the timer 741 starts timing. Subsequently, the process
proceeds to step 51004.
[0086]
In step 51004, the frequency control unit 740 monitors the output of the
10 timer 741. When the output shows the elapse of the preheating time Tth from the
moment of startup, the process proceeds to step S 1005.
[0087]
In step S1005, the frequency control unit 740 raises the operating frequency
of the decoder 701. By doing so, the operating speed of the decoder 701 rises.
15 Subsequently, the process proceeds to step S 1006.
[0088]
In step 51006, the temperature monitoring unit 740 monitors the
temperature of the decoder 701 or its surrounding area. If the temperature exceeds
the permissible ranee Llrc. process proceeds to step 51007 If •`he temperature does
20 not exceed the permissible range, the process proceeds to step 51008.
[0089]
In step 51007, the temperature monitoring unit 754 turns the switch 753A
connected to the decoder 701 OFF to stop the electric current flowing to the
resistance heaters 704 within the decoder 701. Alternatively, the temperature
25 monitoring unit 754 may lower the duty ratio of the switch 753A to reduce the
amount of the electric current flowing to the resistance heaters 704 within the
decoder 701. Subsequently, the process proceeds to step 51010.
[0090]
36
In step 5100&, the temperature monitoring unit 754 confirms whether or not
the temperature of the decoder 701 or its surrounding area is below the permissible
range. If the temperature is below the permissible range, the process proceeds to step
51009. If the temperature is within the permissible range, the process proceeds to
5 step 51010.
[0091]
In step S1009, the temperature monitoring unit 754 turns the switch 753A
connectedtothe decoder 701 ON to cause electric current to flow again to the
resistance heaters 704 within the decoder 701. Alternatively, the temperature
10 monitoring unit 754 raises the duty ratio of the switch 753A to increase the amount
of electric current flowing to the resistance heaters 704 within the decoder 701.
Subsequently, the process proceeds to step 51010.
[0092]
In step 51010, the system control unit 720 determines whether or not to
continue operation of each core circuit. If the operation is to be continued, the
process repeats from step 51006. If the operation is to be ceased, the system control
unit 720 ceases the operation of the frequency control unit 740 and heater control
unit 750. With this, the process ends.
[0093]
20 The integrated circuit 900 of Embodiment 3 of the present invention adjusts,
using the resistance heaters, the temperature of a core circuit, in particular the
temperature of transistors on a critical path, to a suitable value in accordance with
the bandwidth of the external memory MR allocated to each core circuit, as shown
above. As a result, the threshold voltages of the transistors are adjusted to a suitable
25 value; therefore it is possible to balance the operating speed and electric power
consumption of the core circuit. For example, changing a viewing target from a
terrestrial digital television broadcast to online video content raises the frequency of
access to the external memory MR by the decoder 701. Alternatively, when the DSP
37
702 decodes an audio stream, the frequency of access to the external memory MR
by the DSP 702 varies with the compression encoding scheme of the audio stream.
With rise of the frequency of access to the external memory MR, the heater control
unit 750 sends electric current to resistance heaters of both the decoder 701 and the
5 DSP 702. By doing so, the temperature of the transistors on critical paths of the
decoder 701 and the DSP 702 increases and accordingly their threshold voltages
decrease and therefore their operating speeds reliably rise. On the other hand, when
the frequency of access to the external memory MR reduces, the heater control unit
750 stops electric current flowing to the resistance heaters of the decoder 701 and
10 the DSP 702. By doing so, the temperature of the transistors on critical paths
decreases, and thus their threshold voltages increase. As a result, leakage current
reduces, and therefore it is possible to suppress the electric power consumption of
the decoder 701 and the DSP 702. To this way, the integrated circuit 900
dynamically controls the operating speeds of the core circuits to achieve both a
15 reduction in electric power consumption and an increase in operating speeds.
[0094]
[Embodiment 41
[0095]
Fig. 16 is a cross-sectional diagram showing the laminated structure of a
20 transistor and its surroundings included in an integrated circuit of Embodiment 4 of
the present invention. This structure differs from the structure of Embodiment I
shown in Fig. 2 in that the resistance heater is formed on a different substrate from
that where the transistor is formed. Other elements are similar to those of
Embodiment 1, and therefore the following explanation will mainly describe the
25 modifications from Embodiment 1. A description of the similar elements may be
found in the explanation about Embodiment 1.
[0096]
Referring to Fig. 16, a first substrate 1110 is stacked on top of a second
38
substrate 1120 in the integrated circuit. The first substrate 1110 includes a first
surface 1111 and second surface 1112 (the upper and lower surfaces, respectively,
shown in Fig. 16) that are substantially parallel to each other. The transistor 100 is
laminated to the first surface 1110 and includes a first diffusion area 101, a second
5 diffusion area 102, a gate oxide film 103, a gate electrode 104, sidewalls 105, a first
contact hole 106, a second contact hole 107, a first trace 108 and a second trace 109.
These elements are similar to those shown in Figs. 1 and 2, and therefore the
detailed explanation about the elements will be found in the explanation about
Embodiment 1.
10 [0097]
Referring further to Fig. 16, the second substrate 1120 includes a third
surface 1121 and fourth surface 1122 (the upper and lower surfaces, respectively,
shown in Fig. 16) that are substantially parallel to each other. The third surface 1121
is bonded to the second surface 1112 of the first substrate 1 110. (Refer to the arrow
15 ARR shown in Fig. 16.) The resistance heater 1130 is laminated to the part of the
third surface 1121 located underneath the transistor 100. The resistance heater 1130
is formed of polysilicon or non-dope silicon. The planar shape of the resistance
heater 1130 is, like that shown in Fig. 1, a long thin rectangle extending in a
direction orthogonal to the gate electrode 140. Furthermore, two resistance heaters
20 1130 are provided to one transistor 100. The third surface 1 121 is covered with an
insulating film 1210. The insulating film 1210 is formed of silicon oxide. The
insulating film 1210 is sandwiched between the third surface 1121 and the second
surface 1112 of the first substrate 1110, electrically isolating them from each other.
One TSV 1131 is formed on the part of the second substrate 1120 facing each
25 longitudinal end of the resistance heater 1130. The TSVs 1131 are filled with
polysilicon. The fourth surface 1122 of the second substrate 1120 is covered with an
interlayer insulating film 1220. Third contact holes 1132 are formed in the interlayer
insulating film 1220, and the ends of the TSVs 1131 are exposed through the third
39
contact holes 1132. Third traces 1133 are connected to the TSVs 1131 through the
third contact holes 1132. The third traces 1133 are formed of aluminum or copper.
When electric current flows to the resistance heater 1130 through the third traces
1133, a comparatively great Joule heat arises, since the resistance value of the
5 resistance heater 1130 is greater than that of the third traces 1133. By doing so, it is
possible to heat the transistor 100, in particular its channel area, by using the
resistance heater 1130.
[0098]
The resistance heaters 1130 are placed underneath those transistors 100
10 which belong to a critical path. This enables those transistors to be selectively heated
so that their temperatures rise higher than those of other transistors. As shown in Fig.
3, generally speaking, transistors under a high temperature condition have lower
threshold voltages than transistors under a low temperature condition. Accordingly,
raising the temperature of transistors on a critical path higher than that of other
15 transistors enables the transistors on the critical path to operate at faster speeds than
the other transistors, even though all the transistors share a common power supply
voltage. Furthermore, by allowing electric current to flow to the resistance heaters
only during the time period when high speed operation is necessary, it is possible to
suppress the increase cielecfric power consumption to the minimum requirement. In
20 this way, by using the structure shown in Fig. 16, it is possible to dynamically adjust
the transistor threshold voltages. Note that detail of the adjustment method is similar
to that of Embodiment 1. Accordingly, the detailed description can be found in the
explanation about Embodiment I.
[0099]
25 Transistor laminating process
[0100]
Figs. 17-19 show the laminating process of the structure shown in Fig. 16.
All of the transistors included in the integrated circuit of Embodiment 4 of the
40
present invention have been laminated with a similar process.
[0101]
Fig. 17A is a cross-sectional diagram showing the process of laminating the
gate oxide films 103 and gate electrodes 104 onto the first surface 111 1 of the first
5 substrate 1110. First the entirety of the first surface 1111 is thermally oxidized to be
covered with a layer of silicon oxide. Next, polysilicon is accumulated on the
entirety of the silicon oxide layer by LPCVD. Following that, the entirety of this
polysilicon layer is coated with a photoresist and exposed to light in the pattern of
the gate electrodes 104 With this, the photoresist is removed from all but the areas
10 where the gate electrodes 104 are to be formed. Next, using the remaining
photoresist as a mask, RIE is performed to remove the superfluous silicon oxide and
polysilicon from the first surface I I11, and then form the gate oxide films 103 and
the gate electrodes 104. Finally, the remaining photoresist is removed,
[0102]
15 Fig. 17B is a cross-sectional diagram showing the process of forming the
diffusion areas. With this process, the gate electrodes 104 are used as a mask, and
impurity ions such as boron or phosphor are infused into the first surface 111 1 of the
first substrate 1110. The arrows IMP shown in Fig. 17B indicate the infusion ion
current. In this way, the diffusion areas 101 and 102 are thinly formed on either side
20 of each of the gate electrodes 104.
[0103]
Fig. 17C is a cross-sectional diagram showing the process of forming the
sidewalls 105 and the interlayer insulating film 201. After the diffusion areas 101
and 102 are formed, first the entirety of the first surface 1111 of the first substrate
25 1110 is covered with a layer of silicon nitride by LPCVD. Next, anisotropic etching
is performed so that the silicon nitride layer remains only on the sides of the gate
oxide films 103 and the gate electrodes 104. By doing so, the sidewalls 105 are
formed. Following that, using the gate electrodes 104 and the sidewalls 105 as a
41
mask, impurity ions such as boron or phosphor are additionally infused into the first
surface I I11. As a result, the thickness of the diffusion areas 101 and 102 increases
on the outer sides of the sidewalls 105. In this way, the sidewalls 105 function as a
spacer to reliably separate the diffusion areas 101 and 102 from the gate electrode
5 104. After the impurity ions are infused, the entirety of the first surface 1111 is
covered with a silicon oxide coating to form the interlayer insulating film 201.
[0104]
Fig. 18A is across-sectional diagram showing the process of forming the
contact holes 106 and 107 in the interlayer insulating film 201. First, the entirety of
10 the interlayer insulating film 201 is covered with a photoresist, and exposed to light
in the pattern of the contact holes 106 and 107. By doing so, parts of the photoresist
are removed from the areas where the contact holes 106 and 107 should be formed,
and then holes appear. Next, using the remaining photoresist as a mask, RIE is
performed to remove parts of the interlayer insulating film 201 which are exposed
15 through the holes of the photoresist and then deepen the holes. Following that, CVD
is used to fill the insides of the holes with aluminium, tungsten, or copper. At this
point, the metal will be protruding out from the upper ends of the holes. Accordingly,
after the holes are filled with the metal, the surface of the interlayer insulating films
201 is polished with ('MP, which removes the metal protruding from the upper ends
20 of the holes to,flatten the surtaee of the interlayer insulating film 201. In this way,
the contact holes 106 and 107 are formed.
[0105]
Fig. 18B is a cross-sectional diagram which shows the process of forming
the multilayer traces 108 and 109. First, the entirety of the interlayer insulating film
25 201 is covered with a silicon oxide layer 202 by CVD. Next, the entirety of the
silicon oxide layer 202 is covered with a photoresist, and is exposed to light in the
pattern of the traces 108 and 109 as indicated by the dotted lines shown in Fig. 1. By
doing so, parts of the photoresist are removed from the areas where the traces 108
42
and 109 should be formed, and then holes appear. Next, using the remaining
photoresist as a mask, RIB is performed to remove the parts of the silicon oxide
layer 202 which are exposed through the holes of the photoresist and then deepen
the holes. Following that, plating or spattering is used to fill the insides of the holes
5 with aluminium or copper. At this point, the metal will be protruding out from the
upper ends of the holes. Accordingly, after the holes are filled with the metal, the
surface of the silicon oxide layer 202 is polished with CNW, which removes the
metal protruding from the upper ends of the holes to flatten the surface of the silicon
oxide layer 202. By doing so, the traces 108 and 109 within the silicon oxide layer
10 202 are formed. After that, each time one of the silicon oxide layers 203 and 204 are
newly laminated, a similar process is repeated. In this way, the multilayer traces
shown in Fig. 18B are formed.
[0106]
Fig. 18C is a cross-sectional diagram showing the process of polishing the
1 5 second surface I 1 12 of the first substrate 1110. After formation of the structure on
the first surface 1111 of the first substrate 1 110 as shown in Fig. 18B is completed,
polishing of the second surface 1112 is carried out with CMP. The arrows CMP
shown in Fig. 18C show the direction in which the thickness of the substrate 1110
changes with the CMI'. The CMP is repeated .several limes while the roughness of
20 the polishing is altered in several steps. With this, the thickness of the first substrate
1110 decreases to a range of several micrometers to several dozens of micrometers.
At this point in time, it is desirable that the thickness of the first substrate 1110 is
made to be narrower compared to the thickness of the substrate 110 shown in Fig.
6A.
25 [0107]
Fig. 19A is a cross-sectional diagram that shows the process of forming the
resistance heaters 1130 on the third surface 1 121 of the second substrate 1120. First,
polysilicon is accumulated on the entirety of the third surface 1121 with LPCVD.
43
Next, the entirety of the polysilicon layer is covered with a photoresist, which is
exposed to light in the pattern of the resistance heaters 1130. By doing so, the
photoresist is removed from all of the polysilicon layer except where the resistance
heaters 1130 should be formed. Next, using the remaining photoresist as a mask,
S RIE is performed to remove the superfluous polysilicon from the third surface 1 121
and then form the resistance heaters 1130. Finally, the remaining photoresist is
removed.
[0108]
Fig. 19B is a cross-sectional diagram showing the process of forming the
10 insulating films 1210 on the third surface 1121 of the second substrate 1120. After
the resistance heaters 1130 are formed, silicon oxide is accumulated by CVD on the
entirety of the third surface 1121 which includes the resistance heaters 1130 to form
the insulating film 1210.
[0109]
15 Fig. 19C is a cross-sectional diagram showing the process of forming the
TSVs 1131 in the second substrate 1120. First, the fourth surface 1122 of the second
substrate 1120 is covered with a photoresist which is exposed to light in the pattern
of the TSVs 1131. As a result, parts of the photoresist are removed from the areas
where the TSVs 1131 are to be formed, and then holes appear- Next, using the
20 remaining photoresist as a mask, RIE is performed to remove parts of the second
substrate 1120 which are exposed through the holes of the photoresist and then form
vias. Following that, after the photoresist is removed from the entirety of the fourth
surface 1122, an insulating film is formed by using CVD to coat the inner surfaces
of the vias with silicon oxide. Subsequently, CVD is further used to fill the vias with
25 polysilicon. At this point, polysilicon will be protruding out from the upper ends of
the vias. Accordingly, after the vias are filled with polysilicon, the fourth surface
1122 is polished with CMP, which removes the polysilicon protruding from the
upper ends of the vias to flatten the fourth surface 1122. In this way, the TSVs 1131
44
are formed.
[0110]
Fig. 19D is a cross-sectional diagram showing the process of forming the
interlayer insulating film 1220 on the fourth surface 1122 of the second substrate
5 1120. After the TSVs 1131 are formed, silicon oxide is accumulated by CVD on the
entirety of the fourth surface 1122 to form the interlayer insulating film 1220.
[0111]
Fig. 19E is across-sectional diagram showing the process of forming the
third contact holes 1132 and the third traces 1133 in the interlayer insulating film
10 1220. First, the entirety of the interlayer insulating film 1220 is covered with a
photoresist, and exposed to light in the pattern of the third contact holes 1132 and
the third traces 1133. By doing so, parts of the photoresist are removed from the
areas where the third contact holes 1132 and the third traces 1133 should be formed,
and then holes appear. Next, using the remaining photoresist as a mask, RTE is
15 performed to remove parts of the interlayer insulating film 1220 which are exposed
through the holes of the photoresist and then deepen the holes. Following that, CVD
is used to fill the insides of the holes with aluminium,,tungsten , or copper. At this
point, the metal will be protruding out from the upper ends ofthe holes. Accordingly,
after the holes are filled with the metal, the surface of the interlayer insulatine, film
20 1220 is polished with CMP, which removes the polysilicon protruding from the
upper ends of the holes to flatten the surface of the interlayer insulating film 1220.
In this way, the third contact holes 1132 and the third traces 1133 are formed.
[0112]
Embodiment 4 of the present ventio differs from Embodiment 1 in that
25 the transistors and resistance heaters are laminated to different substrates , and both
the substrates are bonded together. Accordingly, the resistance heaters are laminated
with a different process to that of the transistors, and thus there is no risk that the
transistors are exposed to etching solution and ion current used during the process of
45
laminating the resistance heaters. For this reason, the production method of
Embodiment 4, whilst including processes more than that of Embodiment 1, can
improve the reliability of the transistors.
[0113]
5 [Embodiment 5]
[0114]
Fig. 20 is a cross-sectional diagram showing the laminated structure of a
transistor and its surrounding area included in an integrated circuit of Embodiment 5
of the present invention. This structure differs from the structure of Embodiment 4
10 shown in Fig. 16 in that a thermal insulator is placed around a transistor and
resistance heaters. Since other elements are similar, the following will mostly
describe changes from Embodiment 4. A description of the similar elements can be
found in the explanation about Embodiment 4.
[0115]
15 Referring to Fig. 20, the transistor 100 is surrounded by a first thermal
insulator 130. The first thermal insulator 130 is formed on the outside of both the
diffusion areas 101 and 102 in such a way as to separate-the first substrate 1 110. The
first thermal insulator 130 is formed of material, such as silicon oxide, that has lower
conductivity than silicon and aluminium, and does not pollute peripheral malcrials_
20 The first thermal insulator 130 may alternatively be a region where air ornanomaterials
have been trapped in the substrate 110. With the first thermal
insulator 130, the area of each transistor 100 is isolated from the outside not just
electrically, but thermally.
[0116]
25 Referring further to Fig. 20, the resistance beater 1130 is surrounded by a
second thermal insulator 1140. The second thermal insulator 1140 is formed
between the resistance beater 1130 and its surrounding areas in such a way as to
separate the second substrate 1120. The second thermal insulator 1140 is formed of
46
material, such as silicon oxide, that has lower conductivity than silicon and
aluminium, and does not pollute peripheral materials. The thermal insulator 1140
may alternatively be a region where air or nanomaterials have been trapped in the
second substrate 1120. With the first substrate 1 110 and second substrate 1120 being
5 bonded together, the first thermal insulator 130 and second thermal insulator 1140
are connected to each other. Joule heat produced by the resistance heater 1130 is
blocked by the first thermal insulator 130 and second insulator 1140, and thus hardly
propagates to the outside. Accordingly, it is possible to further improve the
efficiency in selectively raising the temperature of the transistor 100 by using the
10 resistance heater 1130.
[0117]
Transistor laminating process
[0118]
The laminating process of the structure shown in Fig . 20 is shown in Figs.
15 21-23. All transistors included in the integrated circuit of Embodiment 5 of the
present invention have been laminated with a similar process. The process shown in
Figs. 21 -23 differs from the process shown in Figs . 17-19 in that a step of forming
thermal insulators is included. Other steps are similar.
[0119]
20 Fig. 21A is a cross-sectional diagram showing the process of forming the
first thermal insulators 130 in the first substrate 1110. First , the first surface 1111 of
the first substrate 1110 is covered with a photoresist 1201 and exposed to light in the
pattern of the first thermal insulators 130. Then, parts of the photoresist 1201 are
removed from the areas where the first thermal insulators 130 are to be formed, and
25 thus holes 1202 appear . Next, using the remaining photoresist 1201 as a mask, RIE
is performed to remove the parts of the first substrate 1110 which are exposed
through the holes 1202 in the photoresist and then form trench-shaped vias 1203
(see the dotted line sections of Fig. 21A). The arrows R13 show in Fig. 21A indicate
47
ion current used in the RIE. Subsequently, after the photoresist 1201 are removed
from the entirety of the first surface 111 1, the insides of the vias 1203 are filled with
silicon oxide by CVD. At this point, silicon oxide will be protruding out of the upper
ends of the vias 1203. Accordingly, after the vial 1203 are filled with silicon oxide,
5 the first surface 1111 is polished with CMP, which removes the silicon oxide
protruding from the upper ends of the vias 1203 and to flatten the first surface 1111.
In this way, the first thermal insulators 130 are formed.
[0120]
Fig. 21B is a cross-sectional diagram showing the process of laminating the
10 gate oxide films 103 and gate electrodes 104 onto the first surface 1111 of the first
substrate 1110. The process shown in Fig. 21B is similar to that shown in Fig. 17A.
After the first thermal insulators 130 are formed, first the entirety of the first surface
I I I I is thermally oxidized to be covered with a layer of silicon oxide. Next,
polysilicon is accumulated on the entirety of the silicon oxide layer by LPCVD.
15 Following that, the entirety of this polysilicon layer is coated with a photoresist and
exposed to light in the pattern of the gate electrodes 104, and thus the photoresist is
removed from all but the areas where the gate electrodes 104 are to be formed.
Furthermore, using the remaining photoresist as a mask, RIC is performed to remove
the superfluous silicnri oxide and polysilicon from the first surface 1111, and then
20 form the gate oxide films 103 and the gate electrodes 104. Finally, the remaining
photoresist is removed.
[0121]
Fig. 21C is a cross-sectional diagram showing the process of forming the
diffusion areas. The process shown in Fig. 21C is similar to that shown in Fig. 178.
25 With this process, the gate electrodes 104 are used as a mask, and impurity ions such
as boron or phosphor are infused into the first surface 1111 of the first substrate
1110, and then the diffusion areas 101 and 102 are thinly formed on either side of
each of the gate electrodes 104.
48
[0122]
Fig. 21D is a cross-sectional diagram showing the process of forming the
sidewalls 105 and the interlayer insulating film 201. The process shown in Fig. 21D
is similar to that shown in Fig. 17C. After the diffusion areas 101 and 102 are
5 formed, first the entirety of the first surface 1111 of the first substrate 1110 is
covered with a layer of silicon nitride by LPCVD. Next, anisotropic etching is
performed so that the silicon nitride layer remains only on the sides of the gate oxide
films 103 and the gate electrodes 104. By doing so, the sidewalls 105 are formed.
Following that, using the gate electrodes 104 and the sidewalls 105 as a mask,
10 impurity ions such as boron or phosphor are additionally infused into the first
surface 111 l . As a result, the thickness of the diffusion areas 101 and 102 increases
on the outer sides of the sidewalls 105. After the impurity ions are infused, the
entirety of the first surface 1111 is covered with a silicon oxide coating to form the
intcrlaycr insulating film 201.
15 [0123]
Fig. 22A is a cross-sectional diagram showing the process of forming the
contact holes 106 and 107 in the interlayer insulating film 201. The process shown
in Fig. 22A is similar to that shown in Fig. iSA. First, the entirety of the interlayer
insulating film 201 is covered with a photoresist, and exposed to light in the fiattern
20 of the contact holes 106 and 107, and then holes are formed. Next, using the
remaining photoresist as a mask, RME is performed to remove parts of the interlayer
insulating film 201 which are exposed through the holes of the photoresist and then
deepen the holes. Following that, CVD is used to fill the insides of the holes with
aluminium, tungsten, or copper. Subsequently, the surface of the interlayer
25 insulating film 201 is polished with CMP, which removes the polysilicon protruding
from the upper ends of the holes to flatten the surface of the interlayer insulating
film 201. In this way, the contact holes 106 and 107 are formed.
[0124]
49
Fig. 22B is a cross-sectional diagram which shows the process of forming
the multilayer traces 108 and 109. The process shown in Fig. 22B is similar to that
shown in Fig. 18B. First, the entirety of the interlayer insulating film 201 is covered
with a silicon oxide layer 202 by CVD. Next, the entirety of the silicon oxide layer
5 202 is covered with a photoresist, and is exposed to light in the pattern of the traces
108 and 109 as indicated by the dotted lines shown in Fig. 1, and then holes are
formed. Next, using the remaining photoresist as a mask, RIE is performed to
remove the parts of the silicon oxide layer 202 which are exposed through the holes
of the photoresist and then deepen the holes. Following that, plating or spattering is
10 used to fill the insides of the holes with aluminium or copper. Subsequently, the
surface of the silicon oxide layer 202 is polished with CMP, which removes the
metal protruding from the upper ends of the holes to flatten the surface of the silicon
oxide layer 202. By doing so, the traces 108 and 109 within the silicon oxide layer
202 are formed. After that, each time one of the silicon oxide layers 203 and 204 are
15 laminated, a similar process is repeated. In this way, the multilayer traces shown in
Fig. 22B are formed.
[0125]
Fig. 22C is a cross-sectional diagram showing the process of polishing the
second surface 1112 of the first substrate 1110. The process shown in Fig. 22C is
20 similar to that shown in Fig. 18C. After formation of the structure of the first surface
1 I 1 1 of the first substrate 11 10 shown in Fig. 22B is completed, polishing of the
second surface 1112 is carried out with CMP. With this, the thickness of the first
substrate 1110 decreases to a range of several micrometers to several dozens of
micrometers. As a result, the first thermal insulators 130 are exposed at the second
25 surface 1112 as shown in Fig. 22C. At this point in time, it is desired that the
thickness of the first substrate 1110 is made to be narrower compared to the
thickness of the substrate 110 shown in Fig. 13A.
[0126]
50
Fig. 23A is a cross-sectional diagram that shows the process of forming the
resistance heaters 1130 on the third surface 1121 of the second substrate 1120. The
process shown in Fig. 23A is similar to that shown in Fig. 19A. First, polysilicon is
accumulated on the entirety of the third surface 1121 with LPCVD. Next, the
5 entirety of the polysilicon layer is covered with a photoresist, which is exposed to
light in the pattern of the resistance heaters 1130 and thus photoresist is removed
from all of the polysilicon layer except where the resistance heaters 1130 should be
formed. Next, using the remaining photoresist as a mask, RIE is performed to
remove the superfluous polysilicon from the third surface 1121 and then form the
10 resistance heaters 1130. Finally, the remaining photoresist is removed.
[0127]
Fig. 23B is a cross-sectional diagram showing the process of forming the
insulating film 1210 on the third surface 1121 of the second substrate 1120. The
process shown in Fig. 23B is similar to that shown in Fig. 19B. After the resistance
15 heaters 1130 are formed, silicon oxide is accumulated by CVD on the entirety of the
third surface 1121 which includes the resistance heaters 1130 to form the insulating
film 1210.
[0128]
Fig. 23C is a cross-sectional diagram showing the process of forming the
20 second thermal insulator 1140 in the second substrate 1120. First, the entirety of the
insulating film 1210 is covered with a photoresist and exposed to light in the pattern
of the second thermal insulator 1140. By doing so, a part of the photoresist is
removed from the area where the second thermal insulator 1140 should be formed,
and then a hole appears. Next, using the remaining photoresist as a mask, RIE is
25 performed to remove the parts of both the insulating film 1210 and second substrate
1120 which are exposed through the holes of the photoresist and then form a
trench-shaped via. Subsequently , after the photoresist is removed from the entirety
of the insulating layer 1210, the inside of the via is filled with silicon oxide by CVD.
51
At this point, silicon oxide will be protruding out of the upper end of the via.
Accordingly, after the via is filled with silicon oxide, the surface of the insulating
layer 1210 is polished with CMP, which removes the silicon oxide protruding from
the upper end of the via to flatten the surface of the insulating layer 1210. In this
5 way, the second thermal insulator 1140 is formed.
[0129]
Fig. 23D is a cross-sectional diagram showing the process of forming the
TSVs 1131i n the second substrate 1120. The process shown in Fig . 23D is similar
to that shown in Fig. 19C. First, the fourth surface 1122 of the second substrate 1120
10 is covered with a. photoresist which is exposed to light in the pattern of the TSVs
1131, and then holes are formed . Next, using the remaining photoresist as a mask,
RIE is performed to remove the parts of the second substrate 1120 which are
exposed through the holes of the photoresist and then form vial. Following that,
after the photoresist is removed from the entirety of the fourth surface 1122, an
15 insulating films is formed by using CVD to coat the inner surfaces of the vial with
silicon oxide . Subsequently, CVD is further used to fill the vial with polysilicon.
After that, the fourth surface 1122 is polished with , CMP, which removes the
polysilicon protruding from the upper end of the via to flatten the fourth surface
1122. In this way, the TSVs 1 131 are. formed.
20 [0130]
Fig. 23E is a cross-sectional diagram showing the process of forming the
interlayer insulating films 1220 on the fourth surface 1122 of the second substrate
1120. The process shown in Fig. 23E is similar to that shown in Fig. 19D. After the
TSVs 1131 are formed, silicon oxide is accumulated by CVD on the entirety of the
25 fourth surface 1 122 to form the interlayer insulating film 1220.
[0131]
Fig. 23F is a cross-sectional diagram showing the process of forming the
third contact holes 1132 and the third traces 1133 in the interlayer insulating film
52
1220. The process shown in Fig. 23F is similar to that shown in Fig. 19E. First, the
entirety of the interlayer insulating film 1220 is covered with a photoresist, and
exposed to light in the pattern of the third contact holes 1132 and the third traces
1133, and then holes are formed. Next, using the remaining photoresist as a mask,
5 RIE is performed to remove the parts of the interlayer insulating film 1220 which
are exposed through the holes of the photoresist and then deepen the holes.
Following that, CHID is used to fill the insides of the holes with aluminium, tungsten,
or copper. Subsequently, the surface of the interlayer insulating film 1220 is
polished with CMP, which removes the metal protruding from the upper ends of the
10 holes to flatten the surface of the interlayer insulating film 1220. In this way, the
third contact holes 1132 and the third traces 1133 are formed.
[0132]
Modifications
[0133]
15 In the structures shown in Figs. 1, 2, 9 , 10, 16 and 20, the individual
transistors are equipped with the resistance heaters- Alternatively , a plurality of
transistors may share a resistance heater. In the structures shown in Figs . 9, 10 and
20, the thermal insulators surround the individual transistors . Alternatively, a block
comprising a plurality of transistors, or the entirety of a critical path may be
20 surrounded by a connecting thermal insulator.
[0134]
In the structures shown in Figs. 1, 2, 9, 10, 16 and 20, the transistors are a
MOS transistor. Alternatively, the transistors may be a bipolar transistor. As shown
in Fig. 3, the control of the present invention may be applied to any transistor that
25 has the characteristic of lowering its threshold voltage with a rise in temperature.
[0135]
The temperature detection unit '760 shown in Figs. 7 and 14 detects the
temperature of each core circuit or its surrounding area. Alternatively, the
53
temperature detection unit 760 may detect only the temperature of a single part of
the integrated circuit 700 or 900. In this case, the temperature monitoring unit 754
may estimate the temperature of each core circuit from the temperature of the single
part detected by the temperature detection unit 760 and the distance between the
5 single part and each core circuit.
[Industrial Applicability]
[0136]
The present invention relates to technology for controlling operation speeds
of semiconductor integrated circuits, and as described above, places resistance
10 heaters across a substrate from transistors to adjust the temperature of the transistors
and thus controls the threshold voltages of the transistors. The present invention
therefore clearly demonstrates industrial applicability.
[Reference Signs List]
[0137]
1 5 100 Transistor
101 First diffusion area
102 Second dffusion area
103 Gate oxide film
104 Gate electrode
20 105 Sidewall
106 First ontact hole
107 Second ontact hole
108 First trace
109 Second trace
25 110 Substrate
111 First sarface
112 Second surface
120 Resistance heater
54
121 TSV
122 Third contact hole
123 Third trace
201-204 Interlayer insulating film
205 Insulating film

CLAIMS
1. An integrated circuit comprising:
a substrate including a first surface and a second surface that are
substantially parallel to each other;
5 an electrode laminated onto the first surface;
two diffusion areas disposed within the substrate by an electrode to form
one transistor with the electrode; and
aresistance heater located on an area of the second surface across the
substrate from the electrode, the resistance heater configured to produce heat by
10 allowing electric current to flow.
2. The integrated circuit of claim 1, further comprising
a thermal insulator located within the substrate and surrounding the two
diffi.ision areas to prevent external leakage of heat from the two diffusion areas.
15
3. The integrated circuit of claim 1, wherein
the transistor belongs to a critical path of the integrated circuit.
4. The integrated circuit of claim 1, wherein
20 operating speed of the transistor rises due to the resistance heater heating the
transistor.
5. The integrated circuit of claim 4, wherein
the transistor is a MOS transistor.
25
6. The integrated circuit of claim 1, further comprising
a heater control circuit located on the substrate and including a current
source configured to supply electric current to the resistance heater, the heater
56
control circuit configured to adjust an amount of electric current flowing between
the current source and the resistance heater.
7. The integrated circuit of claim 6, wherein
5 the heater control circuit further includes a switch to adjust the amount of
electric current supplied to the resistance heater by allowing or preventing flow of
electric current between the current source and the resistance heater.
8. The integrated circuit of claim 6, wherein
10 the heater control circuit allows electric current to flow to the resistance
heater only while the transistor is operating.
9. The integrated circuit of claim 6, wherein
the heater control circuit alters the amount of electric current applied to the
resistance heater in accordance with a use case of the integrated circuit,
10. The integrated circuit of claim 6, wherein
the heater control circuit adjusts the amount of electric current applied to the
resistance heater according to bandwidth of an external memory connected to the
20 integrated circuit.
11. The integrated circuit of claim 6, further comprising
a temperature detection circuit configured to detect a temperature of an area
surrounding the transistor, wherein
25 the heater control circuit adjusts length of a period of time during which
electric current is allowed to flow continuously to the resistance heater according to
the temperature detected by the temperature detection circuit.
57
12. The integrated circuit of claim 6, further comprising
a temperature detection circuit configured to detect a temperature of an area
surrounding the transistor , wherein
the heater control circuit adjusts the amount of electric current allowed to
5 flow to the resistance heater according to the temperature detected by the
temperature detection circuit.
13. An integrated circuit comprising:
a first substrate including a first surface and second surface that are
10 substantially parallel to each other;
an electrode laminated onto the first surface;
two diffusion areas disposed within the first substrate in the vicinity of the
electrode to form one transistor with the electrode;
a second substrate bonded to the second surface; and
15 a resistance heater located on an area of the second substrate opposite to an
area of the second surface across the first substrate from the electrode and
configured to produce heat by allowing electric current to flow.
14. The integrated circuit of claim 13, further comprising
20 a thermal insulator surrounding the two diffusion areas within the first
substrate to prevent external leakage of heat from the two diffusion areas.
15. The integrated circuit of claim 13, wherein
the transistor belongs to a. critical path of the integrated circuit.
25
16. The integrated circuit of claim 13, wherein
operating speed of the transistor rises by the resistance heater heating the
transistor.
58
17. The integrated circuit of claim 16, wherein
the transistor is a MOS transistor.
5 18. The integrated circuit of claim 13, further comprising
a heater control circuit located on one of the first substrate and the second
substrate and including a current source configured to supply electric current to the
resistance heater, the beater control circuit configured to adjust an amount of electric
current flowing between the current source and the resistance heater.
10
19. The integrated circuit of claim 18, wherein
the heater control circuit further includes a switch to adjust the amount of
electric current applied to the resistance heater by allowing or preventing flow of
electric current between the current source and the resistance heater.
15
20. The integrated circuit of claim 18, wherein
the heater control circuit allows electric current to flow to the resistance
heater only while the transistor is operating.
20 21. The integrated circuit of claim 18, wherein
the heater control circuit alters the amount of electric current applied to the
resistance heater in accordance with a use case of the integrated circuit.
22. The integrated circuit of claim 18, wherein
25 the heater control circuit adjusts the amount of electric current applied to the
resistance heater according to bandwidth of an external memory connected to the
integrated circuit.
59
23. The integrated circuit of claim 18, further comprising
a temperature detection circuit configured to detect the temperature of an
area surrounding the transistor, wherein
the heater control circuit adjusts a length of the period of time during which
5 electric current is allowed to flow continuously to the resistance heater according to
the temperature detected by the temperature detection circuit. _
24. The integrated circuit of claim 18, further comprising
a temperature detection circuit configured to detect a temperature of an area
10 surrounding the transistor, wherein
the heater control circuit adjusts the amount of electric current allowed to
flow continuously to the resistance heater according to the temperature detected by
the temperature detection circuit.